Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
164 Input/Output (I/O) Ports MOTOROLA
Input/Output (I/O) Ports
NON-DISCLOSURE AGREEMENT REQUIRED
12.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[5:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Address: $0004
Bit 7654321Bit 0
Read: 0 0
DDRA5 DDRA4 DDRA3
0
DDRA1 DDRA0
Write:
Reset:00000000
= Unimplemented
Figure 12-3. Data Direction Register A (DDRA)