Datasheet
Input/Output (I/O) Ports
Port A
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Input/Output (I/O) Ports 163
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logic level on the PTA2 pin. When the IRQ function is disabled, these
instructions will behave as if the PTA2 pin is a logic 1. However, reading
bit 2 of PTA will read the actual logic level on the pin.
12.3.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six
port A pins.
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
AWUL — Auto Wake-up Latch Data Bit
This is a read-only bit which has the value of the auto wake-up
interrupt request latch. The wake-up request signal is generated
internally (see 14.4.4 Auto Wake-up Interrupt Request). There is no
PTA6 port nor any of the associated bits such as PTA6 data register,
pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard
interrupt control enable register (KBIER) enable the port A pins as
external interrupt pins (see Section 14. Keyboard Interrupt Module
(KBI)).
Address: $0000
Bit 7654321Bit 0
Read: 0 AWUL
PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
Write:
Reset: Unaffected by reset
Additional Functions:
KBI5 KBI4 KBI3 KBI2 KBI1 KBI0
= Unimplemented
Figure 12-2. Port A Data Register (PTA)