Datasheet

Analog-to-Digital Converter (ADC)
Input/Output Registers
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Analog-to-Digital Converter (ADC) 159
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11.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
11.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 11-2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
Address: $003E
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after reset
= Unimplemented
Figure 11-4. ADC Data Register (ADR)
Address: $003F
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0
00000
Write:
Reset:00000000
= Unimplemented
Figure 11-5. ADC Input Clock Register (ADICLK)