Datasheet

Timer Interface Module (TIM)
Input/Output Registers
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Timer Interface Module (TIM) 149
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In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Address: $0026 TCH0H
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
Address: $0027 TCH0L
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Indeterminate after reset
Address: $0029 TCH1H
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
Address: $02A TCH1L
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Indeterminate after reset
Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L)