Datasheet

Timer Interface Module (TIM)
Input/Output Registers
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Timer Interface Module (TIM) 147
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ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
NOTE: After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
Table 10-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X0 0 0
Output preset
Pin under port control;
initial output level high
X1 0 0
Pin under port control;
initial output level low
00 0 1
Input capture
Capture on rising edge only
0 0 1 0 Capture on falling edge only
00 1 1
Capture on rising
or falling edge
01 0 1
Output
compare
or PWM
Toggle output on compare
0 1 1 0 Clear output on compare
0 1 1 1 Set output on compare
1X 0 1
Buffered
output
compare or
buffered PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare