Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
140 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM)
NON-DISCLOSURE AGREEMENT REQUIRED
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
10.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. See 7.9.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
10.9 Input/Output Signals
Port A shares two of its pins with the TIM. The two TIM channel I/O pins
are PTA0/TCH0 and PTA1/TCH1.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTA0/TCH0 can be configured as
a buffered output compare or buffered PWM pin.