Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
118 Monitor ROM (MON) MOTOROLA
Monitor ROM (MON)
NON-DISCLOSURE AGREEMENT REQUIRED
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is V
DD
or V
SS
), then startup port pin
requirements and conditions, (PTA1/PTA4) are not in effect. This is to
reduce circuit requirements when performing in-circuit programming.
NOTE: If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial power-on reset (POR). Once the
part has been programmed, the traditional method of applying a voltage,
V
TST
, to IRQ must be used to enter monitor mode.
The computer operating properly (COP) module is disabled in monitor
mode based on these conditions:
• If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ
.
• If monitor mode was entered with V
TST
on IRQ (condition set 1),
then the COP is disabled as long as V
TST
is applied to IRQ.
NOTE: The PTA0 pin must be at logic 1 (pullup) during chip power up to enter
monitor mode properly.
Figure 9-4 shows a simplified diagram of the monitor mode entry when
the reset vector is blank and just 1 x V
DD
voltage is applied to the IRQ
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four. No external clock is required if IRQ = 0 since
chip clock will be drive by internal clock generator.
Enter monitor mode with pin configuration shown in Figure 9-1 by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security bytes
(see 9.5 Security). After the security bytes, the MCU sends a break
signal (10 consecutive logic 0s) to the host, indicating that it is ready to
receive a command.