Datasheet

ManualsBrandsFreescale Manuals6800 MicrocontrollersMicrocontroller DIL-8

WWW.MOTOROLA.COM/SEMICONDUCTORS

M68HC08

Microcontrollers

NON-DISCLOSURE AGREEMENT REQUIRED

MC68HC908QY4/D

9/2002

MC68HC908QY4

Data Sheet

MC68HC908QT4

MC68HC908QY2

MC68HC908QT2

MC68HC908QY1

MC68HC908QT1

Summary of content (230 pages)

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M68HC08 Microcontrollers MC68HC908QY4/D 9/2002 WWW.MOTOROLA.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D
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R E Q U I R E D Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
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Revision History Date Revision Level September, 2002 N/A Description Initial release Page Number(s) N/A N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Revision History MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 4 MOTOROLA
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Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 43 Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 45 Section 5. Configuration Register (CONFIG) . . . . . . . . . 55 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 59 Section 7. System Integration Module (SIM) . . . . . . . . .
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List of Sections R E Q U I R E D Section 16. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 195 Section 17. Break Module (BREAK) . . . . . . . . . . . . . . . 201 Section 18. Electrical Specifications. . . . . . . . . . . . . . . 211 Section 19. Mechanical Specifications . . . . . . . . . . . . . 223 N O N - D I S C L O S U R E A G R E E M E N T Section 20. Ordering Information . . . . . . . . . . . . . . . . .
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1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.
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Table of Contents A G R E E M E N T R E Q U I R E D Section 4. FLASH Memory (FLASH) 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 FLASH Page Erase Operation . .
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6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.9 Opcode Map . . . . . . . . . . . . . . . . . . .
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Table of Contents R E Q U I R E D 7.7.2 7.7.2.1 7.7.2.2 7.7.2.3 7.7.3 7.7.4 7.7.5 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .91 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . .91 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . .92 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 110 8.8 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.9 Input/Output (I/O) Registers . . . . . . . . . . . .
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Table of Contents A G R E E M E N T R E Q U I R E D 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.5.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 134 10.5.3.
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Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 157 11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 159 Section 12. Input/Output (I/O) Ports 12.1 Contents . . . . . . . . . .
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Table of Contents R E Q U I R E D Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 A G R E E M E N T 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.4.
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.4.
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Table of Contents A G R E E M E N T R E Q U I R E D Section 18. Electrical Specifications 18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.5 Thermal Characteristics . . . .
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Section 20. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 N O N - D I S C L O S U R E A G R E E M E N T 20.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Table of Contents MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 18 Table of Contents MOTOROLA
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Title Page 1-1 1-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 36 4-1 4-2 4-3 4-4 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH Programming Flowchart . . . .
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List of Figures N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Figure Title Page 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . . 91 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .
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Page 10-8 10-9 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 149 11-1 11-2 11-3 11-4 11-5 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . .157 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures Title Page 17-3 17-4 17-5 17-6 17-7 17-8 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 205 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .206 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .206 Break Auxiliary Register (BRKAR) . . . . . . . . . . . . . . . . . . . . . 207 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 208 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .
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Title Page 1-1 1-2 1-3 Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Function Priority in Shared Pins . . . . . . . . . . . . . . . . . . . . . . . .32 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4-1 Examples of Protect Start Address. . . . . . . . . . . . . . . . . . . . . . 54 6-1 6-2 Instruction Set Summary . . . . . . .
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List of Tables Title Page 10-1 10-2 10-3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 147 11-1 11-2 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.
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R E Q U I R E D General Description 1.3 Features Features include: • High-performance M68HC08 CPU core • Fully upward-compatible object code with M68HC05 Family • 5-V and 3-V operating voltages (VDD) • 8-MHz internal bus operation at 5 V, 4-MHz at 3 V • Trimmable internal oscillator A G R E E M E N T – 3.
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• 5 or 13 bidirectional input/output (I/O) lines and one input only: – Six shared with keyboard interrupt function and ADC – Two shared with timer channels – One shared with external interrupt (IRQ) – Eight extra I/O lines on 16-pin package only – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an individual bit basis R E Q U I R E D General Description Features 6-bit keyboard interrupt with wakeup feature (KBI) • Low-voltage inhibit (LVI) module f
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General Description R E Q U I R E D • MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages: – 8-pin PDIP – 8-pin SOIC A G R E E M E N T Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD)
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D VDD PTB POWER SUPPLY VSS DDRB PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA3/RST/KBI3 CPU CONTROL PTA PTA2/IRQ/KBI2 ALU ACCUMULATOR PTA5/OSC1/AD3/KBI5 CLOCK GENERATOR 68HC08 CPU PTA4/OSC2/AD2/KBI4 CPU REGISTERS INDEX REGISTER SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE STACK POINTER 8-BIT ADC General Description PROGRAM COUNTER CONDITION CODE REGISTER V 1 1 H I N Z C BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER M
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R E Q U I R E D General Description VDD 1 8 VSS PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 2 7 PTA0/AD0/TCH0/KBI0 6 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 3 6 PTA1/AD1/TCH1/KBI1 5 PTA2/IRQ/KBI2 PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2 VDD 1 8 VSS PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 3 PTA3/RST/KBI3 4 8-PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC A G R E E M E N T 8-PIN ASSIGNMENT MC68HC908QT1 PDIP/SOIC VDD 1 16 VSS PTB0 PTB7 2 15 PTB0 14 PTB1 PTB6 3 14 PTB1 4 13 PTA0/T
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1.6 Pin Functions Table 1-2 provides a description of the pin functions. Table 1-2.
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1.7 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE: Upon reset all pins come up as input ports regardless of the priority table. Table 1-3.
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2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 33 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Memory $0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $007F RESERVED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $27FF UNIMPLEMENTED 9984 BYTES UNIMPLEMENTED 9984 BYTES $0100 ↓ $27FF $2800 ↓ $2DFF AUXILIARY ROM 1536 BYTES AUXILIARY ROM 1536 BYTES $2800 ↓ $2DFF $2E00 ↓ $EDFF UNIMPLEMENTED 49152 BYTES $2E00 UNIMPLEMENTED 51712 BYTES ↓ $F7FF $EE00 ↓ $FDFF FLASH MEMORY MC68HC908QT4 AND MC68HC908QY4 4096 BYTES $FE00 BREAK STATU
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Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Memory Addr. Register Name $0000 Read: Port A Data Register (PTA) Write: See page 163. Reset: $0001 Read: Port B Data Register (PTB) Write: See page 167. Reset: $0002 Unimplemented $0003 Unimplemented $0004 $0005 $0006 ↓ $000A Read: Data Direction Register A (DDRA) Write: See page 164.
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Register Name Bit 7 6 5 4 3 2 Read: Keyboard Status and $001A Control Register (KBSCR) Write: See page 183. Reset: 0 0 0 0 KEYF 0 $001B Read: Keyboard Interrupt Enable Register (KBIER) Write: See page 184. Reset: $001C Unimplemented $001D Read: IRQ Status and Control Register (INTSCR) Write: See page 176.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Memory Addr. $0023 $0024 Register Name Read: TIM Counter Modulo Register High (TMODH) Write: See page 144. Reset: Read: TIM Counter Modulo Register Low (TMODL) Write: See page 144. Reset: Read: TIM Channel 0 Status and $0025 Control Register (TSC0) Write: See page 145. Reset: $0026 $0027 Read: TIM Channel 0 Register High (TCH0H) Write: See page 149. Reset: Read: TIM Channel 0 Register Low (TCH0L) Write: See page 149.
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Read: Oscillator Status Register (OSCSTAT) Write: See page 111. Reset: $0037 Unimplemented Read: $0038 Oscillator Trim Register Read: (OSCTRIM) Write: See page 112.
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A G R E E M E N T R E Q U I R E D Memory Addr. Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 BDCOP 0 0 0 0 0 0 0 0 BCFE R R R R R R R 0 IF5 IF4 IF3 0 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 2 $FE05 (INT2) Write: See page 176. Reset: IF14 0 0 0 0 0 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 3 $FE06 (INT3) Write: See page 176.
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Register Name Read: LVIOUT LVI Status Register (LVISR) Write: See page 199. Reset: 0 $FE0C 4 3 2 1 Bit 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 R R R R R R R R Reserved for FLASH Test R R R R R R R R BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 0 0 0 0 0 0 0 0 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 1 0 0 0 0 0 0 0 R R R R R R R R Unimplemented Unimplemented Read: FLASH Block Protect Register (FLBPR) Write: See page 53.
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Memory . R E Q U I R E D Table 2-1.
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3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 Introduction This section describes the 128 bytes of random-access memory (RAM). 3.3 Functional Description Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Random-Access Memory (RAM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 44 Random-Access Memory (RAM) MOTOROLA
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4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.7 FLASH Program Operation. . . . . . . . . . . .
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4.3 Functional Description The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section.
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Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Write: Reset: 0 0 0 0 Figure 4-1. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed.
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4.5 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the block to be erased.
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NOTE: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tnvs (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, tErase (minimum 4 ms). 7. Clear the ERASE and MASS bits. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). 8. Wait for a time, tnvh1 (minimum 100 µs). 9. Clear the HVEN bit. 10.
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FLASH Memory (FLASH) R E Q U I R E D 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4. Wait for a time, tnvs (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, tpgs (minimum 5 µs). A G R E E M E N T 7. Write data to the FLASH address being programmed(1). 8. Wait for time, tPROG (minimum 30 µs).
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NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are shown in 4.9 FLASH Block Protect Register.
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FLASH Memory (FLASH) R E Q U I R E D Algorithm for Programming a Row (32 Bytes) of FLASH Memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tnvs A G R E E M E N T 5 SET HVEN BIT 6 WAIT FOR A TIME, tpgs 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, tPROG N O N - D I S C L O S U R E 9 COMPLETED PROGRAMMING THIS ROW? Y N 10 11 12 NOTES: The time between each
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4.9 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. $FFBE Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 U U U U U U U U A G R E E M E N T Read: Write: Reset: U = Unaffected by reset.
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FLASH Memory (FLASH) N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Table 4-1. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range $00–$B8 The entire FLASH memory is protected. $B9 (1011 1001) $EE40 (1110 1110 0100 0000) $BA (1011 1010) $EE80 (1110 1110 1000 0000) $BB (1011 1011) $EEC0 (1110 1110 1100 0000) $BC (1011 1100) $EF00 (1110 1111 0000 0000) and so on...
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5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2).
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Configuration Register (CONFIG) R E Q U I R E D Most of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU) it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytime. NOTE: The CONFIG registers are one-time writable by the user after each reset.
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Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 SSREC STOP COPD Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 Write: Reset: 0 0 0 0 U 0 0 0 POR: 0 0 0 0 0 0 0 0 R = Reserved U = Unaffected R E Q U I R E D Configuration Register (CONFIG) Functional Description 1 = COP reset short cycle = (213 – 24) × BUSCLKX4 0 = COP reset long cycle = (218 – 24) × BUSCLKX4 COPRS (In STOP Mode) — Auto Wake-up Period Selection Bit 1 = Auto wake-up short cycle = (29) × INTRCOSC 0 = Auto wake-up long cy
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Configuration Register (CONFIG) R E Q U I R E D LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5-V mode 0 = LVI operates in 3-V mode NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.
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6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4.3 Stack Pointer . .
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6.
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0 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.1 Accumulator Bit 7 6 5 4 3 2 1 N O N - D I S C L O S U R E The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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Central Processor Unit (CPU) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 6-3. Index Register (H:X) 6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF.
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Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
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Central Processor Unit (CPU) R E Q U I R E D V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag A G R E E M E N T The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation.
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The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.
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6.6.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 6.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
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V H I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP A ← (A) + (M) + (C) Add with Carry IMM DIR EXT – IX2 IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT – IX2 IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP Add without Carry AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM AIX #opr Add Immed
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N O N - D I S C L O S U R E A G R E E M E N T Description Effect on CCR V H I N Z C BGE opr Branch if Greater Than or Equal To (Signed Operands) BGT opr Branch if Greater Than (Signed Operands) BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 BHCS rel Branch if Half Carry Bit Set BHI rel Branch if Higher BHS rel PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 Cycles Operation Opcode Source Form Operand Table 6-1.
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dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 BRSET n,opr,rel Branch if Bit n in M Set Mn ← 1 DIR DIR DIR – – – – – – DIR DIR DIR DIR DIR (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BSET n,opr Set Bit n in M BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel – – – – – – REL AD rr 4 DIR IMM IMM – – – – – – IX1+ IX+ SP1 31 41 51 61 71 9E61 dd rr ii rr ii
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N O N - D I S C L O S U R E A G R E E M E N T Description V H I N Z C CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A (X) – (M) (A) 10 DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP
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#opr opr opr opr,X opr,X ,X opr,SP opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP Load H:X from M LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right MOV MOV MOV MOV Move opr,opr opr,X+ #opr,opr X+,opr MUL 0 – – – IMM DIR 45 55 X ← (M) IMM DIR EXT 0 – – – IX2 IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE 0 DIR INH – – INH IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 C DIR INH – – 0 INH IX1 IX SP1 34 dd 44 54 64 ff 74 9E64 ff 4 1 1 4 3 5 C b
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N O N - D I S C L O S U R E A G R E E M E N T ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Effect on CCR Description V H I N Z C Rotate Left through Carry C b7 b0 Cycles Operation Operand Source Form Opcode Table 6-1.
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SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte TAP Transfer A to CCR CCR ← (A) INH 84 2 TAX Transfer A to X X ← (A) – – – – – – INH 97 1 TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – –
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.3 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . .79 7.4 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 79 7.4.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.4.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . .
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System Integration Module (SIM) A G R E E M E N T R E Q U I R E D 7.7.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 93 7.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.9 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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System Integration Module (SIM) Introduction MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) ÷2 VDD RESET PIN LOGIC INTERNAL CLOCKS CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (F
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D System Integration Module (SIM) Addr. $FE00 Register Name Read: Break Status Register (BSR) Write: See page 99. Reset: Bit 7 6 5 4 3 2 R R R R R R 1 Bit 0 SBSW R Note 1 0 0 0 0 0 0 0 0 1. Writing a logic 0 clears SBSW. Read: SIM Reset Status Register (SRSR) Write: See page 96.
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7.4 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 7-3. FROM OSCILLATOR BUSCLKX4 FROM OSCILLATOR BUSCLKX2 SIM COUNTER ÷2 BUS CLOCK GENERATORS SIM Figure 7-3. SIM Clock Signals 7.4.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 7.4.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D System Integration Module (SIM) 7.4.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4 cycles. See 7.8.2 Stop Mode. In wait mode, the CPU clocks are inactive.
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Reset Type Number of Cycles Required to Set PIN POR 4163 (4096 + 64 + 3) All others 67 (64 + 3) BUSCLKX2 RST ADDRESS BUS VECT H VECT L PC Figure 7-4. External Reset Timing 7.5.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 7-5).
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System Integration Module (SIM) ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET Figure 7-6. Sources of Internal Reset NOTE: For POR resets, the SIM cycles through 4096 BUSCLKX4 cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
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R E Q U I R E D System Integration Module (SIM) Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES BUSCLKX4 BUSCLKX2 $FFFE $FFFF Figure 7-7. POR Recovery 7.5.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources.
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7.5.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.5.2.
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7.6.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 7.6.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter.
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R E Q U I R E D System Integration Module (SIM) 7.7 Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 7.7.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 7-8 flow charts the handling of system interrupts.
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R E Q U I R E D System Integration Module (SIM) Exception Control FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? IRQ INTERRUPT? A G R E E M E N T NO YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR N O N - D I S C L O S U R E (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 7-8.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D System Integration Module (SIM) MODULE INTERRUPT I BIT ADDRESS BUS DATA BUS DUMMY SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 7-9. Interrupt Entry MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 7-10. Interrupt Recovery 7.7.
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INT1 BACKGROUND ROUTINE PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 7-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry.
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7.7.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 7-3.
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System Integration Module (SIM) Exception Control R E Q U I R E D 7.7.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IF5 IF4 IF3 0 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved A G R E E M E N T Figure 7-12. Interrupt Status Register 1 (INT1) IF1 and IF3–IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D System Integration Module (SIM) 7.7.2.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-14. Interrupt Status Register 3 (INT3) IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3.
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Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited.
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System Integration Module (SIM) R E Q U I R E D A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
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The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode.
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System Integration Module (SIM) R E Q U I R E D STOP RECOVERY PERIOD BUSCLKX4 INTERRUPT ADDRESS BUS STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 7-19. Stop Mode Recovery from Interrupt N O N - D I S C L O S U R E A G R E E M E N T 7.9 SIM Registers The SIM has three memory mapped registers. Table 7-4 shows the mapping of these registers. Table 7-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 SRSR User $FE03 BFCR User 7.9.
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System Integration Module (SIM) SIM Registers PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor M
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R E Q U I R E D System Integration Module (SIM) 7.9.2 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Write: A G R E E M E N T Reset: 0 R = Reserved Figure 7-21.
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The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Read: Bit 7 6 5 4 3 2 R R R R R R 1 SBSW Write: Note 1 Reset: 0 R = Reserved Bit 0 R 1. Writing a logic 0 clears SBSW. Figure 7-22. Break Status Register (BSR) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D System Integration Module (SIM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 100 System Integration Module (SIM) MOTOROLA
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8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . 103 8.4.1.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Oscillator Module (OSC) 8.2 Introduction The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system integration module (SIM) and the computer operating properly module (COP). The BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller.
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The internal oscillator will generate a clock of 12.8 MHz typical (INTCLK) resulting in a bus speed (internal clock ÷ 4) of 3.2 MHz. 3.2 MHz came from the maximum bus speed guaranteed at 3 V which is 4 MHz. Since the internal oscillator will have a ±25% tolerance (pre-trim), then the +25% case should not allow a frequency higher than 4 MHz: 3.2 MHz + 25% = 4 MHz Figure 8-2 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register.
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8.4.1.2 Internal to External Clock Switching When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following steps: 1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the crystal circuit start more robustly. 2. Set CONFIG2 bits OSCOPT[1:0] according to Table 8-2.
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In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I/O functions on the pin. 8.4.3 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected.
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Oscillator Module (OSC) R E Q U I R E D FROM SIM TO SIM BUSCLKX4 XTALCLK TO SIM BUSCLKX2 ÷2 SIMOSCEN MCU OSC1 OSC2 RS(1) N O N - D I S C L O S U R E A G R E E M E N T RB X1 C1 C2 Note 1. RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. See Section 18. Electrical Specifications for component value requirements. Figure 8-1. XTAL Oscillator External Connections 8.4.
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R E Q U I R E D Oscillator Module (OSC) Oscillator Module Signals OSCRCOPT TO SIM 0 BUSCLKX4 BUSCLKX2 1 SIMOSCEN EXTERNAL RC EN OSCILLATOR RCCLK ÷2 1 0 PTA4 I/O PTA4 OSC2EN MCU OSC1 VDD REXT PTA4/BUSCLKX4 (OSC2) See Section 18. Electrical Specifications for component value requirements. Figure 8-2. RC Oscillator External Connections 8.5 Oscillator Module Signals The following paragraphs describe the signals that are inputs to and outputs from the oscillator module. 8.5.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Oscillator Module (OSC) 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output. For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has no effect. For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to Table 1-3.
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8.5.6 Internal Oscillator Clock (INTCLK) INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 12.8 MHz, but it can be also trimmed using the oscillator trimming feature of the OSCTRIM register (see 8.4.1.1 Internal Oscillator Trimming). 8.5.7 Oscillator Out 2 (BUSCLKX4) BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the SIM module and is used to determine the COP cycles. 8.5.
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8.6.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module. 8.6.2 Stop Mode The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4. 8.7 Oscillator During Break Mode The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break state. 8.8 CONFIG2 Options Two CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0.
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1. Oscillator status register (OSCSTAT) 2. Oscillator trim register (OSCTRIM) 8.9.1 Oscillator Status Register The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources Address: $0036 Bit 7 6 5 4 3 2 1 R R R R R R ECGON 0 0 0 0 0 0 0 Read: Bit 0 ECGST Write: Reset: R 0 = Reserved Figure 8-3.
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8.9.2 Oscillator Trim Register (OSCTRIM) Address: $0038 Bit 7 6 5 4 3 2 1 Bit 0 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM71 TRIM0 1 0 0 0 0 0 0 0 Read: Write: Reset: Figure 8-4. Oscillator Trim Register (OSCTRIM) TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits A G R E E M E N T R E Q U I R E D Oscillator Module (OSC) N O N - D I S C L O S U R E These read/write bits change the size of the internal capacitor used by the internal oscillator.
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9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4.1 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4.2 VTST Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4.3 Data Format . . . . . .
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9.
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Table 9-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: • If $FFFE and $FFFF does not contain $FF (programmed state): – The external clock is 9.8304 MHz – IRQ = VTST • If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.
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R E Q U I R E D Monitor ROM (MON) VDD N.C. VDD 0.1 µF MAX232 1 + 1 µF 16 9.8304 MHz CLOCK + 3 4 C2+ 1 µF 15 C1– + 1 µF VDD C1+ 5 C2– A G R E E M E N T RST (PTA3) + V+ 1 µF 10 kΩ* 3 PTA1 N.C. PTA4 N.C. 2 VDD IRQ (PTA2) V– 6 1 µF 10 kΩ 74HC125 5 6 + DB9 2 OSC1 (PTA5) 7 10 8 9 74HC125 3 2 PTA0 4 VSS 1 5 * Value not critical Figure 9-1. Monitor Mode Circuit (External Clock, No High Voltage) VDD N.C. RST (PTA3) VDD N O N - D I S C L O S U R E 0.
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VDD VDD 10 kΩ* RST (PTA3) VDD 0.1 µF 0.1 µF 9.8304 MHz CLOCK 1 µF + 3 VTST 1 µF C2+ V+ + 3 1 kΩ 2 IRQ (PTA2) VDD 1 µF 7 10 8 9 10 kΩ* PTA4 9.1 V 10 kΩ + VSS 74HC125 5 6 DB9 2 1 µF V– 6 5 C2– PTA1 1 µF 15 C1– + 4 10 kΩ* 16 C1+ 74HC125 3 2 PTA0 4 1 5 * Value not critical Figure 9-3. Monitor Mode Circuit (External Clock, with High Voltage) Table 9-1.
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Monitor ROM (MON) R E Q U I R E D If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage is VDD or VSS), then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR).
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IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 9-4. Low-Voltage Monitor Mode Entry Flowchart 9.4.1 Forced Monitor Mode If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. The MENRST module monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($FF).
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Monitor ROM (MON) R E Q U I R E D The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration register. See Section 5. Configuration Register (CONFIG). The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will automatically force the MCU to come back to the forced monitor mode.
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START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 9-5. Monitor Data Format 9.4.4 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 9-6. Break Transaction 9.4.
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9.4.6 Commands The monitor ROM firmware uses these commands: A G R E E M E N T R E Q U I R E D Monitor ROM (MON) • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command.
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Monitor ROM (MON) Functional Description R E Q U I R E D A brief description of each monitor mode command is given in Table 9-4 through Table 9-9. Table 9-4.
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Monitor ROM (MON) R E Q U I R E D Table 9-5. WRITE (Write Memory) Command Description Write byte to memory Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence A G R E E M E N T FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 9-6.
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Monitor ROM (MON) Functional Description Description Write to last address accessed + 1 Operand Single data byte Data Returned None Opcode R E Q U I R E D Table 9-7. IWRITE (Indexed Write) Command $19 Command Sequence IWRITE IWRITE DATA A G R E E M E N T FROM HOST DATA ECHO N O N - D I S C L O S U R E A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map.
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Monitor ROM (MON) R E Q U I R E D Table 9-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order Opcode $0C Command Sequence A G R E E M E N T FROM HOST READSP SP HIGH READSP ECHO SP LOW RETURN Table 9-9.
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The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
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R E Q U I R E D Monitor ROM (MON) VDD 4096 + 32 CGMXCLK CYCLES COMMAND BYTE 8 BYTE 2 BYTE 1 RST FROM HOST PA0 4 BREAK 2 1 COMMAND ECHO 1 BYTE 8 ECHO Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. 1 BYTE 2 ECHO A G R E E M E N T FROM MCU 4 1 BYTE 1 ECHO 256 BUS CYCLES (MINIMUM) Figure 9-10.
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10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 10.5.2 Input Capture . . . . . . . .
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10.2 Introduction This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 is a block diagram of the TIM. 10.
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10.5 Functional Description Figure 10-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
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A G R E E M E N T R E Q U I R E D Timer Interface Module (TIM) Addr. $0020 $0021 $0022 $0023 $0024 N O N - D I S C L O S U R E $0025 $0026 $0027 $0028 Register Name Bit 7 6 5 TOIE TSTOP 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 TIM Status and Control Read: Register Write: (TSC) See page 141. Reset: TOF 0 0 1 0 0 0 0 0 Read: TIM Counter Register High (TCNTH) Write: See page 144.
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$002A TIM Channel 1 Read: Register High Write: (TCH1H) See page 149. Reset: TIM Channel 1 Read: Register Low Write: (TCH1L) See page 149. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset = Unimplemented Figure 10-2. TIM I/O Register Summary (Continued) 10.5.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs.
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10.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
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Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last.
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Timer Interface Module (TIM) R E Q U I R E D OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE N O N - D I S C L O S U R E A G R E E M E N T Figure 10-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments.
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NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine.
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R E Q U I R E D Timer Interface Module (TIM) NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 10.5.4.
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Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 10.10.4 TIM Channel Status and Control Registers. 10.6 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests.
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If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.8 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 7.9.2 Break Flag Control Register.
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Timer Interface Module (TIM) Input/Output Registers R E Q U I R E D 10.10 Input/Output Registers TIM status and control register (TSC) • TIM control registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 10.10.
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Timer Interface Module (TIM) R E Q U I R E D TOF — TIM Overflow Flag Bit A G R E E M E N T This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect.
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Table 10-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64 1 1 1 Not available 10.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
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Timer Interface Module (TIM) Read: $0021 TCNTH Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: Address: $0022 Read: TCNTL Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 10-5. TIM Counter Registers (TCNTH:TCNTL) 10.10.
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• Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Address: $0025 TSC0 Bit 7 6 5 4 3 2 1 Bit 0 CH0
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Timer Interface Module (TIM) R E Q U I R E D Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
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When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 10-3.
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Timer Interface Module (TIM) R E Q U I R E D TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow.
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In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Timer Interface Module (TIM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 150 Timer Interface Module (TIM) MOTOROLA
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11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.4.3 Conversion Time . . . . . .
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Analog-to-Digital Converter (ADC) 11.3 Features Features of the ADC module include: • 4 channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock Figure 11-1 provides a summary of the input/output (I/O) registers. Addr.
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voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 11-2 shows a block diagram of the ADC.
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A G R E E M E N T R E Q U I R E D Analog-to-Digital Converter (ADC) 11.4.1 ADC Port I/O Pins PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC.
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11.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 11.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 11.6 Low-Power Modes The following subsections describe the ADC in low-power modes. 11.6.
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11.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 11.7 Input/Output Signals The ADC module has four channels that are shared with I/O port A. ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC module. 11.
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Address: $003C Bit 7 Read: 6 5 4 3 2 1 Bit 0 AIEN ADCO CH4 CH3 CH2 CH1 CH0 0 0 1 1 1 1 1 COCO Write: Reset: 0 = Unimplemented Figure 11-3. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever ADSCR is written or whenever the ADR is read. Reset clears this bit.
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Analog-to-Digital Converter (ADC) R E Q U I R E D CH[4:0] — ADC Channel Select Bits CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels. The five select bits are detailed in Table 11-1. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. A G R E E M E N T The ADC subsystem is turned off when the channel select bits are all set to 1.
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11.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: $003E 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Indeterminate after reset = Unimplemented Figure 11-4. ADC Data Register (ADR) 11.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
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Analog-to-Digital Converter (ADC) R E Q U I R E D Table 11-2.
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12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . 166 12.4 Port B . . . . . . . . . . . . . . . . . .
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A G R E E M E N T R E Q U I R E D Input/Output (I/O) Ports Addr. Register Name $0000 Port A Data Register (PTA) See page 163. $0001 Port B Data Register (PTB) See page 167. Data Direction Register A $0004 (DDRA) See page 164. Data Direction Register B $0005 (DDRB) See page 168.
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logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins.
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12.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: $0004 Read: Bit 7 6 0 0 5 4 3 DDRA5 DDRA4 DDRA3 0 0 0 2 1 Bit 0 DDRA1 DDRA0 0 0 0 Write: A G R E E M E N T R E Q U I R E D Input/Output (I/O) Ports Reset: 0 0 0 = Unimplemented Figure 12-3.
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Figure 12-4 shows the port A I/O logic. READ DDRA ($0004) PTAPUEx INTERNAL DATA BUS WRITE DDRA ($0004) RESET DDRAx 30 k WRITE PTA ($0000) PTAx PTAx R E Q U I R E D Input/Output (I/O) Ports Port A TO KEYBOARD INTERRUPT CIRCUIT Figure 12-4. Port A I/O Circuit NOTE: Figure 12-4 does not apply to PTA2 N O N - D I S C L O S U R E When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin.
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R E Q U I R E D Input/Output (I/O) Ports 12.3.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each if the six port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output.
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DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA5–DDRA0 Pin PTA5–PTA0(3) 0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin PTA5–PTA0(3) X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5) 1. X = don’t care 2. I/O pin pulled to VDD by internal pullup. 3. Writing affects data register, but does not affect input. 4. Hi-Z = high impedance 5. Output does not apply to PTA2 12.4 Port B Port B is an 8-bit general purpose I/O port.
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12.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Read: Write: A G R E E M E N T R E Q U I R E D Input/Output (I/O) Ports Reset: Figure 12-7.
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DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRB7–DDRB0 Pin PTB7–PTB0(3) 1 X Output DDRB7–DDRB0 Pin PTB7–PTB0 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. 12.4.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins.
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Input/Output (I/O) Ports These read/write bits are software programmable to enable pullup devices on port B pins 1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0 0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit. Table 12-3 summarizes the operation of the port B pins. Table 12-3.
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13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 175 13.
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13.4 Functional Description IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A 0 disables the IRQ function and IRQ will assume the other shared functionalities. A1 enables the IRQ function. A logic 0 applied to the external interrupt pin can latch a central processur unit (CPU) interrupt request. Figure 13-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch.
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When the interrupt pin is both falling-edge and low-level triggered, the CPU interrupt request remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
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13.5 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE1 set, both of the following actions must occur to clear IRQ: A G R E E M E N T R E Q U I R E D External Interrupt (IRQ) • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
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When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E). 13.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state.
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External Interrupt (IRQ) R E Q U I R E D Address: $001D Read: Bit 7 6 5 4 3 0 0 0 0 IRQF1 1 Bit 0 IMASK1 MODE1 0 0 ACK1 Write: Reset: 2 0 0 0 0 0 0 = Unimplemented Figure 13-3. IRQ Status and Control Register (INTSCR) A G R E E M E N T IRQF1 — IRQ Flag This read-only status bit is high when the IRQ interrupt is pending.
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14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 182 14.4.3 Keyboard Interrupt Enable Register . .
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Keyboard Interrupt Module (KBI) 14.
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Keyboard Interrupt Module (KBI) Functional Description R E Q U I R E D 14.4 Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK KBI0 VDD D KEYF Q SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST A G R E E M E N T TO PULLUP ENABLE . . . CLR Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER) independently enables or disables each port A pin as a keyboard interrupt pin.
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Keyboard Interrupt Module (KBI) A G R E E M E N T R E Q U I R E D A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low.
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Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt input stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred.
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Keyboard Interrupt Module (KBI) R E Q U I R E D To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit.
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6 5 4 3 2 0 0 0 0 KEYF 0 Bit 0 IMASKK MODEK 0 0 ACKK Write: Reset: 1 0 0 0 0 0 0 = Unimplemented Figure 14-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wake-up. Reset clears the KEYF bit.
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R E Q U I R E D Keyboard Interrupt Module (KBI) 14.4.3 Keyboard Interrupt Enable Register The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wake-up to operate as a keyboard interrupt input. Address: $001B Bit 7 Read: 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 Write: A G R E E M E N T Reset: 0 Figure 14-4.
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14.4.4 Auto Wake-up Interrupt Request COPRS (FROM CONFIG1) VDD TO PTA READ, BIT 6 1 = DIV 29 SHORT 0 = DIV 214 OVERFLOW 32KHz EN CLK E RST AWUL Q AWUIREQ R TO KBI INTERRUPT LOGIC (SEE Figure 14-2) A G R E E M E N T INT RC OSC D CLRLOGIC RESET CLEAR ACKK (CGMXCLK) BUSCLKX4 CLK RST RESET ISTOP RESET AWUIE Figure 14-5.
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Keyboard Interrupt Module (KBI) N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was “borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no MCU clock available) in stop mode.
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The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Keyboard Interrupt Module (KBI) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 188 Keyboard Interrupt Module (KBI) MOTOROLA
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15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.1 BUSCLKX4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.3 Power-On Reset . . . . . .
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15.3 Functional Description SIM MODULE RESET VECTOR FETCH RESET STATUS REGISTER COP TIMEOUT CLEAR STAGES 5–12 CLEAR ALL STAGES INTERNAL RESET SOURCES(1) SIM RESET CIRCUIT 12-BIT SIM COUNTER BUSCLKX4 A G R E E M E N T R E Q U I R E D Computer Operating Properly (COP) COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE CLEAR COP COUNTER N O N - D I S C L O S U R E COP RATE SELECT (COPRS FROM CONFIG1) 1. See Section 7.
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A COP reset pulls the RST pin low for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR). See 7.9.1 SIM Reset Status Register. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 15.4 I/O Signals The following paragraphs describe the signals shown in Figure 15-1. 15.4.
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R E Q U I R E D Computer Operating Properly (COP) 15.4.4 Internal Reset An internal reset clears the SIM counter and the COP counter. 15.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. N O N - D I S C L O S U R E A G R E E M E N T 15.4.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Section 5. Configuration Register (CONFIG).
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15.6 Interrupts The COP does not generate CPU interrupt requests. 15.7 Monitor Mode The COP is disabled in monitor mode when VTST is present on the IRQ pin. The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 15.8.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter. 15.8.2 Stop Mode Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Computer Operating Properly (COP) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 194 Computer Operating Properly (COP) MOTOROLA
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16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.4.3 Voltage Hysteresis Protection .
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A G R E E M E N T R E Q U I R E D Low-Voltage Inhibit (LVI) 16.3 Features Features of the LVI module include: • Programmable LVI reset • Programmable power consumption • Selectable LVI trip voltage • Programmable stop mode operation 16.4 Functional Description Figure 16-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See Section 5. Configuration Register (CONFIG).
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After a power-on reset, the LVI’s default mode of operation is 3 volts. If a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip point to 5-V operation. If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset while the VDD supply is not above the VTRIPR for 5-V mode, the microcontroller unit (MCU) will immediately go into reset. The next time the LVI releases the reset, the supply will be above the VTRIPR for 5-V mode.
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16.4.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. 16.4.
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The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while LVI resets have been disabled. Address: $FE0C Bit 7 Read: LVIOUT 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 Write: Reset: 0 = Unimplemented R = Reserved Figure 16-2.
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R E Q U I R E D Low-Voltage Inhibit (LVI) 16.6 LVI Interrupts The LVI module does not generate interrupt requests. 16.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 16.7.
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17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 204 17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .204 17.4.3 TIM During Break Interrupts . . . . . . . .
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17.3 Features Features of the break module include: • Accessible input/output (I/O) registers during the break Interrupt • Central processor unit (CPU) generated break interrupts • Software-generated break interrupts • Computer operating properly (COP) disabling during break interrupts 17.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM).
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Break Module (BREAK) Functional Description R E Q U I R E D ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] CONTROL BKPT (TO SIM) 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 208. Reset: $FE02 Read: Break Auxiliary Register (BRKAR) Write: See page 207. Reset: Read: Break Flag Control Register (BFCR) Write: See page 209.
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R E Q U I R E D Break Module (BREAK) 17.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 7.9.2 Break Flag Control Register and the Break Interrupts subsection for each module. 17.4.
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Break Module (BREAK) Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) 17.5.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits.
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R E Q U I R E D Break Module (BREAK) 17.5.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE09 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Read: Write: A G R E E M E N T Reset: Figure 17-4.
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17.5.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Address: $FE02 Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Bit 0 BDCOP R E Q U I R E D Break Module (BREAK) Break Module Registers Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 17-6.
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17.5.4 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Bit 7 6 5 4 3 2 R R R R R R Read: A G R E E M E N T R E Q U I R E D Break Module (BREAK) 1 Bit 0 SBSW Write: Note(1) Reset: 0 R = Reserved R 1. Writing a logic 0 clears SBSW. Figure 17-7.
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Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Write: Reset: 0 R = Reserved Figure 17-8. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 17.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Break Module (BREAK) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 210 Break Module (BREAK) MOTOROLA
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18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.6 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 214 18.7 5-V Control Timing . . . . . . . . . . . . .
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18.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 18.6 5-V DC Electrical Characteristics and 18.9 3-V DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) A G R E E M E N T R E Q U I R E D Electrical Specifications Symbol Value Unit Supply voltage VDD –0.3 to +6.
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Operating temperature range Operating voltage range Symbol Value Unit TA – 40 to +125 – 40 to +85 – 40 to +125 – 40 to +85 °C VDD 5 V ± 10% 3 V ± 10% V 18.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Electrical Specifications 18.6 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0–PTA5 only VOH Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.
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Min Typ(2) Max Unit Low-voltage inhibit reset, trip rising voltage VTRIPR 4.00 4.30 4.60 V Low-voltage inhibit reset/recover hysteresis VHYS — 100 — mV 1. V DD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs.
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18.8 5-V Oscillator Characteristics Characteristic Symbol Min Typ Max Unit Internal oscillator frequency fINTCLK — 12.
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18.9 3-V DC Electrical Characteristics Typ(2) Max VDD –0.3 VDD – 1.0 VDD – 0.6 — — — — — — Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0–PTA4 only VOH Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.0 mA, PTA0-PTA5 only VOL — — — — — — 0.3 1.0 0.6 V Input high voltage PTA0–PTA5, PTB0–PTB7, RST, IRQ, OSC1 VIH 0.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Low-voltage inhibit reset, trip rising voltage VTRIPR 2.50 2.65 2.80 V Low-voltage inhibit reset/recover hysteresis VHYS — 60 — mV 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3.
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Electrical Specifications 3-V Oscillator Characteristics Symbol Min Typ Max Unit Internal oscillator frequency fINTCLK — 12.
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R E Q U I R E D Electrical Specifications 18.12 Typical Supply Currents 14 12 10 8 IDD (mA) 6 4 5.5 V 3.3 V 2 0 A G R E E M E N T 0 1 2 3 4 5 fOP OR fBUS (MHz) 6 7 8 9 Figure 18-3. Typical Operating IDD, with All Modules Turned On (25°C) 2 1.75 1.50 1.25 IDD (mA) 1 0.75 0.5 5.5 V 3.3 V N O N - D I S C L O S U R E 0.25 0 0 1 2 3 4 fOP OR fBUS (MHz) 5 6 7 8 Figure 18-4.
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Symbol Min Max Unit Comments Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V — Input voltages VADIN VSS VDD V — Resolution BAD 8 8 Bits — Absolute accuracy AAD ± 0.5 ± 1.5 LSB Includes quantization ADC internal clock fADIC 0.5 1.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Electrical Specifications 18.14 Memory Characteristics Characteristic Symbol Min Max Unit VRDR 1.
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19.1 Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 19.3 8-Pin Plastic Dual In-Line Package (Case #626) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 19.4 8-Pin Small Outline Integrated Circuit Package (Case #968) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 19.5 16-Pin Plastic Dual In-Line Package (Case #648D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A G R E E M E N T R E Q U I R E D Mechanical Specifications 19.3 8-Pin Plastic Dual In-Line Package (Case #626) 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 -B1 4 DIM A B C D F G H J K L M N F -A- NOTE 2 L C J -TN SEATING PLANE D STYLE 1: 1. AC IN 2. DC + IN 3. DC - IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC M K G H 0.13 (0.
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Mechanical Specifications 16-Pin Plastic Dual In-Line Package (Case #648D) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.25 (0.010). 6. ROUNDED CORNERS OPTIONAL. 9 -B1 8 F L C S -T- SEATING PLANE K H G M J D 16 PL 0.25 (0.
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R E Q U I R E D Mechanical Specifications 19.7 16-Pin Thin Shrink Small Outline Package (Case #948F) 16X K REF 0.10 (0.004) M T U 0.15 (0.006) T U V S S S K K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N A G R E E M E N T 0.25 (0.010) 0.15 (0.006) T U S A -V- M NOTES: 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: MILLIMETER. 6. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.
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Section 20. Ordering Information 20.1 Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 A G R E E M E N T 20.2 R E Q U I R E D Data Sheet — MC68HC908QY4 20.2 Introduction This section contains ordering numbers for MC68HC908QY1, MC68HC908QY2, MC68HC908QY4, MC68HC908QT1, MC68HC908QT2, and MC69HC908QT4. 20.
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Ordering Information MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 228 Ordering Information MOTOROLA
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N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D
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R E Q U I R E D A G R E E M E N T HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.