Board Users Guide

MPC5200B Users Guide, Rev. 1
B-6 Freescale Semiconductor
13.15.8 SDMA Task Control 0 Register—MBAR + 0x121C ........................................................................... 13-9
13.15.9 SDMA Task Control 2 Register—MBAR + 0x1220.......................................................................... 13-10
15.2.10 Interrupt Status Register (0x14) — ISR ............................................................................................. 13-19
13.15.11 SDMA Task Control 6 Register—MBAR + 0x1228...........................................................................13-11
13.15.12 SDMA Task Control 8 Register—MBAR + 0x122C ......................................................................... 13-12
13.15.13 SDMA Task Control A Register—MBAR + 0x1230......................................................................... 13-12
13.15.14 SDMA Task Control C Register—MBAR + 0x1234 ......................................................................... 13-13
13.15.15 SDMA Task Control E Register—MBAR + 0x1238 ......................................................................... 13-13
13.15.16 SDMA Initiator Priority 0 Register—MBAR + 0x123C.................................................................... 13-14
13.15.17 SDMA Initiator Priority 4 Register—MBAR + 0x1240 .................................................................... 13-15
13.15.18 SDMA Initiator Priority 8 Register—MBAR + 0x1244 .................................................................... 13-15
13.15.19 SDMA Initiator Priority 12 Register—MBAR + 0x1248 .................................................................. 13-16
13.15.20 SDMA Initiator Priority 16 Register—MBAR + 0x124C.................................................................. 13-17
13.15.21 SDMA Initiator Priority 20 Register—MBAR + 0x1250 .................................................................. 13-18
13.15.22 SDMA Initiator Priority 24 Register—MBAR + 0x1254 .................................................................. 13-18
13.15.23 SDMA Initiator Priority 28 Register—MBAR + 0x1258 .................................................................. 13-19
13.15.24 SDMA Requestor MuxControl—MBAR + 0x125C .......................................................................... 13-20
13.15.25 SDMA task Size0—MBAR + 0x1260 ............................................................................................... 13-22
13.15.26 SDMA task 0 & task Size 1 map........................................................................................................ 13-23
13.15.27 SDMA Reserved Register 1—MBAR + 0x1268................................................................................ 13-23
13.15.28 SDMA Reserved Register 2—MBAR + 0x126C............................................................................... 13
-24
13.15.29 SDMA Debug Module Comparator 1, Value1 Register—MBAR + 0x1270..................................... 13-24
13.15.30 SDMA Debug Module Comparator 2, Value2 Register—MBAR + 0x1274..................................... 13-24
13.15.31 SDMA Debug Module Control Register—MBAR + 0x1278 ............................................................ 13-25
13.15.32 SDMA Debug Module Status Register—MBAR + 0x127C .............................................................. 13-27
Section
14.5 FEC Registers—MBAR + 0x3000........................................................................................................... 14-10
14.5.1 FEC ID Register—MBAR + 0x3000 ..................................................................................................14-11
14.5.2 FEC Interrupt Event Register—MBAR + 0x3004 ............................................................................. 14-12
14.5.3 FEC Interrupt Enable Register—MBAR + 0x3008............................................................................ 14-14
14.5.4 FEC Rx Descriptor Active Register—MBAR + 0x3010 ................................................................... 14-14
14.5.5 FEC Tx Descriptor Active Register—MBAR + 0x3014.................................................................... 14-15
14.5.6 FEC Ethernet Control Register—MBAR + 0x3024........................................................................... 14-16
14.5.7 FEC MII Management Frame Register—MBAR + 0x3040 .............................................................. 14-17
14.5.8 FEC MII Speed Control Register—MBAR + 0x3044 ....................................................................... 14-18
14.5.9 FEC MIB Control Register—MBAR + 0x3064................................................................................. 14-19
14.5.10 FEC Receive Control Register—MBAR + 0x3084 ........................................................................... 14-20
14.5.11 FEC Hash Register—MBAR + 0x3088 ............................................................................................. 14-21
14.5.12 FEC Tx Control Register—MBAR + 0x30C4 ................................................................................... 14-21
14.5.13 FEC Physical Address Low Register—MBAR + 0x30E4 ................................................................. 14-22
14.5.14 FEC Physical Address High Register—MBAR + 0x30E8 ................................................................ 14-23
14.5.15 FEC Opcode/Pause Duration Register—MBAR + 0x30EC.............................................................. 14-23
14.5.16 FEC Descriptor Individual Address 1 Registe—MBAR + 0x3118.................................................... 14-24
14.5.17 FEC Descriptor Individual Address 2 Register—MBAR + 0x311C.................................................. 14-24
14.5.18 FEC Descriptor Group Address 1 Register—MBAR + 0x3120 ........................................................ 14-25
14.5.19 FEC Descriptor Group Address 2 Register—MBAR + 0x3124 ........................................................ 14-25
14.5.20 FEC Tx FIFO Watermark Register—MBAR + 0x3144..................................................................... 14-26
Section 14.6 FIFO Interface .......................................................................................................................................... 14-27
Section 14.7 FEC Tx FIFO Data Register—MBAR + 0x31A4.................................................................................... 14-28