Board Users Guide

MPC5200B Users Guide, Rev. 1
20-24 Freescale Semiconductor
Functional Description
Figure 20-8. J1850 VPW Active Symbols
• Invalid Active Bit
If the active to passive transition beginning the next data bit or symbol occurs between the passive to active transition beginning the
current data bit or symbol and T
rva2(Min)
, the current bit would be invalid. See Figure 20-8(1).
• Valid Active Logic One
If the active to passive transition beginning the next data bit or symbol occurs between T
rva2(Min)
and T
rva2(Max)
, the current bit
would be considered a logic one. See Figure 20-8(2).
• Valid Active Logic Zero
If the active to passive transition beginning the next data bit or symbol occurs between T
rva1(Min)
and T
rva1(Max)
, the current bit
would be considered a logic zero. See Figure 20-8(3).
• Valid SOF Symbol
If the active to passive transition beginning the next data bit or symbol occurs between T
rva3(Min)
and T
rva3(Max)
, the current symbol
would be considered a valid SOF symbol. See Figure 20-8(4).
Figure 20-9. J1850 VPW BREAK Symbol
T
rva2(Min)
T
rva1(Min)
T
rva1(Max)
T
rva2(Max)
T
rva2(Min)
(1) Invalid Active
(2) Valid Active
(3) Valid Active
64µs
128µs
T
rva3(Min)
T
rva3(Max)
Bit
Logic One
Logic Zero
(4) Valid SOF
Symbol
200µs
Active
Passive
Active
Passive
Active
Passive
Active
Passive
(2) Valid BREAK
240µs
T
rv6(Min)
Symbol
Active
Passive