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MPC5200B Users Guide

Document Number: MPC5200BUG

Rev. 1

05/2005

Summary of content (762 pages)

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MPC5200B Users Guide Document Number: MPC5200BUG Rev.
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Table of Contents Paragraph Number Page Number Chapter 1 Introduction 1.1 1.1.1 1.2 1.2.1 1.2.2 1.2.2.1 1.2.2.2 1.2.2.3 1.2.2.4 1.2.2.5 1.2.2.6 1.2.3 1.2.4 1.2.5 1.2.5.1 1.2.5.2 1.2.5.3 1.2.5.4 1.2.5.5 1.2.5.6 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 Overview ...................................................................................................................................................................1-1 Features ...................................................................................
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Table Of Contents Paragraph Number 4.2.2 4.2.3 4.3 4.4 4.5 4.6 Page Number Hard Reset—HRESET ........................................................................................................................................4-1 Soft Reset—SRESET ..........................................................................................................................................4-2 Reset Sequence ......................................................................................................
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Table of Contents Paragraph Number Page Number Chapter 7 System Integration Unit (SIU) 7.1 7.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 7.2.2 7.2.3 7.2.4 7.2.4.1 7.2.4.2 7.2.4.3 7.2.4.4 7.2.4.5 7.2.4.6 7.2.4.7 7.2.4.8 7.2.4.9 7.2.4.10 7.2.4.11 7.2.4.12 7.2.4.13 7.2.4.14 7.2.4.15 7.2.4.16 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.5 7.3.1.6 7.3.1.7 7.3.1.8 7.3.1.9 7.3.2 7.3.2.1 7.3.2.1.1 7.3.2.1.2 7.3.2.1.3 7.3.2.1.4 7.3.2.1.5 7.3.2.1.6 7.3.2.1.7 7.3.2.1.8 7.3.2.1.9 7.3.2.1.10 7.3.2.1.11 7.3.2.1.12 7.3.2.1.
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Table Of Contents Paragraph Number 7.3.2.1.16 7.3.2.2 7.3.2.2.1 7.3.2.2.2 7.3.2.2.3 7.3.2.2.4 7.3.2.2.5 7.3.2.2.6 7.3.2.2.7 7.3.2.2.8 7.3.2.2.9 7.3.2.2.10 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.4.1 7.4.4.2 7.4.4.3 7.4.4.4 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.1.3 7.5.1.4 7.6 7.6.1 7.6.2 7.6.3 7.6.3.1 7.6.3.2 7.6.3.3 7.6.3.4 7.6.3.5 7.6.3.6 7.6.3.7 7.6.3.8 7.6.3.9 Page Number GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C ......................................................
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Table of Contents Paragraph Number 8.4.4.3 8.4.4.4 8.4.4.5 8.4.4.6 8.4.4.7 8.5 8.5.1 8.5.2 8.5.2.1 8.6 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.8 8.8.1 Page Number Bank Active Command ..............................................................................................................................8-14 Read Command ..........................................................................................................................................8-14 Write Command ....................................
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Table Of Contents Paragraph Number 9.7.4.4 9.7.4.5 9.7.4.6 Page Number LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C ............................................................................9-30 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50 ..................................................................9-30 LPC Rx/Tx FIFO Write Pointer Register—MBAR + 0x3C54 ..................................................................9-31 Chapter 10 PCI Controller 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 10.
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Table of Contents Paragraph Number 10.3.3.1.4 10.3.3.1.5 10.3.3.1.6 10.3.3.1.7 10.3.3.1.8 10.3.3.1.9 10.3.3.1.10 10.3.3.1.11 10.3.3.1.12 10.3.3.1.13 10.3.3.1.14 10.3.3.2 10.3.3.2.1 10.3.3.2.2 10.3.3.2.3 10.3.3.2.4 10.3.3.2.5 10.3.3.2.6 10.3.3.2.7 10.3.3.2.8 10.3.3.2.9 10.3.3.2.10 10.3.3.2.11 10.3.3.2.12 10.3.3.2.13 10.3.3.2.14 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.1.4 10.4.1.5 10.4.1.5.1 10.4.1.5.2 10.4.1.5.3 10.4.1.5.4 10.4.2 10.4.2.1 10.4.3 10.4.4 10.4.4.1 10.4.4.2 10.4.4.2.1 10.4.4.2.2 10.4.4.2.
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Table Of Contents Paragraph Number 10.4.6.2 10.4.6.3 10.4.6.4 10.4.6.5 10.4.6.6 10.4.6.7 10.4.6.8 10.4.6.9 10.4.7 10.4.8 10.4.8.1 10.4.8.2 10.5 10.6 10.6.1 10.6.2 10.6.2.1 10.6.2.1.1 10.6.2.1.2 10.6.2.1.3 10.6.3 Page Number Addressing ................................................................................................................................................10-57 Data Translation ............................................................................................................
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Table of Contents Paragraph Number 11.3.3.5 11.3.3.6 11.3.3.7 11.3.3.8 11.3.3.9 11.3.3.10 11.3.3.11 11.3.3.12 11.4 11.4.1 11.4.2 11.4.2.1 11.5 11.6 11.7 11.7.1 11.7.2 11.7.3 11.7.31 11.7.3.2 11.7.3.3 11.7.3.4 11.7.4 11.7.4.1 11.7.4.1.1 11.7.4.1.2 11.7.4.1.3 11.7.4.2 11.7.4.3 11.7.4.3.1 11.7.4.4 11.8 11.8.1 11.8.2 11.9 Page Number ATA Drive Error Register—MBAR + 0x3A64 .......................................................................................
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Table Of Contents Paragraph Number 12.4.3.2 12.4.3.3 12.4.3.4 12.4.3.5 12.4.3.6 12.4.3.7 12.4.4 12.4.4.1 12.4.4.2 12.4.4.3 12.4.4.4 12.4.4.5 12.4.5 12.4.5.1 12.4.5.2 12.4.5.3 12.4.5.4 12.4.5.5 Page Number USB HC Period Current Endpoint Descriptor Register —MBAR + 0x101C ..........................................12-13 USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020 ............................................12-14 USB HC Control Current Endpoint Descriptor Register —MBAR + 0x1024 ..........
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Table of Contents Paragraph Number 13.12.22 13.12.23 13.12.24 13.12.25 13.12.26 13.12.27 13.12.28 13.12.29 13.12.30 13.12.31 13.12.32 13.13 13.14 13.14.1 13.14.1.1 13.14.1.2 13.14.2 Page Number SDMA Initiator Priority 24 Register—MBAR + 0x1254 ...............................................................................13-17 SDMA Initiator Priority 28 Register—MBAR + 0x1258 ...............................................................................13-18 SDMA Requestor MuxControl—MBAR + 0x125C ......
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Table Of Contents Paragraph Number 14.5.17 14.5.18 14.5.19 14.5.20 14.6 14.6.1 14.7 14.7.1 14.8 14.8.1 14.8.2 14.8.3 14.8.4 14.8.5 14.8.6 14.8.7 14.8.8 14.9 14.9.1 14.9.2 14.9.2.1 14.9.3 14.9.3.1 14.9.3.2 14.9.4 14.9.5 14.9.6 14.9.7 14.9.8 14.9.9 14.9.10 14.9.11 14.9.11.1 14.9.11.2 Page Number FEC Descriptor Individual Address 2 Register—MBAR + 0x311C ..............................................................14-24 FEC Descriptor Group Address 1 Register—MBAR + 0x3120 ..................................
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Table of Contents Paragraph Number 15.2.14 15.2.15 15.2.16 15.2.17 15.2.18 15.2.19 15.2.20 15.2.21 15.2.22 15.2.23 15.2.24 15.2.25 15.2.26 15.2.27 15.2.28 15.2.29 15.2.30 15.2.31 15.2.32 15.2.33 15.2.34 15.2.35 15.2.36 15.2.37 15.2.38 15.2.39 15.2.40 15.2.41 15.2.42 15.3 15.3.1 15.3.1.1 15.3.1.2 15.3.1.3 15.3.1.4 15.3.1.5 15.3.2 15.3.2.1 15.3.2.2 15.3.2.2.1 15.3.2.2.2 15.3.2.2.3 15.3.2.3 15.3.2.4 15.3.2.4.1 15.3.2.4.2 15.3.2.4.3 15.3.2.4.4 15.3.2.4.5 15.3.2.4.6 15.3.3 15.3.3.1 15.3.3.2 15.3.3.
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Table Of Contents Paragraph Number 15.3.3.4 15.3.4 15.3.4.1 15.3.4.2 15.3.4.3 15.3.5 15.3.5.1 15.3.5.2 15.3.5.3 15.3.5.4 15.3.6 15.3.6.1 15.3.6.2 15.3.6.3 15.3.7 15.3.7.1 15.3.7.2 15.3.8 15.3.8.1 15.3.8.2 15.3.8.3 15.3.9 Page Number Configuration Sequence for AC97 Mode .................................................................................................15-58 PSC in SIR Mode .........................................................................................................................
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Table of Contents Paragraph Number Page Number Chapter 17 Serial Peripheral Interface (SPI) 17.1 17.1.1 17.1.2 17.2 17.2.1 17.2.2 17.2.3 17.2.4 17.3 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 Overview .................................................................................................................................................................17-1 Features ..............................................................................................................................
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Table Of Contents Paragraph Number 19.5.4 19.5.5 19.5.6 19.5.7 19.5.8 19.5.9 19.5.10 19.5.11 19.5.12 19.5.13 19.5.14 19.5.15 19.5.16 19.5.17 19.5.18 19.6 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.6.6 19.7 19.7.1 19.7.2 19.7.2.1 19.7.2.2 19.7.2.3 19.7.3 19.7.4 19.7.5 19.7.6 19.7.7 19.7.7.1 19.7.7.2 19.7.8 19.7.8.1 19.7.8.2 19.7.8.3 19.7.8.4 19.7.8.5 19.7.8.6 19.7.8.7 19.7.9 19.7.9.1 19.7.9.2 19.7.9.3 19.7.9.4 19.7.10 19.7.11 Page Number MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 .........................
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Table of Contents Paragraph Number Page Number Chapter 20 Byte Data Link Controller (BDLC) 20.1 20.2 20.3 20.4 20.5 20.6 20.6.1 20.6.1.1 20.6.1.2 20.7 20.7.1 20.7.2 20.7.3 20.7.3.1 20.7.3.2 20.7.3.3 20.7.3.4 20.7.3.5 20.7.3.6 20.7.3.7 20.7.3.8 20.8 20.8.1 20.8.1.1 20.8.1.2 20.8.1.3 20.8.1.4 20.8.2 20.8.2.1 20.8.3 20.8.3.1 20.8.4 20.8.4.1 20.8.4.2 20.8.4.3 20.8.5 20.8.5.1 20.8.5.2 20.8.5.3 20.8.5.4 20.8.6 20.8.6.1 20.8.6.2 20.8.6.3 20.8.6.4 20.8.6.5 20.8.6.6 20.8.6.7 20.8.7 20.8.7.1 20.8.7.2 20.8.
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Table Of Contents Paragraph Number 20.8.8.1 20.8.8.2 20.8.9 20.8.9.1 20.8.9.2 20.8.9.3 20.8.9.4 20.9 20.9.1 Page Number Transmitting Or Receiving A Block Mode Message ...............................................................................20-45 Transmitting Or Receiving A Message In 4X Mode ................................................................................20-46 BDLC Module Initialization ..................................................................................................
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List of Figures Figure Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 4-1 4-2 4-3 5-1 5-2 5-3 7-1 7-2 7-3 7-4 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 12-1 Page Number Simplified Block Diagram—MPC5200 ....................................................................................................................1-4 MPC5200-Based System................................................................
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List of Figures Figure Number 12-2 12-3 12-3 12-4 13-1 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 15-27 16-1 17-1 18-1 18-2 18-3 18-4 18-5 18-6 18-7 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 Page Number Communication Channels .......................................................................................................................................
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List of Figures Figure Number 19-11 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 21-1 21-2 21-3 21-4 21-5 21-6 Page Number Initialization Request/Acknowledge Cycle ...........................................................................................................19-35 BDLC Operating Modes State Diagram .................................................................................................................
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List of Figures Notes MPC5200B Users Guide, Rev.
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List of Tables Table Number 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 3-1 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 Page Number Signals by Ball/Pin ...................................................................................................................................................2-4 Signals by Signal Name ......................................
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List of Tables Table Number 5-19 5-20 5-21 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 Page Number CDM PSC2 Mclock Config ....................................................................................................................................5-21 CDM PSC3 Mclock Config ...........................
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List of Tables Table Number 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 Page Number SLT 0 Terminal Count Register ..............................................................................................................................7-62 SLT 0 Control Register ..................................
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List of Tables Table Number 10-9 10-10 10-11 10-12 10-13 10-14 10-15 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-23 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 12-1 12-2 12-3 12-4 12-5 12-6 12-7 Page Number Special Cycle Message Encodings ........................................................................................................................
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List of Tables Table Number 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 13-34 13-35 13-36 13-37 13-38 Page Number USB HC Period Current Endpoint Descriptor Register ........................................................................................
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List of Tables Table Number 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 14-25 14-26 14-27 14-28 14-29 14-30 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 14-40 14-41 14-42 14-43 14-44 14-45 14-46 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 Page Number Signal Properties .................................................................................................................................................
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List of Tables Table Number 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 15-27 15-28 15-29 15-30 15-31 15-32 15-33 15-34 15-35 15-36 15-37 15-38 15-39 15-40 15-41 15-42 15-43 15-44 15-45 15-46 15-47 15-48 15-49 15-50 15-51 15-52 15-53 15-54 15-55 15-56 15-57 15-58 15-59 15-60 15-61 15-62 Page Number Stop-Bit Lengths ..................................................................................................................................
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List of Tables Table Number 15-63 15-64 15-65 15-66 15-67 15-68 15-69 15-70 15-71 15-72 15-73 15-74 15-75 15-76 15-77 15-78 15-79 15-80 15-81 15-82 15-83 15-84 15-85 15-86 15-87 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 18-1 18-2 18-3 18-4 Page Number Tx FIFO Control (0x88) ........................................................................................................................................
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List of Tables Table Number 18-5 18-6 18-7 18-8 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20 19-21 19-22 19-23 19-24 19-25 19-26 19-27 19-28 19-29 19-30 19-31 19-32 19-33 19-34 19-35 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 Page Number I2C Control Register ................................................................................................................................................
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List of Tables Table Number 20-16 20-17 20-18 20-19 20-20 21-1 21-2 21-3 21-4 Page Number BDLC Receiver VPW Symbol Timing for Binary Frequencies ...........................................................................20-21 BDLC Receiver VPW 4X Symbol Timing for Integer Frequencies .....................................................................20-21 BDLC Receiver VPW 4X Symbol Timing for Binary Frequencies .....................................................................
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Revision History Release Date Author Summary of Changes 0 26MAR2005 AS Initial Version 0.1 26MAR2005 AS, TB, PL Updated PCI, PSC, BestComm, I2C, GPIO, CDM chapters. 0.2 03MAY2005 AE Cross refs, hyperlinks, TOC, Verso, and fonts. 1 12AUG2005 AE, TB, PL, CM, AS Minor updates. MPC5200B Users Guide, Rev.
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MPC5200B Users Guide, Rev.
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Overview Chapter 1 Introduction 1.1 Overview The digital communication networking and consumer markets require significant processor performance to enable operating systems and applications such as VxWorks™, QNX™, JAVA and soft modems. High integration is essential to reducing device and systems costs. The MPC5200B is specifically designed to meet these market needs while building on the family of microprocessors that use PowerPC™ architecture.
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Architecture • • • • • • • • • • 1.2 — IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller (FEC) — Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface Universal Serial Bus Controller (USB) — USB Revision 1.1 Host — Open Host Controller Interface (OHCI) — Integrated USB Hub, with two ports. Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.
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Architecture A dynamically managed external pin multiplexing scheme minimizes overall pin count. The result is low cost packaging and board assembly costs. Local Bus Figure 1-1 shows a simplified MPC5200B block diagram.
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Architecture The MPC5200B supports a dual external bus architecture consisting of: 1. an SDRAM Bus 2. a multi-function LocalPlus Bus The SDRAM Bus has a Memory Controller interface which supports standard SDRAM and Double Data Rate (DDR) SDRAM devices. The Memory Controller has 13 Memory Address (MA) lines multiplexed with 32 Data Bus lines. Standard SDRAM control signals are included.
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Architecture SDRAM/DDR Controller Demodulator MPC5200 Audio Memory Controller SIU Transport & Video Decoder/ Encoder PCI Bus Embedded e300 Core (MPC603e) SDRAM ATA Interface SRAM Interface Control Video SRAM Graphics SDRAM DMA Ethernet IrDA Rx/Tx I2C1 USB ENET PSC6 PSC5 PSC4 PSC3 PSC2 PSC1 Flash, Boot ROM IDE Disk Interface IC Control Printer or I/O port UART UART Codec AC97 Debug Interface Figure 1-2. MPC5200B-Based System 1.2.
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Architecture Up to 3 instructions can be issued and retired per clock. Most instructions execute in a single cycle. The core contains an integrated Floating Point Unit (FPU), a Data Cache Memory Management Unit and an Instruction Cache Memory Management Unit.. The core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addressing and integer data types of 8-, 16-, and 32-bits.
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Architecture MSCAN supports both standard and extended identifier (ID) message formats specified in BOSCH CAN protocol specification, revision 2.0, part B. Each MSCAN module contains: • 4 receive buffers (with FIFO storage scheme) • 3 transmit buffers • flexible maskable identifier filters 1.2.
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Architecture 1.2.5.5 Functional Pin Multiplexing Many serial/parallel port pins serve multiple functions, allowing flexibility in optimizing the system to meet a specific set of integration requirements.
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Architecture A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a low-power standby mode, then re-enabled by one of the Wake Up inputs without resetting the MPC5200B. 1.2.9 Systems Debug and Test The MPC5200B supports the Common On-chip Processor (COP) debug capability common on other microprocessors that use the PowerPC architecture.
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Architecture MPC5200B Users Guide, Rev.
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Overview Chapter 2 Signal Descriptions 2.1 Overview The MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks and associated I/O ports. There are two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure 1-1. In general, the LocalPlus bus connects to external SRAM, FLASH, peripheral devices, etc. The LocalPlus bus is capable of executing standard memory cycles, PCI cycles and ATA cycles.
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Overview Y1 signal: ext_ad_27 View Looking at Pins (Balls) Y20 signal: timer0 Y W V U T R P N M L K J H G F E D C B A A1 signal: test_mode_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A20 signal: mem_dqm_2 Note: Table 2-1 and Table 2-2 give the signals on each pin/ball. Figure 2-1. 272-Pin PBGA Pin Detail Table 2-1 gives a list of MPC5200B I/O signals sorted by package ball name. Table 2-2 gives the same list sorted by signal name.
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Freescale Semiconductor A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 TEST_MODE_1 JTAG_TDO JTAG_TDI JTAG_TMS PSC3_8 PSC3_5 PSC3_2 PSC2_4 PSC2_2 PSC1_4 PSC1_1 PSC6_2 PORRESET SRESET SYS_XTAL_IN MEM_MA_1 MEM_MBA_1 MEM_RAS MEM_WE MEM_DQM_2 B14 B15 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 TEST_SEL_0 TEST_MODE_0 JTAG_TRST JTAG_TCK PSC3_7 PSC3_4 PSC3_1 PSC2_3 PSC2_1 PSC1_3 PSC1_0 PSC6_0 HRESET C01 C0
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Pinout Tables M S C A N SDRAM CS1 S P I P S C 5 System chip selects TSIZE_1 4 G P I O I 2 C 4 T I M E R S 4 P S C 1 8 P S C 2 5 5 P S C 3 5 E T H E R U S B P2 10 100 5 7 2 ATA chip selects 4 2 P S C 4 5 P S C 6 J 1 8 5 0 P1 10 10 18 Reset Conf.
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Pinout Tables Table 2-1.
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Pinout Tables Table 2-1.
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Pinout Tables Table 2-1.
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Pinout Tables Table 2-1.
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Pinout Tables Table 2-2.
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Pinout Tables Table 2-2.
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Pinout Tables Table 2-2.
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Pinout Tables Table 2-2.
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Pinout Tables Table 2-2. Signals by Signal Name (continued) Signal Name Ball/Pin VDD_MEM_IO P17 VDD_MEM_IO T17 VSS_IO/CORE D04 VSS_IO/CORE D16 VSS_IO/CORE J09 VSS_IO/CORE J10 VSS_IO/CORE J11 Signal Name Ball/Pin Table 2-3.
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Pinout Tables Table 2-4.
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Pinout Tables Table 2-4.
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Pinout Tables Table 2-4.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-5.
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Pinout Tables Table 2-6.
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Pinout Tables Table 2-6. PCI Dedicated Signals (continued) PIN / BALL NUMBER Pin PCI_RESET Function Reset Value Description Ball R02 PCI PCI_RESET logic 0 PCI Reset Output (open drain) MOST Graphics A15 logic 0 MOST Graphics Address Bit A15 Table 2-7.
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Pinout Tables Table 2-8.
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Pinout Tables UART1(e) CODEC1 5 4 AC971 GPIO 5 5 Pin Drivers and MUX Logic PSC_0 Function Port_conf [29:31] GPIO 00X GPIO AC97_1 01X UART1 PSC_2 PSC_1 PSC_0 PSC_1 GPIO PSC_2 PSC_3 PSC_3 GPIO PSC_4 PSC_4 GPIO GPIO_W/WAKE_UP AC97_1_SDATA_O AC97_1_SDATA_IN AC97_1_SYNC UT AC97_1_BITCLK AC97_1_RES 100 UART1_TXD UART1_RXD UART1_RTS UART2_CTS GPIO_W/WAKE_UP UART1e 101 UART1e_TXD UART1e_RXD UART1e_RTS UART1e_CTS UART1e_DCD CODEC1 110 CODEC1_TXD CODEC1_RXD GPIO CODE
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Pinout Tables Table 2-10.
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Pinout Tables Table 2-10.
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Pinout Tables UART2(e) CODEC2 5 AC972 4 CAN1/2 GPIO 4 5 5 Pin Drivers and MUX Logic PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 Function Port_conf [25:27] GPIO 000 GPIO GPIO GPIO GPIO GPIO_W/WAKE_UP CAN1/2 001 CAN1_TX CAN1_RX CAN2_TX CAN2_RX GPIO_W/WAKE_UP AC97_2 01X AC97_2_SDATA_OUT AC97_2_SDATA_IN AC97_2_SYNC AC97_2_BITCLK AC97_2_RES PSC_0 PSC_1 PSC_2 PSC_3 PSC_4 UART2 100 UART2_TXD UART2_RXD UART2_RTS UART2_CTS GPIO_W/WAKE_UP UART2e 101 UART2e_TXD UART2e_RXD U
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Pinout Tables Table 2-12.
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Pinout Tables Table 2-12.
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Pinout Tables UART3(e) CODEC3 5 USB2 4 SPI 10 GPIO 10 4 Pin Drivers and MUX Logic PSC3_0 PSC3_1 Function Port_conf [20:23] GPIO 0000 GPIO GPIO GPIO USB2 0001 USB2_OE USB2_TXN UART3 0100 UART3_TXD UART3_RXD PSC3_0 PSC3_1 PSC3_2 PSC3_2 PSC3_3 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_6 PSC3_7 PSC3_7 PSC3_8 PSC3_4 PSC3_5 GPIO LP_CS_6 or INTERRUPT LP_CS_7 or INTERRUPT GPIO USB2_TXP USB2_RXD USB2_RXP USB2_RXN USB2_PRTPW USB2_SPEED USB2_SUSPE USB2_OVRCNT R ND UART3_RTS
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Pinout Tables Table 2-14. PSC3 Pin Functions (cont.) Pin name Dir.
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Pinout Tables Table 2-15.
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Pinout Tables Table 2-15.
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Pinout Tables Table 2-15.
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Pinout Tables Table 2-15.
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Pinout Tables Table 2-15.
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Pinout Tables Table 2-16. USB Pin Functions Pin Name Dir. USB_0 I/O USB_1 I/O USB_2 I/O USB_3 Reset Configuration GPIO USB 2x UART4/5 GPIO USB1_OE GPIO RST_CFG6 USB1_TXN UART4_RTS RST_CFG7 USB1_TXP UART4_TXD I USB1_RXD UART4_RXD USB_4 I USB1_RXP UART4_CTS USB_5 I USB1_RXN UART5_RXD USB_6 I/O GPIO USB1_PORTPWR UART5_TXD USB_7 I/O GPIO USB1_SPEED UART5_RTS USB_8 I/O GPIO USB1_SUSPEND UART5_CTS USB_9 I/O INTERRUPT USB1_OVERCNT INTERRUPT Table 2-17.
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Pinout Tables Table 2-17. USB Pin Functions by Pin (continued) PIN / BALL NUMBER Pin USB_3 Function Reset Value Description Ball G01 GPIO hi - z ---- USB1 hi - z USB1_RXD USB1 Receive Data RESET Config. hi - z ---- UART4, UART5 hi - z UART4_RXD Uart Receive Data GPIO hi - z ---- USB1 hi - z USB1_RXP USB1 Receive Positive RESET Config. hi - z ---- UART_, UART5 hi - z UART4_CTS Uart Clear To Send GPIO hi - z ---- USB1 hi - z USB1_RXN USB1 Receive Negative RESET Config.
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Pinout Tables Table 2-17. USB Pin Functions by Pin (continued) PIN / BALL NUMBER Pin USB_9 Reset Value Function Description Ball F03 GPIO hi - z GPIO Simple General Purpose I/O USB1 hi - z USB1_OVRCRNT USB1 Over Current RESET Config.
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Pinout Tables J1850 PSC4 PSC5 2 5 5 USB2 (I/O portion) Ethernet (Inputs) 10 GPIO 4 9 Pin Drivers and MUX Logic ETH_8 ETH_9 ETH_10 ETH_11 ETH_12 ETH_13 ETH_14 ETH_15 ETH_16 ETH_17 Port_ conf [12:15] ETH_8 ETH_9 ETH_10 ETH_11 GPIO 0000 OUTPUT OUTPUT OUTPUT USB2 0001 OUTPUT OUTPUT OUTPUT ETH7 0010 ETH7 / USB2 0011 ETH_18 no MD 0100 ETH18_RXDV ETH18_RXCL ETH18_COL ETH18_TXC ETH18_RX ETH18_RXD ETH18_RXD_ ETH18_RXD ETH18_RXE ETH18_CRS K LK D_0 _1 2 _3 RR ETH_18 w/ MD 01
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Pinout Tables Table 2-18. Ethernet Pin Functions (continued) Pin name Dir.
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Pinout Tables Table 2-19. Ethernet Pin Functions (cont.) Pin name Dir. ETH_18 no MD ETH_18 w/ MD ETH7 / UART4e/J1850 ETH7 /J1850 2UART4/5e/J1850 UART5e/J1850 J1850 ETH_16 I/O ETH18_RXERR ETH18_w/ MD_RXERR UART4e__DCD INTERRUPT UART4_CD INTERRUPT INTERRUPT ETH_17 I/O ETH18_CRS ETH18_w/ MD_CRS GPIO_W/WAKEUP GPIO_W/WAKEUP GPIO_W/WAKE- GPIO_W/WAKE-UP GPIO_W/WAKE-UP UP Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-20.
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Pinout Tables Table 2-21.
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Pinout Tables Table 2-21.
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Pinout Tables Table 2-21.
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Pinout Tables Table 2-21.
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Pinout Tables Table 2-21.
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Pinout Tables Timer0 (IC/OC/PWM) 1 Timer1 (IC/OC/PWM) Timer7 (IC/OC/PWM) 1 1 ATA Chip Selects CAN2 2 SPI 2 GPIO 4 8 TMR_5 TMR_6 Pin Drivers and MUX Logic TMR_0 Function Port_config [2:3_6:7] TIMER0 TMR_1 TIMER1 TMR_2 TIMER2 TIMER3 TMR_3 TMR_4 TIMER4 TIMER5 TIMER6 TIMER7 GPIO TIMER 00_0X 00_10 GPIO TIMER_0 GPIO TIMER_1 GPIO TIMER_2 GPIO TIMER_3 GPIO TIMER_4 GPIO TIMER_5 GPIO TIMER_6 GPIO TIMER_7 ATA_CS 00_11 ATA_CS_0 ATA_CS_1 GPIO TIMER_2 GPIO TIMER_3 GPIO TIME
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Pinout Tables Table 2-23.
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Pinout Tables Table 2-23.
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Pinout Tables Table 2-23.
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Pinout Tables Table 2-24. PSC6 Pin Functions Pin name Dir. GPIO UART6/ IrDA CODEC6 / IrDA PSC6_0 I/O WAKE_UP UART6_RXD IrDA_RX CODEC6_RXD Irda_RX PSC6_1 I/O WAKE_UP UART6_CTS CODEC6_FRAME PSC6_2 I/O SIMPLE GPIO UART6_TXD IrDA_TX CODEC6_TXD IrDA_TX PSC6_3 I/O SIMPLE GPIO UART6_RTS CODEC6_CLK/ IR_USB_CLK Table 2-25.
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Pinout Tables I2C2 I2C1 2 2 ATA Chip Selects CAN1 2 2 Pin Drivers and MUX Logic I2C_0 Function Port_conf I2C_0 I2C_1 I2C_2 I2C_1 I2C_2 I2C_3 I2C_3 I2C1 / I2C2 default I2C1_CLK I2C1_IO I2C2_CLK I2C2_IO CAN1 / I2C2 Port_conf[2:3]=01 CAN1_TX CAN1_RX I2C2_CLK I2C2_IO I2C1 / ATA CHIP Port_conf[6:7]=10 SELECTS I2C1_CLK I2C1_IO ATA_CS_0 ATA_CS_1 NOTE: 1. CAN RX input supports WakeUp functionality. Figure 2-12. I2C Port Map—4 Pins (two pins each, for two I2Cs) Table 2-26.
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Pinout Tables Table 2-27.
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Pinout Tables Table 2-27.
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Pinout Tables Table 2-27.
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Pinout Tables Table 2-27. SDRAM Bus Pin Functions (continued) PIN BALL NUMBER Function Pin MEM_MDQ_5 Reset Value Description hi - z SDRAM Bus Data 5 hi - z SDRAM Bus Data 4 hi - z SDRAM Bus Data 3 hi - z SDRAM Bus Data 2 hi - z SDRAM Bus Data 1 hi - z SDRAM Bus Data 0 clk SDRAM Bus Memory Read Clock Ball R19 Pin MEM_MDQ_4 Ball R20 Pin MEM_MDQ_3 Ball T19 Pin MEM_MDQ_2 Ball T20 Pin MEM_MDQ_1 Ball U19 Pin MEM_MDQ_0 Ball U20 Pin MEM_RDCLK Ball not pinned out (not pinned out) Table 2-28.
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Pinout Tables Table 2-29. CLOCK / RESET Pin Functions CLOCK / RESET Functions Pin PORRESET Reset Value Description logic 1 Power On Reset logic 1 Hard Reset logic 1 Soft Reset Ball A13 Pin HRESET Ball B13 Pin SRESET Ball A14 Pin SYS_XTAL_IN APLL Chip clock crystal / external clock input Ball A15 Pin SYS_XTAL_OUT clk APLL Chip Clock Crystal Ball D14 Pin SYS_PLL_TPA MPC5200B System Test Pll Output (analog output) Ball B15 Table 2-30.
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Pinout Tables Table 2-31.
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Signal Descriptions Notes MPC5200B Users Guide, Rev.
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Overview Chapter 3 Memory Map 3.
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Internal Register Memory Map 3.2 Internal Register Memory Map Table 3-1. Internal Register Memory Map Address Name MBAR + 0x0000 MM MBAR + 0x0100 Description Memory Map Registers SDRAM SDRAM Memory Controller registers. Reference Section 3.3.3 Section 8.7 MBAR + 0x0200 CDM Clock Distribution Module registers. Section 5.5 MBAR + 0x0300 CSC Chip Select Controller registers. Section 9.7.1 MBAR + 0x0500 ICTL Interrupt Controller registers. Section 7.2.
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MPC5200B Memory Map 3.3 MPC5200B Memory Map The MPC5200B memory map has the following main regions: • MPC5200B Internal Register Space • External Busses — SDRAM Bus — LocalPlus Bus – External Chip Selects 0 - 7 – Memory Space – Boot Space – Program Space – Data Space • ATA Space 3.3.1 MPC5200B Internal Register Space The internal registers of the MPC5200B are memory mapped, just like external RAM or any other peripheral devices.
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MPC5200B Memory Map 3.3.2.2 LocalPlus Bus The LocalPlus Bus is designed to connect to ROM, FLASH, static RAM and other peripheral devices. It is not designed to accommodate DRAM’s. Program execution begins from the LocalPlus Bus memory device connected to LP_CS0. In actual practice, the only programs that are usually executed from LocalPlus Bus memory are those used to initialize the MPC5200B and to transfer data from LocalPlus Bus memory to SDRAM bus memory.
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MPC5200B Memory Map 3.3.3 Memory Map Space Register Description These registers exist in the Memory Map register space relative to Memory Base Address Register (MBAR). 3.3.3.
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MPC5200B Memory Map MBAR offset Name Description 0x002C CS5 Start Address Chip Select 5 through the LocalPlus Bus. Any access on an address between the Start and Stop Addresses enables this chip select. 0x0030 CS5 Stop Address 0x004C Boot Start Address 0x0050 Boot Stop Address 0x0058 CS6 Start Address 0x005C CS6 Stop Address 0x0060 CS7 Start Address 0x0064 CS7 Stop Address Boot Addressing through the LocalPlus Bus.
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MPC5200B Memory Map msb 0 1 2 3 4 R 5 6 7 8 9 10 11 12 Base XLB Address 13 14 15 Reserved W RESET 0 0 16 17 0 18 0 19 0 20 R 0 21 0 0 0 0 0 0 0 0 0 22 23 24 25 26 27 28 29 30 Reserved 0 31 lsb SDRAM Size W RESET 0 0 0 0 0 0 Bits Name 0:11 Base XLB Address Start address for memory 12:26 Reserved These bits are reserved.
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MPC5200B Memory Map 3.3.3.
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Overview Chapter 4 Resets and Reset Configuration 4.1 Overview The following sections are contained in this document: • Hard and Soft Reset Pins • Reset Sequence • Reset Operation • Other Resets • Reset Configuration 4.2 Hard and Soft Reset Pins MPC5200B has three primary reset pins, which are implemented as open drain I/Os1: • Power-On Reset—PORRESET • Hard Reset—HRESET • Soft Reset—SRESET PORRESET is a power-on reset input.
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Reset Sequence 4.2.3 Soft Reset—SRESET External SRESET is an open drain signal. SRESET requires an external pull-up. Assertion of SRESET causes assertion of the internal soft reset. Internal soft reset is actually an interrupt that takes the same exception vector as HRESET. In particular, this means that SRESET cannot abort a hung XLB operation, and no device should use SRESET in a way that interferes with any bus operation in progress. SRESET can also be asserted by internal sources.
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Other Resets ≥100 us 4096 ref cycles All Power Supplies SYS_XTAL PORRESET HRESET SRESET Figure 4-2. PORRESET Assertion When external HRESET is asserted, internal reset logic catches the reset signal held low and asserts internal hard and soft resets for 4096 reference clock cycles. The external reset signal must be held low for at least 4 reference clock cycles (must catch 4 rising edges of reference clock) to be recognized and assert the internal reset signals.
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Reset Configuration Table 4-1. Module Specific Reset Signals (continued) Definition JTAG_TRST JTAG reset input. Generated externally from JTAG or debug control logic. This input only resets the JTAG logic. Other system resets (PORRESET, HRESET, and SRESET) do not reset the JTAG logic. Note: For information on the reset signal JTAG_TRST and the relationship to other reset signals refer to the MPC5200 Hardware Specifications. ATA Reset 4.6 This is NOT a reset pin on MPC5200B.
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Reset Configuration Table 4-2. Reset Configuration Word Source Pins (continued) Pkg Ball Reset Config Pin I/O Signal Name CDM Reset Config Register Bit Config Signal from CDM L03 RST_CFG13 ETH5 PORCFG[18] boot_rom_size Description For non-muxed boot ROMs: 2,3 bit=0:8bit boot ROM data bus, 24bit max boot ROM address bus bit=1:16bit boot ROM data bus, 16bit boot ROM address bus For muxed boot ROMs: boot ROM address is max 25 significant bits during address tenure.
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Resets and Reset Configuration Notes MPC5200B Users Guide, Rev.
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Overview Chapter 5 Clocks and Power Management 5.1 Overview The following sections are contained in this document: • Clock Distribution Module (CDM) • MPC5200B Clock Domains • Power Management • CDM Registers 5.2 Clock Distribution Module (CDM) The CDM is the source of all internally generated clocks and reset signals. The MPC5200B clock generation uses two analog phase locked loop (APLL) blocks.
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MPC5200B Clock Domains — When generated externally, the frequency can be different NOTE Only one pin is allocated to supply the USB and PSC6/IrDA clock. If both modules require external clock generation, the frequency must be 48MHz. SPI—The SPI (Serial Peripheral Interface) has a clock input pin, SPI_CLK. When the SPI is configured as a slave, the clock is supplied externally. The SPI module therefore has a small asynchronous clock domain.
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MPC5200B Clock Domains 5.3.1 MPC5200B Top Level Clock Relations Figure 5-2 shows the CDM clock divide circuitry. This picture shows only the functional clocks. The clock network regarding the scan and bypass modes is not included. VCO fVCOcore divide by 2 or 4 e300 CORE CLOCK e300 Core APLL divide by 2, 2.5,3.0 ...7.
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MPC5200B Clock Domains Table 5-2 shows the System PLL configuration and the corresponding fsystem frequencies for a 27.0 MHz and 33.0 MHz input clock. Table 5-3 shows all possible clock ratios. Table 5-2. System PLL Ratios SYS_XTAL_IN sys_pll_cfg[1] sys_pll_cfg[0] fVCOsys [MHz] fsystem [MHz] 0 0 432.0 432.0 0 1 324.0 324.0 1a 0 864.0 432.0 1 1 648.0 324.0 0 0 528.0 528.0 0 1 396.0 396.0 1a 0 1056.0 528.0 1 1 792.0 396.0 27.0 33.0 a These are invalid configurations.
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MPC5200B Clock Domains Table 5-4. Typical System Clock Frequencies fsystem [MHz] XLB Clock [MHz] IPB CLock [MHz] PCI CLOCK [MHz] Clock Ratio XLB:IPB:PCI 132.0 66.0 4:4:2 33.0 4:4:1 66.0 4:2:2 33.0 4:2:1 33.0 33.0 4:1:1 66.0 66.0 2:2:2 33.0 2:2:1 33.0 2:1:1 132.0 528.0 66.0 66.0 33.0 Table 5-4 shows the typical clock ratios with a 33.0 MHz clock input on the SYS_XTAL_IN pin and a System PLL divide value 16 (sys_pll_cfg[0] = 0).
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MPC5200B Clock Domains Table 5-5. e300 Core Frequencies vs. XLB Frequencies 132 108 99 81 66 54 49.5 40.5 33 27 x1 — — — — — — — — — — x1.5 — — — — — — — — — — x2 264 216 198 162 132 108 99 81 66 54 x2.5 330 270 247.5 202.5 165 135 123.8 101.3 82.5 67.5 x3 396 324 297 243 198 162 148.4 121.5 99 81 378 346.5 283.5 231 189 173.3 141.8 115.5 94.5 396 324 264 216 198 162 132 108 364.5 297 243 222.8 182.3 148.5 121.
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MPC5200B Clock Domains Table 5-6. e300 Core APLL Configuration Options (continued) ppc_pll_cfg Bus:Core Ratio (XLB : CORE CLOCK) Core:VCO Ratio (CORE CLOCK: fVCOcore) Bus:VCO Ratio (XLB : fVCOcore) hex [0:1:2:3:4] 0x08 01000 1:3 1:2 1:6 0x09 01001 1:5.5 1:2 1:11 0x0A 01010 1:4 1:2 1:8 0x0B 01011 1:5 1:2 1:10 0x0C 01100 — — — 0x0D 01101 1:6 1:2 1:12 0x0E 01110 1:3.5 1:2 1:7 0x10 10000 1:3 1:4 1:12 0x11 10001 1:2.5 1:4 1:10 0x12 10010 1:6.
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MPC5200B Clock Domains Table 5-7. SDRAM Memory Controller Clock Domain Bits Description mem_clk mem_clk is always the same frequency as xlb_clk. mem_2x_clk, mem_2x_clk These internal clocks are twice the frequency of xlb_clk and are used to add more resolution to SDRAMC control signals mem2x1x_clk (becomes mem_rd_clk) This is the source of the internal memory read clock. It always operates at the memory data rate, 1x mem_clk for SDR, 2x mem_clk for DDR.
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Power Management 5.4 Power Management Power Management modes are listed below. Details are given in the sections that follow. • Full-Power Mode • Power Conservation Modes The MPC5200B design is equipped with many power conservation features, which are supported in the peripherals and system logic. The e300 Core has its own power-down modes: • nap • doze • sleep Individual peripheral functions can be disabled by stopping the module’s clock.
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Power Management 5.4.3.1 Dynamic Power Mode This is the default power state mode. The core is fully powered and internal functional units are operating at the full processor clock speed. If Dynamic Mode is enabled, idle functional units automatically enter a low-power state. This does not effect: • performance • software execution • external hardware 5.4.3.2 Doze Mode All functional e300 Core units are disabled except for the time base/decrementer registers and the bus snooping logic.
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CDM Registers mode. The e300 Core must enable the deep sleep process in the CDM module, then put itself into sleep mode before the e300 Core PLL can be disabled. Since MPC5200B clocks are stopped in Deep Sleep mode, the wake-up time is longer than in the e300 Core-only power down modes. A power-on sequence must occur which re-locks both the MPC5200B system and processor PLLs.
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CDM Registers 5.5.1 CDM JTAG ID Number Register—MBAR + 0x0200 The CDM JTAG ID Number Register is a read-only register that contains the JTAG Identification number identifying MPC5200B. The value is hard coded (1001 101D hex) and cannot be modified. Table 5-8.
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CDM Registers Bit Name Description 15 sys_pll_bypass bit=0:Normal mode. The SYS OSC clock input is multiplied up by the system PLL, then the PLL VCO is divided down to produce internal clocks. bit=1:The SYS OSC clock input is used directly, bypassing the system PLL. No multiplication of the input frequency is performed, but the input frequency is divided to produce internal clocks just as the system PLL VCO frequency would be. sys_pll_cfg_1 and sys_pll_cfg_0 are ignored.
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CDM Registers Bit Name 27 ppc_pll_cfg_0 28 ppc_pll_cfg_1 29 ppc_pll_cfg_2 30 ppc_pll_cfg_3 31 ppc_pll_cfg_4 5.5.3 Description e300 Core core pll config pins. See also Table 5-6 CDM Bread Crumb Register—MBAR + 0x0208 The CDM Bread Crumb Register is a 32-bit register that is not reset. Its purpose is to let firmware designers leave some status code before entering a reset condition. Since this register is never reset, the value written is available after the reset condition has ended.
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CDM Registers Bit Name Description 0–6 — 7 ddr_mode Reserved for future use. Write 0. SDRAM Controller DDR memory mode, read-only. bit=0:SDRAM Controller configured for SDR SDRAM (single data rate) bit=1:SDRAM Controller configured for DDR SDRAM (double data rate) This register location is a read-only status bit; write 0. The controlling register is in the SDRAM Controller register map. In the CDM this bit determines the frequency and phase of memory read clock. Reserved for future use. Write 0.
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CDM Registers Bit Name Description 0–4 — 5 ext_usb_sync_en Reserved for future use. Write 0. Enable the synchronization logic which synchronize the external ext_usb_48Mhz clock to the internal clock system. bit=1:ext USB 48MHz clock is synchronized to the internal clock system. bit=0:ext USB 48MHz clock is not synchronized to the internal clock system. 6 ext_usb_48MHz_en USB External 48MHz Clock Select bit=1:USB 48MHz clock tree sourced from external clock from GPIO.
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CDM Registers Bit Name Description 0 — Reserved for test. Write 0. 1–11 — Reserved for future use. Write 0. 12 mem_clk_en Memory Clock Enable—controls SDRAM Controller module clocks Memory Controller IPB_CLK is not controlled by mem_clk_en. 13 pci_clk_en PCI Bus Clock Enable—controls PCI bus control module clocks Note: PCI Arbiter and external PCI Bus clocks are not controlled by pci_clk_en.
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CDM Registers 16 17 18 19 20 21 22 R 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Reserved Write 0 W RESET: 23 0 0 0 0 0 0 0 0 Bit Name 0–6 — Reserved for future use. Write 0. 7 sys_osc_disable CDM System Oscillator Disable 0 Description bit=1:System Oscillator is disabled. External clock source is required. bit=0:System Oscillator is enabled. 27–33MHz crystal is being used. 8–31 5.5.8 — Reserved for future use. Write 0.
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CDM Registers Bit Name 16–30 — 31 ccs_qreq_test Description Reserved for future use. Write 0. CCS Test bit—Used in CCS module functional simulation to simulate a QREQ signal. bit=0:QREQ input to CCS forced active. bit=1:QREQ input to CCS comes directly from e300 Core. MPC5200B Users Guide, Rev.
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CDM Registers 5.5.9 CDM Soft Reset Register—MBAR + 0x0220 This register contains 2 reset control bits. Table 5-16.
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CDM Registers Bit Name 0–6 — 7 pll_lock1 Description Reserved for future use. Write 0. CDM System PLL Lock Detect—read-only status bit. bit=1:CDM has detected System PLL lock condition. bit=0:CDM has NOT detected System PLL lock condition. 8–14 — 15 pll_lost_lock Reserved for future use. Write 0. CDM System PLL Lock Lost—hardware can only set this bit, register write must clear bit. bit=1:CDM detected loss of PLL lock after PLL lock has been achieved.
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CDM Registers 5.5.12 PSC2 Mclock Config Register—MBAR + 0x022C This register controls the generation of the Mclock for PSC2. Before modify the register value the divider must be disabled. Table 5-19.
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CDM Registers 5.5.14 PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234 This register controls the generation of the Mclock for PSC6. Before modify the register value the divider must be disabled. Table 5-21.
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CDM Registers MPC5200B Users Guide, Rev.
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Overview Chapter 6 e300 Processor Core 6.1 Overview The following sections are contained in this document: • MPC5200B e300 Processor Core Functional Overview • e300 Core Reference Manual • Not supported e300 Core Features 6.2 MPC5200B e300 Processor Core Functional Overview The MPC5200B integrates a e300 processor core based on, and compatible with, the 603e which is a PowerPC compliant microprocessor.
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e300 Core Reference Manual 6.3 e300 Core Reference Manual A complete specification for the e300 core implementation used on the MPC5200B is obtained through a collection of documentation. • PowerPC MicroprocessorFamily: The Programming Environments for 32-bit Microprocessors, Rev. 2: MPCFPE32B/AD • G2 PowerPC Core Reference Manual, Rev. 1: G2CORERM/D The programming environments manual provides information about resources defined by the PowerPC architecture that are common to PowerPC processors.
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Overview Chapter 7 System Integration Unit (SIU) 7.
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Interrupt Controller Table 7-1 does not include machine-check bus errors or transaction handshaking. e300 core interrupt pins given in Section 7.2.1.1, Machine Check Pin—core_mcp through Section 7.2.1.3, Standard Interrupt—core_int show e300 core interrupt priority. 7.2.1.1 Machine Check Pin—core_mcp NOTE The core_mcp pin is not used. Bus errors occur on the XL bus, thus generating an internal machine-check exception, or are reflected as a normal interrupt from the offending source module.
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Interrupt Controller IRQ[0] Slice Timer 0 CCS Wkup core_cint BestComm HI_int Peripherals (ATA/PCI etc.) LO_int Slice Timer 1 core_smi IRQ[1:3] core_int SIU interrupts (RTC/GPIO/WKUP/TMRS) Indicates it can be masked in controller. Indicates priority encoding programmability. Figure 7-1.
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Interrupt Controller 7.2.2 Interface Description 4 Timers (IC, OC, PWM) Slice Timers e300 core 4 core_mcp 0 core_cint 1 core_smi Real Time Clock 8 8 core_int GPIO/Std Main Interrupt Controller GPIO/WakeUp IRQ0 Peripheral 1 IRQ1 Peripheral 2 IRQ2 Peripheral 3 IRQ3 cint_ded Encoder smi_ded int_ded Grouper Encoder programmable inputs Peripheral 4 Grouper Encoder Peripheral 5 HI Peripheral 6 LO Peripheral … XLB Arbiter BestComm Controller NOTE: 1.
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Interrupt Controller correct behavior, the e300 core always completes the core_int before treating the core_smi. In this case, the CPU does not authorize nested interrupt at the exception if the ISR set the 603e’s MSR[EE] to support nested interrupt (core_smi and core_int). In order to guaranty the assertion of the core_cint when a core_int is pending, the ISR needs to force the re-evaluation of the Peripheral Interrupt condition by writing “1” to the Peripheral Status Encoded Pse msb.
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Interrupt Controller Bits Name — Per_mask Description Bits 0:23—To mask/accept individual peripheral interrupt sources. This masking is in addition to interrupt enables, which may exist in each source module. 0=Accept interrupt from source module. 1=Ignore interrupt from source module. Important—See Note 1.
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Interrupt Controller 7.2.4.2 ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504 Table 7-5.
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Interrupt Controller 7.2.4.3 ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508 Table 7-6.
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Interrupt Controller Bits Name 8:11 Per18_pri Peripheral 18 = CAN2 12:15 Per19_pri Reserved 16:19 Per20_pri Reserved 20:23 Per21_pri Peripheral 21 = XLB Arbiter 24 :27 Per22_pri Peripheral 22 = BDLC 28 :31 Per23_pri Peripheral 23 = BestComm LocalPlus 7.2.4.5 Description ICTL External Enable and External Types Register —MBAR + 0x0510 Table 7-8.
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Interrupt Controller Bits Name Description — EENA[x] Individual enable bits for each IRQ input pin. Setting the associated bit lets the related IRQ pin generate interrupts. In either case, status indications in PSa and CSa (ICTL Peripheral Interrupt Status All Register) are active.
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Interrupt Controller Bits Name Description — Main_Mask[x] To mask/accept individual main interrupt sources (as opposed to peripheral or critical interrupt sources). This masking is in addition to interrupt enables, which may exist in each source module. 0=Default. Accept interrupt from source module. 1=Ignore interrupt from source module. Take care if masking LO_int, which is a collection of multiple Peripheral sources in a single presentation.
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Interrupt Controller 7.2.4.7 ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR + 0x0518 Table 7-10.
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Interrupt Controller 7.2.4.8 ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR + 0x051C Table 7-11.
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Interrupt Controller 7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524 Table 7-12.
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Interrupt Controller Bits Name Description 21:23 CSe Critical Status Encoded—makes a singular indication of the current critical interrupt (3bits indicating 1 of 4 possible interrupts). The msb operates as a Flag bit, as described above. This msb can also be written to 1 to force a re-evaluation of the critical interrupt sources. 00 = IRQ input pin is the source. See Note 2. 01 = Slice Timer 0 is the source. 10 = HI_int is the source. See Note 3. 11 = CCS module is the source. WakeUp from deep-sleep.
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Interrupt Controller Bits Name 0:3 — — CSa[x] Description Reserved Critical Interrupt Status All—Indicates all pending interrupts, including the currently active interrupt (if any). CSa is binary, showing each active interrupt input in its corresponding bit position. See Note 1. Number in parenthesis indicates equivalent encoded value in CSe, ICTL PerStat, MainStat, CritStat Encoded Register.
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Interrupt Controller Bits Name Description 23 MSa8 GPIO WakeUp interrupt 24 MSa9 TMR0 interrupt 25 MSa10 TMR1 interrupt 26 MSa11 TMR2 interrupt 27 MSa12 TMR3 interrupt 28 MSa13 TMR4 interrupt 29 MSa14 TMR5 interrupt 30 MSa15 TMR6 interrupt 31 MSa16 TMR7 interrupt Note: 1. All main interrupt sources are directly maskable in Main_Mask, ICTL Critical Priority and Main Interrupt Mask Register. If masked in Main_Mask, status information still shows in MSa.
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Interrupt Controller Bits Name Description 16 PSa6 USB 17 PSa7 ATA 18 PSa8 PCI Control module 19 PSa9 PCI SC Initiator Rx 20 PSa10 PCI SC Initiator Tx 21 PSa11 PSC4 22 PSa12 PSC5 23 PSa13 SPI modf 24 PSa14 SPI spif 25 PSa15 I2C1 26 PSa16 I2C2 27 PSa17 CAN1 28 PSa18 CAN2 29:30 — 31 PSa21 Reserved XLB Arbiter Note: 1. These interrupts are directly maskable by ICTL Peripheral Interrupt Mask Register.
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Interrupt Controller 7.2.4.14 ICTL Main Interrupt Emulation All Register—MBAR + 0x0540 Table 7-17.
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Interrupt Controller 7.2.4.15 ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544 Table 7-18.
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Interrupt Controller Bits Name 27 PEa17 CAN1 28 PEa18 CAN2 29:30 — 31 PEa21 7.2.4.16 Description Reserved XLB Arbiter ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 Table 7-19.
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General Purpose I/O (GPIO) 7.3 General Purpose I/O (GPIO) There are a total of 56 possible GPIO pins on the MPC5200B. Virtually all of these pins are shared with alternate hardware functions. Therefore, GPIO availability is entirely dependant on the peripheral set a particular application requires. There are 5 basic types of GPIO pins, controlled by separate register groupings, and in some cases, different register modules: • 24 “Simple” GPIO, controlled in the standard GPIO register module.
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General Purpose I/O (GPIO) Table 7-20.
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General Purpose I/O (GPIO) Table 7-20.
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General Purpose I/O (GPIO) 7.3.1 GPIO Pin Multiplexing Figure 7-3 shows the GPIO/Generic MUX cell. Alternate Func 1 IN Pin MUX Logic OUT BC Enabled Alternate Func 2 IN OUT BC Enabled I/O Cell TIMER MultiFunction I/O OUT IN BC Enabled GPIO/d/W ODconfig IN OUT Awake BC Enabled Priority Output Enable Logic Interrupt for WakeUp supported GPIO pins only Note: 1. Open-Drain Emulation is supported on the GPIO function. 2.
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General Purpose I/O (GPIO) 7.3.1.1 PSC1 (UART1/AC97/CODEC1) The PSC1 port has 5 pins with hardware support for: • CODEC • UART (4 pins consumed) • UARTe (expanded with carrier detect input–5 pins consumed) • AC97 Unused pins can serve as simple GPIOs, with one available as a WakeUp input. For use as AC97, this WakeUp GPIO becomes available. A special mode is available in which the CD input for UART use can be unused. This makes a WakeUp GPIO available on this port.
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General Purpose I/O (GPIO) Full Ethernet consumes all 18 pins, unless the optional MDIO and MDC pins are specified as unused. In this case, 2 Output Only GPIO are available. Meanwhile, there are other cases becasue many pins can be used for UART, J1850. Please Refer to the port-mapping illustrations for details.
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General Purpose I/O (GPIO) • Timer pins 6 and 7 are dedicated as Timer GPIO and have no alternate function. Although the Timer as GPIO only operates to the Simple GPIO level, Interrupt capability can be achieved by configuring the Timer for Input Capture mode. 7.3.1.9 Dedicated GPIO Port There is a dedicated GPIO port group that consists of 2 pins. Both pins operate at the WakeUp GPIO level.
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General Purpose I/O (GPIO) 7.3.2.1.1 GPS Port Configuration Register—MBAR + 0x0B00 Table 7-21.
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General Purpose I/O (GPIO) Bit Name 9:11 IRDA Description Infrared Data Association 000 = All IrDA pins are GPIOs 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = UART (without CD) / IrDA 110 = Reserved 111 = CODEC (without MCLK) / IrDA 12: 15 Ether Ethernet 0000 = All 18 Ethernet pins are GPIOs 0001 = USB2 on Ethernet, see Note 3 0010 = Ethernet 10Mbit (7-wire) mode 0011 = Ethernet 7-wire and USB2, see Note 3 0100 = Ethernet 100Mbit without MD 0101 = Ethernet 100Mbit with MD 011X =
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General Purpose I/O (GPIO) Bit Name 20:23 PSC3 Description Programmable Serial Controller 3 0000 = All PSC3 pins are GPIOs 0001 = USB2 on PSC3, no GPIOs available, see Note 3 001X = Reserved 0100 = UART functionality without CD 0101 = UARTe functionality with CD 0110 = CODEC3 functionality 0111 = CODEC3 functionality (with MCLK) 100X = SPI 101X = Reserved 1100 = SPI with UART3 1101 = SPI with UART3e 111X = SPI with CODEC3 24 — Reserved 25:27 PSC2 Programmable Serial Controller 2 000 = All PSC2 pin
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General Purpose I/O (GPIO) Table 7-22. GPS Simple GPIO Enables Register R Reserved IRDA ETHR Reserved USB W RESET: R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb Reserved PSC3 PSC2 PSC1 W RESET: 0 0 Bit Name 0:1 — 2:3 IRDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved Individual enable bits for the 2 Simple GPIO on IRDA port.
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General Purpose I/O (GPIO) Bit Name 24:27 PSC2 Description Individual enable bits for the 4 Simple GPIO on PSC2 port. bit 24 controls GPIO_PSC2_3 (PSC2_3 pin) bit 25 controls GPIO_PSC2_2 (PSC2_2 pin) bit 26 controls GPIO_PSC2_1 (PSC2_1 pin) bit 27 controls GPIO_PSC2_0 (PSC2_0 pin) 0 = Disabled for GPIO (default) 1 = Enabled for GPIO 28:31 PSC1 Individual enable bits for the 4 Simple GPIO on PSC1 port.
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General Purpose I/O (GPIO) Bit Name 12:15 USB Description Individual bits to cause open drain emulation for pins configured as GPIO output. bit 12 controls GPIO_USB_3 (USB1_8 pin) bit 13 controls GPIO_USB_2 (USB1_7 pin) bit 14 controls GPIO_USB_1 (USB1_6 pin) bit 15 controls GPIO_USB_0 (USB1_0 pin) 0 = Normal CMOS output (default) 1 = Open Drain emulation (a drive to high creates Hi-Z) 16:17 — Reserved 18:23 PSC3 Individual bits to cause open drain emulation for pins configured as GPIO output.
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General Purpose I/O (GPIO) Bit Name 0:1 — 2:3 IRDA Description Reserved Individual bits to control directionality of the pin as GPIO. bit 2 controls GPIO_IRDA_1 (IR_USB_CLK pin) bit 3 controls GPIO_IRDA_0 (IRDA_TX pin) 0 = Pin is Input (default) 1 = Pin is Output 4:7 ETHR Individual bits to control directionality of the pin as GPIO.
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General Purpose I/O (GPIO) Bit Name 24:27 PSC2 Description Individual bits to control directionality of the pin as GPIO. bit 24 controls GPIO_PSC2_3 (PSC2_3 pin) bit 25 controls GPIO_PSC2_2 (PSC2_2 pin) bit 26 controls GPIO_PSC2_1 (PSC2_1 pin) bit 27 controls GPIO_PSC2_0 (PSC2_0 pin) 0 = Pin is Input (default) 1 = Pin is Output 28:31 PSC1 Individual bits to control directionality of the pin as GPIO.
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General Purpose I/O (GPIO) 7.3.2.1.5 GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10 Table 7-25.
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General Purpose I/O (GPIO) Bit Name 24:27 PSC2 Description Individual bits to control the state of pins configured as GPIO output. bit 24 controls GPIO_PSC2_3 (PSC2_3 pin) bit 25 controls GPIO_PSC2_2 (PSC2_2 pin) bit 26 controls GPIO_PSC2_1 (PSC2_1 pin) bit 27 controls GPIO_PSC2_0 (PSC2_0 pin) 0 = Drive 0 on the pin (default) 1 = Drive 1 on the pin 28:31 PSC1 Individual bits to control the state of pins configured as GPIO output.
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General Purpose I/O (GPIO) Bit Name 12:15 USB Description Individual status bits reflecting the state of corresponding GPIO pins. bit 12 reflects GPIO_USB_3 (USB1_8 pin) bit 13 reflects GPIO_USB_2 (USB1_7 pin) bit 14 reflects GPIO_USB_1 (USB1_6 pin) bit 15 reflects GPIO_USB_0 (USB1_0 pin) 16:17 — Reserved 18:23 PSC3 Individual status bits reflecting the state of corresponding GPIO pins.
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General Purpose I/O (GPIO) Bit Name 0:7 ETHR Description Individual bits to enable each Output Only GPIO pin—all reside on the Ethernet port.
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General Purpose I/O (GPIO) Bit Name 0:7 ETHR Description Individual bits to control the state of enabled Output Only GPIO pins.
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General Purpose I/O (GPIO) Bit Name 0:7 SIGPIOE Description Individual bits to enable each Interrupt GPIO pin (pins are scattered).
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General Purpose I/O (GPIO) 7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28 Table 7-31.
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General Purpose I/O (GPIO) Bit Name 0:7 SIDVO Description Individual bits to control the state of pins configured as GPIO output.
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General Purpose I/O (GPIO) 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34 Table 7-34.
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General Purpose I/O (GPIO) Bit Name 0:2 — Reserved 3 ME GPIO Simple Interrupt Master Enable pin—This pin must be high before any Simple Interrupt pin can generate an interrupt. This bit should remain clear while programming individual interrupts, then set high as a final step. This prevents any spurious interrupt occurring during programming. 4:31 — Reserved 7.3.2.1.16 Description GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C Table 7-36.
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General Purpose I/O (GPIO) 7.3.2.2 WakeUp GPIO Registers—MBAR+0x0C00 The WakeUp GPIO Register Set provides GPIO control for the 8 WakeUp GPIO pins. These pins are scattered throughout the pin groups, but are all controlled in this module. It should be noted that WakeUp GPIO can operate as Simple Interrupt GPIO. Because of this, there are separate registers to enable these pins as Wakeup interupts and/or Simple Interrupts.
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General Purpose I/O (GPIO) 7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register —MBAR + 0x0C04 Table 7-38.
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General Purpose I/O (GPIO) Bit Name 0:7 WDDR[7:0] Description Individual bits to control directionality of the pin as GPIO. Bit 0 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin) Bit 1 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin) Bit 2 controls GPIO_WKUP_5 (PSC6_1 pin) Bit 3 controls GPIO_WKUP_4 (PSC6_0 pin) Bit 4 controls GPIO_WKUP_3 (ETH_17 pin) Bit 5 controls GPIO_WKUP_2 (PSC3_9 pin) Bit 6 controls GPIO_WKUP_1 (PSC2_4 pin) Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin) 0 = Pin is Input (default). 1 = Pin is Output.
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General Purpose I/O (GPIO) 7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register—MBAR + 0x0C10 Table 7-41.
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General Purpose I/O (GPIO) Bit Name 0:7 WINe Description Individual bits to enable generation of Simple interrupt for WakeUp GPIO configured as input.
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General Purpose I/O (GPIO) Bit Name 0:1 Ityp7 2:3 Ityp6 4:5 Ityp5 6:7 Ityp4 8:9 Ityp3 10:11 Ityp2 12:13 Ityp1 14:15 Ityp0 Description GPIO Interrupt Type bits for WakeUp GPIO pins 7–0 00=Interrupt at any transition 01=Interrupt on rising edge 10=Interrupt on falling edge 11=Interrupt on pulse (any 2 transitions) The above interrupt types describe operation for interrupts occuring while MPC5200B is not in Deep Sleep mode (i.e., Simple Interrupt types).
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General Purpose I/O (GPIO) Bit Name 0:6 — Reserved 7 ME WakeUp GPIO Master Enable pin. This pin must be high before any WakeUp GPIO pin can generate an interrupt. This bit should remain clear while programming individual interrupts and then set high as a final step. This prevents any spurious interrupt occuring during programming. 8:31 — Reserved 7.3.2.2.9 Description GPW WakeUp GPIO Data Input Values Register —MBAR + 0x0C20 Table 7-45.
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General Purpose I/O (GPIO) 7.3.2.2.10 GPW WakeUp GPIO Status Register—MBAR + 0x0C24 Table 7-46.
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General Purpose Timers (GPT) 7.4 General Purpose Timers (GPT) Eight (8) General-Purpose Timer (GPT) pins are configurable for: • Input Capture • Output Compare • Pulse Width Modulation (PWM) Output • Simple GPIO • Internal CPU timer • Watchdog Timer (on GPT0 only) Timer modules run off the internal IP bus clock. Each Timer is associated to a single I/O pin. Each Timer has a 16-bit prescaler and 16-bit counter, thus achieving a 32-bit range (but only 16-bit resolution). 7.4.
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General Purpose Timers (GPT) 7.4.4 GPT Registers—MBAR + 0x0600 Each GPT uses 4 32-bit registers. These registers are located at an offset from MBAR of 0x0600. Register addresses are relative to this offset.
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General Purpose Timers (GPT) Bit Name Description 0:7 OCPW Output Compare Pulse Width—Applies to OC Pulse types only. This field specifies the number of IP bus clocks (non-prescaled) to create a short output pulse at each Output Event. This pulse is generated at the end of the OC period and overlays the next OC period (rather than adding to the period). Note: This field is alternately used as the Watchdog reset field if Watchdog Timer mode is enabled.
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General Purpose Timers (GPT) Bit Name 21 Stop_Cont Description Stop Continuous—Applies to multiple modes, as follows: 0 = Stop 1 = Continuous • IC mode Stop operation—At each IC event, counter is reset. Continuous operation—counter is not reset at each IC event. Effect is to create Status count values that are cumulative between Capture events. If the special Pulse Mode Capture type is specified, the Stop_Cont bit is not used, operation fixed as if it were Stop.
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General Purpose Timers (GPT) Bit Name Description 28 — 29:31 Timer_MS Reserved Timer Mode Select (and module enable). 000=Timer module not enabled. Associated I/O pin is in input state. All Timer operation is completely disabled. Control and status registers are still accessible. This mode should be entered when timer is to be re-configured, except where the user does not want the I/O pin to become an input. 001=Timer enabled for input capture. 010=Timer enabled for output compare.
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General Purpose Timers (GPT) Bit Name Description 0:15 Prescale Prescale amount applied to internal counter (in IP bus clocks). BE AWARE—The prescale field should be written prior to enabling any timer mode. A prescale of 0x0001 means one IP bus clock per count increment. If prescale is 0 when any timer mode is started, it results in an effective prescale of 64K. The counter will immediately begin and an output event will occur with the 64K prescale, rather than the desired value.
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General Purpose Timers (GPT) Bit Name Description 23 PWMOP Pulse Width Mode Output Polarity—Defines PWM output polarity for OFF time. Opposite state is ON time polarity. PWM cycles begin with ON time. 24:30 — 31 LOAD Reserved Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with the current count and width settings. If LOAD = 0, new count or width settings are not updated until end of current period. Note: Prescale setting is not part of this process.
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Slice Timers Bit Name Description 17:19 OVF Represents how many times internal counter has rolled over. This is pertinent only during IC mode and would represent an extremely long period of time between Input Events. However, if Stop_Cont = 1 (indicating cumulative reporting of Input Events), this field could come into play. Note: This field is cleared by any “sticky bit” status write in the 4 bit fields below (28, 29, 30, 31).
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Slice Timers 7.5.1.1 SLT 0 Terminal Count Register—MBAR + 0x0700 SLT 1 Terminal Count Register—MBAR + 0x0710 Table 7-51.
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Slice Timers Bit Name 0:4 — 5 Run_ Wait A high indicates the Timer should run continuously while enabled. When the Timer counter reaches terminal count it immediately resets to 0 and resumes counting. If the Run/Wait bit is set low, the Timer Counter expires, but then waits until the Timer is cleared (either by writing 1 to the status bit or by disabling and re-enabling the Timer), before resuming operation. 6 Interrupt Enable CPU Interrupt is generated only if this bit is high.
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Real-Time Clock 7.5.1.4 SLT 0 Timer Status Register—MBAR + 0x070C SLT 1 Timer Status Register—MBAR + 0x071C Table 7-54. SLT 0 Timer Status Register SLT 1 Timer Status Register msb 0 1 2 3 4 5 6 Reserved R 7 8 9 10 ST 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Reserved R W RESET: 7.
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Real-Time Clock Periodic interrupts are separately enabled by control bits, and a global enable must be asserted to allow any of the periodic sources to generate a CPU interrupt. Clearing Periodic interrupts is accomplished by writing 1 to the appropriate status bit. Stopwatch and Alarm interrupts are enabled simply by initiating the function. In the Stopwatch case, this means starting the Stopwatch, in the Alarm case, this means enabling the Alarm.
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Real-Time Clock • RTC New Year and Stopwatch Register (0x0808) • RTC Periodic Interrupt and Bus Error Register (0x081C), read-only • RTC Alarm and Interrupt Enable Register (0x080C) • RTC Test Register/Divides Register (0x0820) • RTC Current Time Register (0x0810), read-only 7.6.3.1 RTC Time Set Register—MBAR + 0x0800 Table 7-56.
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Real-Time Clock Bits Name Description 18:23 Minute_set Minute written in RTC after successful state machine transition by set_time and pause_time bits. 24:25 — 26:31 Second_set 7.6.3.2 Reserved Second written in RTC after successful state machine transition by set_time and pause_time bits. RTC Date Set Register—MBAR + 0x0804 Table 7-57.
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Real-Time Clock 7.6.3.3 RTC New Year and Stopwatch Register—MBAR + 0x0808 Table 7-58.
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Real-Time Clock Bits Name Description 8:10 — 11:15 Alm_24Hset 16:17 — 18:23 Alm_Min_set 24:27 — 28 MPEb 29 IntEn_day Enable bit of periodic interrupts at midnight rollover. 30 IntEn_min Enable bit of periodic interrupts at minute rollover. 31 IntEn_sec Enable bit of periodic interrupts at second rollover. Reserved Hour setting (in 24 hour format) to be compared to time of day for the purpose of generating Alarm Status/Interrupt. Can be written at any time.
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Real-Time Clock Bits Name 24:25 — 26:31 Second 7.6.3.6 Description Reserved Shows seconds in current time. RTC Current Date Register—MBAR + 0x0814 This is a read-only register. Table 7-61.
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Real-Time Clock Bits Name 0:6 — 7 Int_alm Description Reserved Status bit indicating that enabled once-a-day Alarm has occurred (active high). Alarm interrupt has been activated. This bit and the Interrupt is cleared by writing 1 to this bit position. Note: A Stopwatch interrupt, if also active, must be cleared before the interrupt signal to the CPU is negated. 8:14 — 15 Int_SW Reserved Status bit indicating that Stopwatch expiration has occurred (active high).
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Real-Time Clock Bits Name 16:22 — 23 Int_min Description Reserved Periodic interrupt at each minute rollover. High indicates interrupt has occurred. Cleared by writing 1 to this bit position. 24:30 — Reserved 31 Int_sec Periodic interrupt at each second rollover. High indicates interrupt has occurred. Cleared by writing 1 to this bit position. 7.6.3.
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Real-Time Clock MPC5200B Users Guide, Rev.
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Overview Chapter 8 SDRAM Memory Controller 8.1 Overview The following sections are contained in this document: • Section 8.2, Terminology and Notation • Section 8.3, Features — Section 8.3.1, Devices Supported • Section 8.4, Functional Description — Section 8.4.1, External Signals (SDRAM Side) — Section 8.4.2, Block Diagram — Section 8.4.3, Transfer Size — Section 8.4.4, Commands • Section 8.5, Operation — Section 8.5.1, Power-Up Initialization • Section 8.6, Programming the SDRAM Controller • Section 8.
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Features stripped along the way). Nor is the transportation of data an execution context. Without knowledge of atom boundaries and significance (if any), the following convention is the de facto standard: • “Bit significance, byte address”: From every observation point in a system, the relative address order of bytes shall be maintained, and the relative significance of bits within each individual byte shall be maintained, as if they represented an 8 bit unsigned binary integer.
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Features — 2 bits of bank address (BA[1:0]) NOTE In this document the Auto Precharge control signal (A10 usually), conveyed on the memory address bus along with column address, is never included in the stated CA width; it is always in addition to the CA width. The Memory Controller does not support memory devices with >9 CA bits, but <13 RA bits. RA[12:0] correspond directly with MEM_MA[12:0]. CA[7:0] correspond directly with MEM_MA[7:0]. CA[11:8] do not correspond directly with MEM_MA[12:8].
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Features Table 8-1.
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Features Table 8-1.
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Features Table 8-1.
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Features Table 8-1.
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Features Table 8-1.
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Features Table 8-1. 32-Bit External Data Width Legal Memory Configurations (continued) Row Bits Column Bits Bank Bits Spaces (CS) 13 9 2 1 Physical Address Range 2 x 512Mb 8M x 4bank x 32bit 384MB + 13 11 2 1 2 x 1Gb 16M x 4bank x 32bit 12 11 2 1 1 x 1Gb 8M x 4bank x 32bit 12 12 2 1 1 x 2Gb 16M x 4bank x 32bit 13 10 2 1 1 x 1Gb 8M x 4bank x 32bit 384MB + 384MB + 13 11 2 1 1 x 2Gb 16M x 4bank x 32bit Table 8-2.
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Features Table 8-2.
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Features Table 8-2.
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Features Table 8-2.
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Features Table 8-2. 16-Bit External Data Width Legal Memory Configurations (continued) Row Bits Column Bits Bank Bits Spaces (CS) 13 11 2 1 Physical Address Range 2 x 512Mb 16M x 4bank x 8bit 256MB + 13 11 2 1 1 x 1Gb 16M x 4bank x 16bit MPC5200B Users Guide, Rev.
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Features Figure 8-1 shows an example memory configuration of 1 space (CS) of 4 devices of 128Mbit (4M x 4 banks x 8bit) DDR SDRAM, for a total memory size of 64MB.
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Functional Description 8.4 Functional Description 8.4.1 External Signals (SDRAM Side) Table 8-3. SDRAM External Signals Signal Name Description Outputs MEM_CLK Memory Clock (frequency is the same as the internal XL bus clock). Maximum allowed value is 132 MHz. MEM_CLK Inverted Memory Clock, used for DDR-SDRAM devices. Internally generated “DQS” for SDR-SDRAM devices. MEM_CLK_EN MEM_CS[0], MEM_CS[1] Memory Clock Enable (CKE). When low, the SDRAM is disabled.
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Functional Description 8.4.2 Block Diagram Figure 8-2 shows the SDRAM MC block diagram. It is important to notice: • the internal XL bus is 64 bits wide • the external interface to the SDRAM is only 32 bits wide Internal XL bus The SDRAM row, column, and bank address bits are extracted from internal address XLA[4:29]; XLA[29:31], TSIZ[0:2], and TBST control the data path (MDQ, DQM).
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Functional Description modulo 8 boundary within the modulo 32 range; the address “wraps” from the highest address to the lowest address of the range if the starting address is not aligned at the beginning of the range. No data is masked during a burst. The beat address order of the XL bus is sequential.
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Functional Description Some of the configuration parameters required by the memory are also needed by the Memory Controller for command generation. The parameters are: • burst length • latency These must be programmed in the Memory Controller Configuration registers separately from setting the memory Mode register. 8.4.4.
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Operation With both SDR and DDR memory, a Read command can be issued overlapping the masked beats at the end of a previous Single Write of the same CS; the Read command aborts the remaining (unnecessary) Write beats. With DDR memory, a Read of one CS can even overlap the masked beats at the end of a previous Single Write of the other CS. The Write is not aborted, but the masks remain asserted. This is not possible with SDR memory, because SDR memory cannot be read with the masks asserted. 8.4.4.
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Programming the SDRAM Controller If all the memory and controller register values have been precalculated and stored in ROM, skip step 3 and go directly to step 4. Otherwise, continue with step 3. Step 3. Read the SDRAM parameters (type, size, address muxing, timing), and determine the memory clock frequency. (The memory clock frequency is always equal to the XLB frequency.) Using the SDRAM parameters and the clock frequency, calculate all the memory and controller register values now.
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Memory Controller Registers (MBAR+0x0100:0x010C) Table 8-5. Memory Controller Mode Register msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 R W RESET: 14 15 Rsvd MEM_MBA [1:0] MEM_MA[11:0] cmd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Reserved R W RESET: 0 0 0 0 0 0 0 0 0 Bit Name Description 0:1 MEM_MBA [1:0] See SDRAM data sheet.
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Memory Controller Registers (MBAR+0x0100:0x010C) 8.7.2 Control Register—MBAR + 0x0104 The 32-bit read/write Control register controls specific operations and generates some SDRAM commands. This register is reset only by a power-up reset signal. Table 8-6.
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Memory Controller Registers (MBAR+0x0100:0x010C) Bit Name 10:15 ref_interval[0:5] Description The average periodic interval at which the controller generates refresh commands to memory; measured in increments of 64 x MEM_CLK period. 1) Multiply tREFI by the MEM_CLK frequency. (If the memory data sheet does not define tREFI, it can be calculated by tREFI = tREF / #rows.) Example: Assume tREF = 64ms, #rows = 4K, MEM_CLK = 133MHz. Then: tREFI = 64ms / 4K = 15.625µs; 15.625µs x 133MHz = 2078.
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Memory Controller Registers (MBAR+0x0100:0x010C) Table 8-8.
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Memory Controller Registers (MBAR+0x0100:0x010C) Table 8-9.
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Memory Controller Registers (MBAR+0x0100:0x010C) MEM_CLK2—double frequency of MEM_CLK—DDR uses both edges of the bus-frequency clock (MEM_CLK) to read/write data. Table 8-10.
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Memory Controller Registers (MBAR+0x0100:0x010C) Bit Name 16 — 17:19 pre2act Description Reserved Precharge to Active or Refresh delay. Suggested value at 132 MHz = 0x02 Rule: tRP/MEM_CLK-1. Round up to nearest integer. EXAMPLE: If tRP = 20ns and MEM_CLK = 99 MHz 20ns / 10.1 ns = 1.98; round to 2; write 0x1. If tRP = 20 ns and MEM_CLK = 132 MHz 20ns / 7.5 ns = 2.66; round to 3; write 0x2. 20:23 ref2act Refresh to Active delay. Suggested value at 132 MHz = 0x9 Rule: tRFC/MEM_CLK - 1.
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Memory Controller Registers (MBAR+0x0100:0x010C) Bit Name 0:3 brd2rp Description Burst Read to Read/Precharge delay. Limiting case is Read to Read. For DDR, suggested value = 0x4 (BurstLength/2) For SDR, suggested value = 0x8 (BurstLength) 4:7 bwt2rwp Burst Write to Read/Write/Precharge delay. Limiting case is Write to Precharge. For DDR, suggested value = 0x6 (BurstLength/2 + tWR) For SDR, suggested value = 0x8 (BurstLength + tWR - 2) 8:11 brd2wt Burst Read to Read/Write/Precharge delay.
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Memory Controller Registers (MBAR+0x0100:0x010C) The Figure 8-3. Programmable Command Timings shows the timings which can be programmed by the two Controller Configuration Register. The timing diagram uses the suggested values for a DDR memory and a 132 MHz memory clock. The displayed Commands are the limiting cases.
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Address Bus Mapping 8.8 Address Bus Mapping This is an illustration of how the XL bus address enters the Memory Controller and is broken down into Row, Column, and Bank Address fields. Shown below is the 32-bit XL bus address. The Memory Controller uses bits 4:31.
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Address Bus Mapping This is an illustration of how the XL bus address enters the Memory Controller and is broken down into Row, Column, and Bank Address fields. Shown below is the 32-bit XL bus address. The Memory Controller uses bits [27:0].
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Address Bus Mapping By default, the Memory Controller only provides 12 row address bits and 12 column address bits. To enable the 13th row address bit, the hi_addr bit of the Control register must be set to 1 (MBAR+0x0104, Control[7]). This also reduces the column address width to 11 bits. MPC5200B Users Guide, Rev.
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Overview Chapter 9 LocalPlus Bus (External Bus Interface) 9.1 Overview The LocalPlus Bus is the external bus interface of the MPC5200B. This multi-function bus system supports interfacing to external Boot ROM or Flash memories, external SRAM memories or other memory mapped devices. The following sections are contained herein: • Section 9.1, Overview • Section 9.2, Features • Section 9.3, Interface — Section 9.3.1, External Signals — Section 9.3.2, Block Diagram • Section 9.
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Interface – (Address 8, 16, 24 or 25 bits, Data 8,16 or 32 bits, 2 Bank Selects) 8 Chip Select (CS) signals — Programmable Wait States per CS — Programmable Deadcycles per CS — Programmable Byte Swapping per CS Configurable Boot interface supporting PowerPC architecture code execution Dynamic bus sizing on some interfaces Support of BURST MODE FLASH devices DMA (BestComm) support allows data movement independently from the CPU NO support of misaligned accesses • • • • • • 9.
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Interface 9.3.2 Block Diagram The block diagram of the LocalPlus Controller (LPC) is shown in Figure 9-1. This diagram shows the non-multiplexed implementation of address and data lines. The LPC is driven by the internal IP bus clock and the PCI_CLOCK. The supported ratios of the IP bus clock to the reference clock PCI_CLOCK (the one externally seen by peripherals) are 4:1, 2:1 and 1:1. The reference clock is the PCI_CLOCK and all clock counts are referred to this clock.
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Modes of Operation Peripheral MPC5200 DATA[31:0] AD[31:0] AD Bus ALE Bank Bits Address External Logic ADD[6:5] ADD[31:7] TSIZ[0:2] LPC Interface TS CS TS CS ACK ACK Figure 9-2. Muxed Mode Address Latching 9.4 Modes of Operation There are 2 primary modes of operation: • MUXed • non-MUXed (Legacy, Large Flash, Most/Graphic modes, Burst and Non-Burst) Within each mode, there is considerable flexibility to control the operation.
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Modes of Operation Table 9-2. Non-Muxed Mode Options Category Address Size Data Size Pins used Memory size Comments Small 8 8 16 256 Bytes Legacy Mode Small 8 16 24 256 Bytes Legacy Mode Small 16 8 24 64 kBytes Legacy Mode Small 16 16 32 64 kBytes Legacy Mode (BOOT OPTION) Medium 24 8 32 16 MBytes Legacy Mode (BOOT OPTION) MOST/G 24 32 56 16 MBytes MOST Graphics (BOOT OPTION) Burst support.
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Modes of Operation CS[x] ADDR Valid Address OE R/W DATA (wr) Valid write Data Valid read Data DATA (rd) ACK TS TSIZ[1:2] NOTE: 1. ACK can shorten the CS pulse width. 2. TS is only available in Large Flash and MOST Graphics mode. Figure 9-4. Timing Diagram—Non-MUXed Mode PCI CLK CS[x] ADDR Valid Address OE R/W Valid read Data DATA (rd) ACK TS NOTE: 1. Burst Mode is only available for Large Flash and MOST Graphics mode. 2. ACK is output and indicates the burst. Figure 9-5.
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Modes of Operation In this mode, the peripheral address and data lines are limited to a total of 32 in Legacy Modes, to 40 or 48 in Large Flash or to 56 in MOST Graphics mode. They are driven/read simultaneously on the external AD bus. A single dedicated R/W pin is driven to indicate read or write. An individually dedicated CS pin is driven low while an external access is active. Wait states are programmable and simply select how many PCI clocks the CS pin (and related signals) remain asserted.
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Modes of Operation The MUXed mode requires external logic to latch the address during the address tenure and to decode bank selects if they are encoded. This mode is slower than the non-MUXed mode because data and address are multiplexed in time. The supported address space is limited by the 25 address lines. In MUXed mode, LocalPlus can access up to 128 MBytes of data divided into four banks each of 32 MBytes maximum. 9.4.2.
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Configuration Figure 9-6 shows a MUXed transaction type timing diagram. PCI CLK AD[31,27] (wr) valid write Data AD[30:28] (wr) TSIZ[0:2] bits valid write Data AD[26:25] (wr) Bank[0:1] bits valid write Data AD[24:0] (wr) Address[7:31] valid write Data valid read Data AD[31:0] (rd) ALE TS CSx OE RW ACK Address tenure Data tenure NOTE: 1. ACK can shorten the CS pulse width. 2. Address should be latched with the rising edge of ALE. Figure 9-6. Timing Diagram—MUXed Mode 9.
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Configuration • The boot address/exception table can be located at 0x0000 0100 or 0xfff0 0100. The PowerPC architecture compatible processor core requires 64-bit instruction fetches. During boot code accesses from CS Boot space on-chip logic is provided to perform enough LocalPlus accesses to accumulate 64-bit instructions to be given to the e300 processor.
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DMA (BestComm) Interface (SCLPC) • BootSwap Table 9-1 describes possible boot settings. Table 9-6. BOOT_CONFIG (RST_CONFIG) Options Parameter If Pulled Down (0) If Pulled Up (1) BootType non-MUXed boot mode MUXed boot mode BootSize non-MUXed type: non-MUXed type: 8-bit data 16-bit data 24-bit address 16-bit address MUXed type: 16-bit data (25 bit address) Notes MUXed type: 32-bit data (25 bit address) BootMostGr aphics MostGraphics boot mode.
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Programmer’s Model • Section 9-7, Chip Select 0/Boot Configuration Register (0x0300) • Section 9-10, Chip Select Status Register (0x031C) • Section 9-11, Chip Select Burst Control Register (0x0328) • Section 9-12, Chip Select Deadcycle Control Register (0x032C) MPC5200B Users Guide, Rev.
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Programmer’s Model 9.7.1.1 Chip Select 0/Boot Configuration Register—MBAR + 0x0300 Table 9-7.
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Programmer’s Model Bits Name Description 20:21 AS Address Size field—defines size of peripheral Address bus (in bytes) and must be consistent with physical connections. 00 = 8 bits 01 = 16 bits 10 = 24 bits 11 = > 25 bits See documentation for Physical Connection requirements. The combination of address size, data size, and transaction type (MX) must be consistent with the peripheral physical connection.
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Programmer’s Model Bits Name 30 WO Description Write Only bit—If bit is high, the peripheral is treated as a write-only device. An attempted read access results in a bus error (as dictated by Chip Select Contro Register EBEE bit) and/or an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction is presented to the peripheral. A bus error means the internal cycle is terminated with a transfer error acknowledge (ips_xfr_err assertion to IP bus, TEA assertion to XL bus).
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Programmer’s Model Bits Name Description 16 MX MX bit specifies whether transaction operates as multiplexed or non-multiplexed. A multiplexed transaction presents address and data in different tenures. During the address tenure, ALE is asserted. At the end of ALE, AD bus is switched to data tenure and CSx pin is asserted. 0 = Non-multiplexed 1 = Multiplexed 17 — Reserved 18 AA ACK Active—multiplexed transactions only. This bit defines whether ALK input is active or not.
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Programmer’s Model Bits Name 28 WS Description Write Swap bit—If high, Endian byte swapping occurs during writes to a peripheral. • • • For 8-bit peripherals, this bit has no effect. For 16-bit peripherals, byte swapping can occur. For 32-bit peripherals (possible in MUXed mode only) byte swap can occur. 1 = swap 0 = NO swap 2-byte swap is AB to BA, 4-byte swap is ABCD to DCBA. Note: Transactions at less than the defined port size (i.e.
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Programmer’s Model Bits Name 0:6 — Reserved 7 ME Master Enable bit—a global module enable bit. If this bit is low, register access can still occur, but no external transactions are accepted. However, ME does not affect boot ROM operation on CS[0]. If software wishes to disable CS[0], it must write 0 to the Chip Select Boot ROM Configuration Register enable bit (CE). 8:31 — Reserved 9.7.1.4 Description Chip Select Status Register—MBAR + 0x031C Table 9-10.
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Programmer’s Model W RESET: 0 0 0 0 20 21 CW2 SLB2 0 0 22 Rsvd 0 23 0 24 25 CW1 SLB1 0 0 26 Rsvd 0 27 0 28 29 CW0 SLB0 0 0 30 Rsvd 0 31 lsb BRE0 Rsvd 19 BRE1 CW3 SLB3 18 BRE2 R 17 BRE3 16 0 Bits Name Description 0 CW7 Chip Select 7 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit setting only applies in Large Flash or MOST Graphics Mode. 1 SLB7 Chip Select 7 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable.
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Programmer’s Model Bits Name Description 13 SLB4 Chip Select 4 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable. Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also). This bit setting only applies in Large Flash or MOST Graphics Mode.
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Programmer’s Model Bits Name Description 28 CW0 Chip Select 0 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit setting only applies in Large Flash or MOST Graphics Mode. 29 SLB0 Chip Select 0 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is 8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
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Programmer’s Model Bits Name 12:13 — 14:15 DC4 16:17 — 18:19 DC3 20:21 — 22:23 DC2 24:25 — 26:27 DC1 28:29 — 30:31 DC0 Description Reserved Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 4 read access and will occur in addition to any cycles which may already exist. These cycles are to provide peripheral additional time to tri-state it's bus after a read operation. This is for all access types. Reserved Deadcycles can be specified as 0 to 3.
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Programmer’s Model 9.7.2 SCLPC Registers—MBAR + 0x3C00 There are 6 32-bit BestComm Registers for the LocalPlus (SCLPC). These registers are located at an offset from MBAR of 0x3C00. Register addresses are relative to this offset.
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Programmer’s Model 9.7.2.2 SCLPC Start Address Register—MBAR + 0x3C04 Table 9-14. SCLPC Start Address Register msb 0 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 Start Address W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Start Address W RESET: 0 0 0 0 0 0 0 0 0 Bits Name Description 0:31 Start Address Address of the first byte in the packet to be sent.
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Programmer’s Model Bits Name 16:22 — 23 DAI Description Reserved Disable Auto Increment. Normally, SCLPC and LPC will present sequential incrementing addresses to the peripheral as the Packet proceeds. If the peripheral is operating as a single address Fifo, then the DAI bit should be set to 1. When set, addresses to the peripheral will be stuck at Start_Address for every transaction. For DAI operation, the BPT field *MUST* be set to the port size of the peripheral.
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LocalPlus Bus (External Bus Interface) Bits Name 22 AIE Notes Description Abort Interrupt Enable. If set, and a fifo error occurs during packet transmission, a cpu interrupt from SCLPC will be generated. In any case, the Packet will be terminated and an Abort Status bit will be set. Note: This bit does *not* affect the Requestor to BestComm in any way. 23 NIE Normal Interrupt Enable. This bit, if set enables a cpu interrupt to occur at the end of a normally terminated Packet.
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Programmer’s Model Bits Name 7 NT Description Normal Termination. This bit is set to 1 whenever a complete Packet has been transferred successfully. Note: This bit is ANDed with the NIE bit above to generate a single CPU interrupt signal to the core. This bit is "sticky write to 1" for clearing the bit and clearing the interrupt. 8:31 Bytes Done Bytes Done is updated dynamically by the SCLPC state machine to represent the actual number of bytes transmitted at a given point in time.
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Programmer’s Model 9.7.3 SCLPC FIFO Registers—MBAR + 0x3C40 LPC uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction change and flushes FIFO before changing directions. FIFO memory is 512Bytes (32 x 128). LPC FIFO is controlled by six 32-bit registers. These registers are located at an offset from MBAR of 0x3C40. Register addresses are relative to this offset.
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Programmer’s Model Bits Name Description 0:31 FIFO_Data_Word The FIFO data port. Reading from this location “pops” data from the FIFO, writing “pushes” data into the FIFO. During normal operation the BestComm Controller pushes data here. Note: ONLY full word access is allowed. If all byte enables are not asserted when accessing this location, a FIFO error flag is generated. 9.7.3.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44 Table 9-19.
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Programmer’s Model 9.7.3.3 LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48 Table 9-20.
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Programmer’s Model 9.7.3.5 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50 Table 9-22. LPC Rx/Tx FIFO Read Pointer Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 R Reserved ReadPtr W RESET: 0 0 Bits Name 0:22 — 23:31 ReadPtr 9.7.3.
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LocalPlus Bus (External Bus Interface) Notes MPC5200B Users Guide, Rev.
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Overview Chapter 10 PCI Controller 10.1 Overview The Peripheral Component Interface (PCI) Bus is a high-performance bus with multiplexed address and data lines. It is especially suitable for high data-rate applications. The MPC5200B PCI Controller module supports a 32-bit PCI initiator and target interface. As a target, access to the internal XL bus is supported.
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PCI External Signals 10.1.2 Block Diagram PCI Arbiter Req/Gnt PCI Controller Block Config Master bus/ CommBus Initiator CommBus XL bus Slave bus Master bus Target External REQ/GNT PCI Controller External Config Interface PCI bus Target Interface Initiator Interface Figure 10-1. PCI Block Diagram 10.2 PCI External Signals Table 10-1. PCI External Signals Signal I/O Definition AD[31:0] I/O Multiplexed Address and Data Bus (Shared with ATA and LPC).
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PCI External Signals For detailed description of the PCI bus signals, see the PCI Local Bus Specification, Revision 2.2. 10.2.1 PCI_AD[31:0] - Address/Data Bus The PCI_AD[31:0] lines are a time multiplexed address data bus. The address is presented on the bus during the address phase while the data is presented on the bus during one or more data phases. 10.2.2 PCI_CBE[3:0] - Command/Byte Enables The PCI_CBE[3:0] lines are time multiplexed.
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Registers 10.3 Registers MPC5200B has several sets of registers that control and report status for the different interfaces to the PCI controller: PCI Type 0 Configuration Space Registers, General Status/Control Registers, and Communication Sub-System Interface Registers. All of these registers are accessible as offsets of MBAR (the PCI interface is located starting at offset 0x0D00 relative to the MBAR register’s value, while the BestComm interface starts at offset 0x3800).
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Registers Table 10-2. PCI Register Map (continued) Register Offset Mnemonic Name 0x74 PCIIW1BTAR Initiator Window 1 Base/Translation Address Register 0x78 PCIIW2BTAR Initiator Window 2 Base/Translation Address Register Reserved 0x7C 0x80 PCIIWCR Initiator Window Configuration Register 0x84 PCIICR Initiator Control Register 0x88 PCIISR Initiator Status Register 0x8C PCIARB PCI Arbiter Register 0x90 Reserved ...
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Registers Table 10-3. PCI Communication System Interface Register Map (continued) Register Offset Mnemonic Name Reserved 0x58 ... 0x7C 0x80 PCIRPSR Rx Packet Size 0x84 PCIRSAR Rx Start Address 0x88 PCIRTCR Rx Transaction Control Register 0x8C PCIRER Rx Enables 0x90 PCIRNAR Rx Next Address 0x94 PCIRLWR Rx Last Word 0x98 PCIRDCR Rx Bytes Done Counts 0x9C PCIRSR Rx Status 0xA0 PCIRPDCR Rx Packets Done Counts 0xA4 Reserved ...
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Registers 0x108 0x02 PCICCRIR Class Code 0x10C 0x03 PCICR1 0x110 0x04 PCIBAR0 BAR0 0x114 0x05 PCIBAR0 BAR1 0x118 0x06 ... ... 0x124 0x09 0x128 0x0A PCICCPR 0x12C 0x0B PCISID 0x130 0x0C Expansion ROM Base Address 0x134 0x0D Reserved 0x138 0x0E 0x13C 0x0F na 0x10 na ...
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Registers 10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) —MBAR + 0x0D04 msb 0 1 2 3 4 R PE SE MA TR TS W rwc rwc rwc rwc rwc RESET: 0 0 0 0 0 16 17 18 R 19 20 5 6 DT 7 8 9 10 11 DP FC R 66M C 12 13 14 15 Reserved rwc 0 1 0 1 0 1 0 0 0 0 0 21 22 23 24 25 26 27 28 29 30 31 lsb F S St PER V MW Sp B M IO 0 0 0 0 0 0 0 0 0 0 Reserved W RESET: 0 0 0 0 0 0 Bits 31-27 and 24 are read-write-clear (RWC).
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Registers Bits Name Description 9 Reserved (R) Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (User Defined Features) Supported bit. 1 = Supported User Defined Features 0 = Does not support UDF 10 66 MHz Capable (66M) 11 Capabilities List (C) 12:21 Reserved 22 23 Fixed to 1. This bit indicates that the PCI controller is 66 MHz capable. Fixed to 0.
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Registers Bits Name 30 Memory Access Control (M) 31 10.3.1.3 Description This bit controls the PCI controller’s response to Memory Space accesses. A value of 0 disables the response. A value of 1 allows the controller to recognize a Memory access. This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles). IO access Control (IO) Fixed to 0. This bit is not implemented because there is no MPC5200B IO type space accessible from the PCI bus.
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Registers Bits Name Description 0:7 Built-In Self Test (BIST) Fixed to 0x00. The PCI controller does not implement the Built-In Self Test register. Initialization software should write a 0x00 to this register location. 8:15 Header Type Fixed to 0x00. The PCI controller implements a Type 0 PCI Configuration Space Header. Initialization software should write a 0x00 to this register location.
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Registers 10.3.1.6 Base Address Register 1 PCIBAR1(RW) —MBAR + 0x0D14 msb 0 R W RESET 1 2 3 4 5 6 7 Base Address 1 8 9 10 11 12 13 14 15 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 R Reserved pref range 31 lsb IO/M# W RESET 0 0 Bits Name 0:1 Base Address Register 1 (BAR1) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Description MPC5200B PCI Base Address Register 1 (1Gbyte).
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Registers 10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)—MBAR + 0x0D34 Not implemented. Fixed to 0x00000000. 10.3.1.
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Registers R 16 17 18 19 Rsvd BME PEE SEE 0 0 0 0 20 21 22 23 24 25 26 27 28 29 30 31 lsb Reserved PR W RESET Bits Name 0 Reserved 1 Broken Master Detected (BM) 0 0 0 0 0 0 0 0 0 0 0 1 Description Unused bit. Software should write zero to this register. This bit is set when the PCI Arbiter detects a broken external PCI master.
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Registers 20:30 Reserved 31 PCI Reset (PR) Unused bits. Software should write zero to this register. This bit controls the external PCI RST. When this bit is cleared, the external PCI RST deasserts. Setting this bit does not reset the internal PCI controller. The application software must not initiate PCI transactions while this bit is set. It is recommended that this bit be programmed last. The reset value of the bit is 1 (PCI RST asserted).
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Registers 10.3.2.
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Registers Bits Name Description 0:1 Base Address Translation 1 This base address register corresponds to a hit on the BAR1 in MPC5200B PCI Type 0 Configuration space register (PCI space). When there is a hit on MPC5200B PCI BAR1 (MPC5200B as Target), the upper 2 bits of the external PCI address (1Gbyte boundary) are written over by this register value to address some 1Gbyte space in MPC5200B.
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Registers 23 Write Combine This control bit applies only when MPC5200 is Target. When set, it prevents the PCI Disable Controller from automatically combining write data to be sent out on the XL bus as a burst, (WCD) if possible. Instead, data is transferred as soon as possible on the XL bus as single-beat transactions. Better target write performance is achieved when this bit cleared.
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Registers 16:23 24:31 10.3.2.6 Window 0 Translation Address For any translated bit (described above), the corresponding value here will be driven onto the PCI address bus for the XL bus Window 0 address hit. Note: The Window Translation operation can not be turned off. If a direct mapping from XL Bus to PCI space is desired, program the same value to both the Window Base Address Register and Window Translation Address Register. Reserved Unused bits. Software should write zero to this register.
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Registers 10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) —MBAR + 0x0D78 msb 0 1 2 R 3 4 5 6 7 8 9 Window 2 Base Address 10 11 12 13 14 15 Window 2 Address Mask W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 R Window 2 Translation Address Reserved W RESET 10.3.2.
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Registers 8:11 12:15 Reserved Reserved register. Write a zero to this register. Window 1Control Bit[3] - IO/M#. [3:0] Bit[2:1] - PRC. Bit[0] - Enable. 16:19 20:23 Reserved Reserved register. Write a zero to this register. Window 0 Control Bit[3] - IO/M#. [3:0] Bit[2:1] - PRC. Bit[0] - Enable. 24:31 10.3.2.9 Reserved Reserved register. Write a zero to this register.
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Registers 10.3.2.
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Registers 7 PCI Arbiter Soft This bit puts the PCI Arbiter in a reset condition. Reset (ASR) 1 = reset the PCI Arbiter 0 = release the PCI Arbiter Note: Resetting the PCI arbiter will disrupt any related transaction in progress and should be reserved only for error conditions, or when it is known that no PCI or AD bus transactions are in progress. 8:31 10.3.2.12 Reserved Configuration Address Register PCICAR (RW) —MBAR + 0x0DF8 msb 0 R Unused bits. Software should write zero to this register.
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Registers 10.3.3.1.1 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 0 0 0 0 0 0 30 31 lsb Packet_Size[31:16] W RESET 0 0 16 0 17 0 18 0 19 0 20 0 21 R 0 22 0 23 0 24 25 26 27 28 29 Packet_Size[15:2] PacketSize[1:0] W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0:31 Packet_Size User writes the number of bytes for transmit controller to send over PCI.
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Registers 16 17 R 18 19 20 21 Reserved 22 23 24 Max_Beats 25 26 Reserved 27 28 W 29 30 Reserved 31 lsb DI W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0:3 Reserved Unused. Software should write zero to these bits. 4:7 PCI_cmd The user writes this field with the desired PCI command to present during the address phase of each PCI transaction. The default is Memory Write.
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Registers 10.3.3.1.4 R Tx Enables PCITER(RW)—MBAR + 0x380C msb 0 1 2 3 4 5 6 RC RF Rsvd CM BE 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 Reserved 7 8 ME 9 10 11 12 13 14 15 FEE SE RE TAE IAE NE 0 0 0 0 0 0 0 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Reserved W RESET R Reserved W RESET 0 0 0 0 0 0 0 0 0 Bits Name Description 0 Reset Controller (RC) User writes this bit high to put Transmit Controller in a reset state.
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Registers Bits Name Description 12 Retry abort Enable (RE) User writes this bit high to enable CPU Interrupt generation in the case of retry abort termination of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel DMA is controlling operation, but in such a case software should poll the status bits to prevent a possible lock-up condition.
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Registers 10.3.3.1.
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Registers 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Packets_Done W RESET 0 0 0 Bits Name 0:31 Packets_Done 0 0 0 0 0 0 Description This status register indicates the number of packets transmitted and is active only if continuous mode is in effect.
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Registers Bits Name Description 10 Bus Error type 1 (BE1) This flag is set whenever a Slave bus transaction attempts to read a Reserved register (an entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus error Enable bit (BE). If software is polling this Byte and wishes to disregard this error it must mask this bit out. 11 FIFO Error (FE) This flag is set whenever the Transmit FIFO asserts its FIFO Error output.
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Registers Bits Name Description 0:31 FIFO_Data_Word This is the data port to the FIFO. Reading from this location will “pop” data from the FIFO, writing data will “push” data into the FIFO. During normal operation the Multi-Channel DMA controller will be pushing data here. The PCI controller will pop data for transmission from a dedicated peripheral port, so the user program should not be reading here. At reset any uninitialized random 32 bit value is read at this address.
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Registers 10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848 5 Reserved 6 7 GR W RESET 0 0 0 0 0 16 17 18 19 20 1 21 8 9 10 11 12 13 14 15 Reserved OF_MASK 4 UF_MASK 3 RXW_MASK R 2 FAE_MASK 1 IP_MASK msb 0 0 0 0 0 1 0 0 0 0 0 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET 0 0 0 0 0 0 0 0 0 Bits Name Description 0:4 Reserved Unused. Software shall write zero to these bits.
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Registers 16 R 17 18 19 20 Reserved 21 22 23 24 25 26 27 Alarm 28 29 30 31 lsb 0 0 0 Alarm W RESET 0 0 Bits Name 0:19 Reserved 20:31 Alarm 0 0 0 0 0 0 0 0 0 0 0 Description Unused. Software should write zero to these bits. User writes these bits to set low level “watermark”, which is the point where FIFO asserts request for Multi-Channel DMA controller data filling. Value is in Bytes.
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Registers 10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 R Reserved ReadPtr W RESET 0 0 Bits Name 0:19 Reserved 20:31 ReadPtr 0 0 0 0 0 0 0 0 0 Description Unused. Software should write zero to these bits.
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Registers 10.3.3.2.1 Rx Packet Size PCIRPSR(RW) —MBAR + 0x3880 msb 0 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 Packet_Size[31:16] W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Packet_Size[15:2] Packet_Siz[1:0] W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0:31 Packet_Size The user writes this register with the number of bytes for Receive Controller to fetch over PCI.
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Registers 16 R 17 18 Reserved 19 20 FB R 0 0 21 22 23 24 Max_Beats 25 26 Reserved 27 28 W 29 30 Reserved 31 lsb DI W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0:3 Reserved Unused. Software should write zero to these bits. 4:7 PCI_cmd The user writes this field with the desired PCI command to present during the address phase of each PCI transaction. The default is Memory Read Multiple.
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Registers 10.3.3.2.4 Rx Enables PCIRER (RW) —MBAR + 0x388C msb 0 1 2 3 4 RC RF FE CM BE 0 0 0 0 0 0 0 0 0 17 18 19 20 21 22 23 24 25 26 0 0 0 0 0 0 0 0 0 R 5 6 Reserved 7 8 ME 9 Reserved 10 11 12 13 14 15 FEE SE RE TAE IAE NE 0 0 0 0 0 0 27 28 29 30 31 lsb 0 0 0 0 0 W RESET 16 R 0 Reserved W RESET 0 0 Bits Name Description 0 Reset Controller (RC) User writes this bit high to put Receive Controller in a reset state.
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Registers Bits Name Description 11 System error Enable (SE) User writes this bit high to enable CPU Interrupt generation in the case of system error termination of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel DMA is controlling operation, but in such a case software should be polling the status bits to prevent a possible lock-up condition.
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Registers 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Last_Word W RESET 0 0 0 0 0 0 0 0 0 Bits Name Description 0:31 Last_Word This status register indicates the last 32-bit data fetched from the FIFO and is designed for the case in which an abnormal PCI termination has corrupted the integrity of the FIFO data (for that word). 10.3.3.2.
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Registers Bits Name Description 0:31 Packets_Done This status register indicates the number of packets received. It is active only if continuous mode is in effect. If the following occurs, the counter is reset: • • Reset Controller bit, PCIRER[RC], is asserted (normal way to restart continuous mode) Master Enable bit, PCIRER[ME], is negated In this way, master enable can be used to reset Packets_Done status without disturbing continuous mode addressing.
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Registers Bits Name Description 12 System Error (SE) This flag is set in response to the Transmit Controller entering an illegal state. A CPU interrupt will be generated if the System error Enable (SE) bit is set. In normal operation this should never occur. The only recovery is to assert the Reset Controller bit, PCIRER[RC], and clear this flag.
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Registers R Reserved W RESET RXW UF OF rwc rwc rwc FR Full Alarm Empty 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET 0 0 0 0 0 0 0 0 0 Bits Name Description 0:8 Reserved 9 Receive Wait Condition (RXW) This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not enough room in the FIFO to accept the data without causing overflow.
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Registers Bits Name Description 0:4 Reserved Unused. Software shall write zero to these bits. (R/W) 5:7 Granularity (GR) Granularity bits control high “watermark” point at which FIFO negates Alarm condition (i.e., request for data). It represents the number of free Bytes times 4. Note: A granularity setting of zero should be avoided because it means the Alarm bit (and the Requestor signal) will not negate until the FIFO is completely full.
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Functional Description 10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) —MBAR + 0x38D0 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 R Reserved ReadPtr W RESET 0 0 Bits Name 0:19 Reserved 20:31 ReadPtr 0 0 0 0 0 0 0 0 0 Description Unused. Software should write zero to these bits.
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Functional Description NOTE Only the internal PCI arbiter of the MPC5200B can be used as PCI arbiter for the PCI bus. An external PCI arbiter cannot be used. The registers, described in Section 10.3, Registers, control and provide information about these multiple interfaces. An additional Configuration interface allows internal access through the Slave bus(also referred to as IP bus) to the PCI Type 0 Configuration registers, which are accessible to both MPC5200B and external masters through the PCI bus.
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Functional Description or more data phases. Data is transferred between initiator and target in each cycle that both IRDY and TRDY are asserted. Wait cycles may be inserted in a data phase by the initiator (by negating IRDY) or by the target (by negating TRDY). Once an initiator has asserted IRDY, it cannot change IRDY or FRAME until the current data phase completes regardless of the state of TRDY.
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Functional Description 1 2 3 4 5 6 7 8 CLK FRAME AD A1 C/BE CMD D2 D1 Byte Enables IRDY TRDY (wait) DEVSEL STOP Address Phase Data Phase 1 Data Phase 2 Figure 10-3. PCI Write Terminated by Target 10.4.1.4 PCI Bus Commands PCI supports a number of different commands. These commands are presented by the initiator on the C/BE[3:0] lines during the address phase of a PCI transaction. Table 10-5.
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Functional Description Table 10-5. PCI Bus Commands (continued) C/BE[3:0] PCI Bus Command MPC5200B supports as Initiator MPC5200B supports as Target 0111 Memory-write Yes Yes The memory write command accesses agents mapped into PCI memory space. 1000 Reserved No No -- 1001 Reserved No No -- 1010 Configuration read Yes Yes The configuration read command accesses the 256 byte configuration space of a PCI agent.
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Functional Description For linear incrementing mode, the memory address is encoded/decoded using AD[31:2]. Thereafter, the address is incremented by 4 bytes after each data phase completes until the transaction is terminated or completed (a 4 byte data width per data phase is implied). Note, the two low-order bits of the address are still included in all the parity calculations. MPC5200B supports both linear incrementing and cache wrap mode as an initiator.
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Functional Description Target configuration doubleword number 31 11 10 87 Function Number Reserved 21 0 DW Number 0 0 Figure 10-4. Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction Address bits [10:8] identify the target function and bits AD[7:2] select one of the 64 configuration dwords within the target function’s configuration space. For Type 0 configuration transactions, the target device’s IDSEL pin must be asserted.
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Functional Description 10.4.2 Initiator Arbitration There are three possible internal initiator sources - CommBus Transmit, CommBus Receive, or the XL bus (from Internal System Arbiter). Custom interface logic arbitrates and provides mux select control for these sources to the PCI controller. Figure 10-6 illustrates the arbitration block connection.
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Functional Description In addition to the configurable address window mapping logic, the register interface provides a Configuration Address Register, which provides the ability to generate Configuration, Interrupt Acknowledge and Special Cycles. External PCI devices should be configured through this interface. Section 10.4.4.2, Configuration Mechanism for configuration, interrupt acknowledge, and special cycle command support.
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Functional Description Table 10-7.
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Functional Description Table 10-7.
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Functional Description Reserved Contents of Configuration Address Register 31 30 E 24 23 0000000 16 15 Bus Number 11 10 Device Number 8 7 2 10 Function Number dword 00 AD[31:0] Signals During Address Phase See Table 10-8 31 11 10 IDSEL (only one signal high) 2 10 Function Number/dword 00 Figure 10-7. Type 0 Configuration Translation For Type 0 configuration cycles, MPC5200B translates the device number field of the Configuration Address Register into a unique IDSEL line shown in Table 10-8.
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Functional Description Table 10-8. Type 0 Configuration Device Number to IDSEL Translation (continued) Device Number IDSEL Binary Decimal 0b1_1101 29 AD29 0b1_1110 30 AD30 0b1_1111 31 - NOTE: Device numbers 0b0_0000 to 0b0_1001 are reserved. Programming to these values and issuing a configuration transaction will result in a PCI configuration cycle with AD31-AD11 driven low. MPC5200B can issue PCI configuration transactions to itself.
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Functional Description During the data phase, AD[31:0] contain the Special Cycle message and an optional data field. The Special Cycle message is encoded on the 16 least significant bits (AD[15:0]) and the optional data field is encoded on the most significant bits (AD[31:16]). The Special Cycle message encodings are assigned by the PCI SIG Steering Committee. The current list of defined encodings are provided in Table 10-9. Table 10-9.
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Functional Description 10.4.5.1 Reads from Local Memory MPC5200B can provide continuous data to a PCI master using two 32-byte buffers. The PCI controller bursts reads internally at each 32-byte PCI address boundary. The data is stored in the first 32-byte buffer until either the PCI master flushes the data or the transaction terminates (FRAME deasserts).
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Functional Description Table 10-12.
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Functional Description The Communication Sub-System Initiator Interface consists of Receive and Transmit FIFOs, integrated as separate Multi-Channel DMA peripherals. Therefore, it is generally controlled by the Multi-Channel DMA controller through a pre-described program loop. As with all Communication Sub-System peripherals, it can be accessed and controlled directly through the Slave bus interface if desired, but this path does not generally lend itself to high throughput.
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Functional Description 2. 3. 4. 5. 6. 7. 8. Set the PCI command, Max_Retries, and Max_Beats Set mode, Continuous or Non-continuous Reset the FIFO Set the FIFO Alarm and Granularity fields Set the Master Enable bit (eventually enable the wanted interrupt in case of errors or even of a normal termination) Set the Reset Controller bit low Setup the BestComm (eventually passing the parameters to the task if needed, enabling, if required, the Task to interrupt the Core when finished, etc.) 9. Start the Task(s).
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PCI Arbiter 10.4.6.8 Alarms The FIFO alarm registers allow software to control when the DMA fills or empties the appropriate FIFO. 10.4.6.9 Bus Errors Since Bus Errors are particular to the module register set and that register set includes both Transmit and Receive Controller and FIFO settings, the Bus Error status bits and Bus error Enable bit(s) are duplicated in the Transmit and Receive register groupings. Clearing or setting one will clear or set the other.
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Application Information The PCI Arbiter implements a Round-Robin fairness algorithm, which avoids the domination of the bus by high-priority masters and exclusion of low-priority masters. The PCI Arbiter is capable of Parking the current Master to stay on last master in absence of other requests. The support of the non-PCI clients presents special challenges to the arbitration scheme. The PCI Arbiter runs independently.
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Application Information Table 10-15. Transaction Mapping: XL Bus -> PCI (continued) Initiator Register Settings XL bus Transaction (XL Bus Slave Interface) Single-Beat 1 -> 4 byte Write Cache Line Size Register= 8 Initiator Window Configuration bits x Configuration Address Register IO/M# PRC En device number == b1_1111 1 x 1 true PCI Transaction Controller (XL Bus Initiator Interface) -> PCI Target Special Cycle Note: 1.
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Application Information MPC5200B PCI Space (Memory View) 0 Inbound Translation base address 0 0 TBATR0 Address Translation Register Space 1G System Memory 1G MPC5200B BAR1 Not Recommended Initiator Window(s) MPC5200B memory PCI Space TBATR1 Address Translation Inbound Translation 2G base address 1 2G MPC5200B memory MPC5200B BAR0 Sdram Space 3G 3G 4G 4G Figure 10-8. Inbound Address Map 10.6.2.1.
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Application Information 0 PCI Space (Memory View) MPC5200B Space 0 PCI Space (IO View) PCI Space (Configuration View) 0 0 1G 1G Window 0 MBAR Register Space Window 0 Translation 1G 1G Window 0 Not Recommended XL Bus Initiator Windows MPC5200 B mem- Window 1 Translation Window 1 2G Window 1 2G 2G 2G 3G 3G 4G 4G MPC5200B mem- Window 2 Not Recommended Window 2 Translation 3G 3G Window 2 4G 4G Associated with PCI Prefetchable Memory Window 0 Base Address = 0x40 Window 0 Address
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Application Information 10.6.3 XL bus Arbitration Priority When the XL Bus Arbiter Master Priority Register (Section 16.2.11, Arbiter Master Priority Register (R/W)—MBAR + 0x1F68) is set to any configuration except all-master fair-share (all masters have the same priority), live lock can occur on the shared PCI bus and the XL Bus, which results in system-wide live lock.
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Application Information MPC5200B Users Guide, Rev.
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Overview Chapter 11 ATA Controller 11.1 Overview The following sections are contained in this document: • Section 11.2, BestComm Key Features — Section 11.3, ATA Register Interface, includes: — Section 11.3.1, ATA Host Registers—MBAR + 0x3A00 — Section 11.3.2, ATA FIFO Registers—MBAR + 0x3A00 — Section 11.3.3, ATA Drive Registers—MBAR + 0x3A00 • Section 11.4, ATA Host Controller Operation • Section 11.5, Signals and Connections • Section 11.6, ATA Interface Description • Section 11.
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ATA Register Interface 4. As FIFO fills, BestComm is interrupted and moves data from FIFO to an internal destination. 11.2.2 1. 2. 3. 4. BestComm Write microprocessor sets up descriptors in BestComm RAM and initiates a transfer. BestComm hits on an ATA command FIFO space and writes a command (ATA drive register address, transfer size) into FIFO. BestComm reads data from internal source and puts data in FIFO ATA Controller transfers data from FIFO and writes to drive.
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ATA Register Interface Bits Name 6 IE 7 IORDY 16:31 — 11.3.1.2 Description Enables drive interrupt to pass to CPU in PIO modes. Set by software when the drive supports IORDY. Required for PIO mode 3 and above. Reserved ATA Host Status Register—MBAR + 0x3A04 Table 11-2.
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ATA Register Interface Bits Name 0:7 pio_t0 8:15 pio_t2_8 PIO read/write pulse width for 8-bit transfers. Count value is based on system clock operating frequency. 16:23 pio_t2_16 PIO read/write pulse width for 16-bit transfers. Count value is based on system clock operating frequency. 24:31 — 11.3.1.4 Description PIO cycle time count value is based on system clock operating frequency. Reserved ATA PIO Timing 2 Register—MBAR + 0x3A0C Table 11-4.
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ATA Register Interface Bits Name 0:7 dma_t0 Multiword DMA cycle time. Count value is based on system clock operating frequency. 8:15 dma_td Multiword DMA read/write (DIOR/DIOW) asserted pulse width. Count value is based on system clock operating frequency. 16:23 dma_tk Multiword DMA read/write (DIOR/DIOW) negated pulse width. Count value is based on system clock operating frequency. 24:31 dma_tm CS[0], CS[1] valid to DIOR/DIOW. Count value is based on system clock operating frequency. 11.3.1.
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ATA Register Interface Bits Name 0:7 udma_t2cyc Ultra DMA sustained average two cycle time. Count value is based on system clock operating frequency. 8:15 udma_tcyc Ultra DMA strobe edge to strobe edge cycle time. Count value is based on system clock operating frequency. 16:23 udma_tds Ultra DMA read data setup time. Count value is based on system clock operating frequency. 24:31 udma_tdh Ultra DMA read data hold time. Count value is based on system clock operating frequency. 11.3.1.
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ATA Register Interface Bits Name Description 0:7 udma_tmli Limited interlock time with a defined minimum, when drive or host are waiting for response from each other. Count value is based on system clock operating frequency. 8:15 udma_taz Maximum time allowed for output drivers to release from being driven. Count value is based on system clock operating frequency. 16:23 udma_tenv Envelope time from DMACK to STOP and HDMARDY during data-out burst initiation.
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ATA Register Interface 11.3.1.11 ATA Ultra DMA Timing 5 Register—MBAR + 0x3A28 Table 11-11. ATA Ultra DMA Timing 5 Register msb 0 1 2 R 3 4 5 6 7 8 9 10 udma_tzah 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET: 0 0 Bits Name 0:7 udma_tzah 8:31 — 11.3.1.
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ATA Register Interface ATA FIFO is controlled by 32-bit registers. These registers are located at an offset from MBAR of 0x3a00. Register addresses are relative to this offset.
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ATA Register Interface Bits Name 10 UF UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read beyond empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag. 11 OF OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full. Resetting FIFO clears this condition; writing 1 to this bit clears flag. 12 Full FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
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ATA Register Interface 16 17 R 18 19 20 21 22 23 24 25 26 Reserved 27 28 29 30 31 lsb 0 0 0 0 0 Alarm W RESET: 0 0 Bits Name 0:19 — 20:31 Alarm 11.3.2.5 0 0 0 0 0 0 0 0 0 Description Reserved User writes these bits to set low level “watermark”, which is the point where FIFO asserts request for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32, alarm condition occurs when FIFO contains 32Bytes or less.
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ATA Register Interface Bits Name 0:19 — 20:31 WritePtr 11.3.3 Description Reserved Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special cases, but this disrupts data flow integrity. Value represents the Read address presented to the FIFO RAM. ATA Drive Registers—MBAR + 0x3A00 The ATA drive registers are physically located inside the drive controller on the ATA disk drive.
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ATA Register Interface 11.3.3.2 ATA Drive Alternate Status Register—MBAR + 0x3A5C Table 11-20. ATA Drive Alternate Status Register R msb 0 1 2 3 4 BSY DRDY 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 0 0 Reserved 5 DRQ 6 Rsvd 7 8 9 10 ERR 11 12 13 14 15 0 0 0 0 27 28 29 30 31 lsb 0 0 0 0 0 13 14 15 Reserved W RESET: R Reserved W RESET: 0 0 Bits Name 0 BSY 1 DRDY 2:3 — 4 DRQ 5:6 — 7 ERR 8:31 — 11.3.3.
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ATA Register Interface 11.3.3.4 ATA Drive Features Register—MBAR + 0x3A64 Table 11-22. ATA Drive Features Register msb 0 1 2 3 4 5 6 7 8 9 10 R 12 13 14 15 Reserved W RESET: 11 Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET: 0 0 0 0 0 0 0 0 0 Bits Name Description 0:7 Data Register content is command dependent.
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ATA Register Interface 11.3.3.6 ATA Drive Sector Count Register—MBAR + 0x3A68 Table 11-24. ATA Drive Sector Count Register msb 0 1 2 R 3 4 5 6 7 8 9 10 Data 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET: 0 0 0 0 0 0 0 0 0 Bits Name Description 0:7 Data Bit content is command dependent.
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ATA Register Interface 11.3.3.8 ATA Drive Cylinder Low Register—MBAR + 0x3A70 Table 11-26. ATA Drive Cylinder Low Register msb 0 1 2 R 3 4 5 6 7 8 9 10 Data 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R Reserved W RESET: 0 0 0 0 0 0 0 0 0 Bits Name Description 0:7 Data Bit content is command dependent.
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ATA Register Interface 11.3.3.10 ATA Drive Device/Head Register—MBAR + 0x3A78 Table 11-28.
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ATA Register Interface Bits Name Description 0:7 Data 8 — 9 HUT Host UDMA burst Terminate—Software can terminate UDMA burst prematurely by setting this bit. Bits 15 through 10 are unaffected and retain previous values. 10 FR FIFO Reset—Hardware resets FIFO when the direction is switched from Tx to Rx. No hardware reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling it for Tx.
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ATA Register Interface 11.3.3.12 ATA Drive Device Status Register—MBAR + 0x3A7C Table 11-30.
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ATA Host Controller Operation Bits Name Description 12 IE Enables drive interrupt to pass to CPU in DMA/UDMA modes. Software writes to this register as follows: • • FE (bit 11) and IE (bit 12) Clear IE and set FE if SDMA task loop count is the same as the data transfer requested from the drive. The following is a typical sequence if the SDMA task loop is a larger count than data request programmed for the drive: 1. Start transaction with IE set and FE cleared. 2.
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ATA Host Controller Operation udma_t2cyc is another special case. Unlike the name implies, this register does not control 2 UDMA timing cycles. Rather, it controls how long the host continues to accept data after it has de-asserted HDMARDY–. According to the ATA-4 specification—if tSR is met, the host should accept 0–1 more data words, or if tSR is exceeded, 0–2 more data words.
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ATA Host Controller Operation Table 11-31. PIO Timing Requirements (continued) Counter Start from Activity at end Dependencies t93 N/A (Use t4 instead) — — tA t1 Check IORDY IORDY=1 tB N/A (Timing controlled by drive controller) — — tC N/A (Timing controlled by drive controller) — — Note: 1.
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Signals and Connections 11.5 Signals and Connections Table 11-33. MPC5200B External Signals Signal I/O Description DATA[15:0] I/O SA[2:0] O Address—3-bit address, when combined with the two chip-selects, CS1FX and CS3FX, is used to address Control and Command Block Registers in an ATA drive controller (DA2, DA1 and DA0 on ATA cable, respectively). CS[1]FX O Chip select connected to CS[0] on ATA cable. CS[3]FX O Chip select connected to CS[1] on ATA cable.
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ATA Interface Description Cable System Board See Notes MPC5200 ATA Controller Pin1 N/A–GPIO Optional RESET GND 33 Ohms ATA_DATA[15:0] 82 Ohms ATA_DRQ 22 Ohms ATA_IOW 22 Ohms ATA_IOR 82 Ohms ATA_IOCHRDY 22 Ohms ATA_DACK 82 Ohms ATA_INTRQ 22 Ohms ATA_SA[1] DA[0] 22 Ohms ATA_SA[0] DA[2] 22 Ohms ATA_SA[2] CS[0] 22 Ohms ATA_CS[1]FX(CS[4]) CS[1] DASP GND 22 Ohms ATA_CS[3]FX(CS[5]) DD[15:0] GND KEY DMARQ GND DIOW:STOP GND DIOR:HDMARDY:HSTROBE GND IORDY:DDMARDY:DSTROBE CSEL DMACK GN
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ATA Interface Description Table 11-34.
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ATA Bus Background HOST DEVICE CS[0], CS[1] DA[2:0] DD[15:0] DIOR:HDMARDY:HSTROBE Chip Select to select Command Block registers. Address to access drive registers or data ports. 8-, 16-bit data interface. DIOR → Asserted by host to read drive registers or data ports. HDMARDY → Host ready to receive UDMA data in bursts. Negated to pause. HSTROBE → Host signal for UDMA data out bursts. Data latched in drive registers from DD[15:0] on both edges of HSTROBE. Host stops generating HSTROBE edges to pause.
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ATA Bus Background Table 11-35.
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ATA Bus Background 11.7.3.1 ATA Register Addressing The address used to reference an ATA drive register. This is the actual address (CS[1]FX, CS[3]FX, DA[2:0]) present on the physical ATA interface. Table 11-37 gives details. Table 11-37.
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ATA Bus Background Notes 1. 2. LBA mode is only available in ATA-2 or later specifications. A block mode exists (not to be confused with logical block addressing), in which sectors are grouped into a unit, called a block, for purposes of data transfer. The number of sectors is set with SET MULTIPLE MODE command and is used by the READ MULTIPLE and WRITE MULTIPLE commands. When specifying sectors within a block, either CHS or LBA mode may be used. 11.7.3.
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ATA Bus Background 11.7.4 ATA Transactions ATA Transactions are divided into three types: • PIO Mode • Multiword DMA • Ultra DMA 11.7.4.1 PIO Mode Transactions PIO mode transactions are the simplest transaction available on the ATA interface. They essentially consist of single word accesses across the ATA interface. There are currently 6 PIO modes available, which are summarized in Table 11-36. Timing and sequence information are given in the MPC5200B datasheet.
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ATA Bus Background Host Set Up Register Block Send Command Read Status Read Sector Buffer Read Sector Drive Read Status Read Sector Buffer Read Sector DRDY BSY DRQ INTRQ Figure 11-5. Timing Diagram—PIO Read Command (Class 1) 11.7.4.1.2 Class 2—PIO Write The PIO single sector write command [format, write buffer, write sector(s)] is as follows: 1. HOST: Write to ATA control/command block registers to setup for data write. 2. HOST: Write to ATA command register to execute write command. 3.
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ATA Bus Background Host Set Up Register Block Send Command Write Sector Buffer Write Sector Buffer Read Status Write Sector Drive Read Status Write Sector DRDY BSY DRQ INTRQ Figure 11-6. Timing Diagram—PIO Write Command (Class 2) 11.7.4.1.3 Class 3—Non-Data Command The Non-Data Command is as follows: 1. HOST: Write to ATA control/command block registers to setup for data read. 2. HOST: Write to ATA command register to execute read command. 3. DRIVE: Execute command.
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ATA Bus Background 3. Write command code 0xEF to command register to execute SET FEATURES command. This sets the data transfer protocol to multiword DMA with desired mode. Data transfers into DMA differ from a PIO transfer in that: • Data is transferred using the DMA channel. • A single interrupt is issued at command completion. The Host initializes the DMA channel prior to issuing DMA mode commands. The drive asserts an interrupt when data transfer is complete. The DMA command protocol is as follows: 1.
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ATA Bus Background START Drive: Assert DMARQ when ready to transfer data Host: Read Status or Alternate Status register Host: BSY = 0 & DRQ = 0 Host: Assert DMACK when ready to transfer data No Yes Drive: Transfer Done Host: Write Device/Head register to select drive No Yes Host: Read Status or Alternate Status register No Drive: Error Yes Host: BSY = 0 & DRQ = 0 No Drive: Set error status Yes Drive: Clear BSY = 0 and DRQ = 0 Write Control/Command block registers to setup data transfer No D
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ATA Bus Background 11.7.4.3 Multiword DMA Transactions Multiword DMA transactions differ from PIO mode transactions in three ways: 1. Data transfers are done using a drive DMA and a host DMA (optional). 2. Handshaking is done with DMARQ and DMACK, no address is necessary. 3. Interrupts do not occur after every sector for multi-sector transfers 11.7.4.3.1 Class 4—DMA Command Figure 11-9 shows the DMA timing diagram. The DMA command (Read DMA, Write DMA) is as follows: 1.
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ATA RESET/Power-Up NOTE Ultra DMA mode 2 (UDMA2) requires that the ip bus clock speed is at least 66MHz. Table 11-39 lists the redefined ultra DMA protocol signal lines. These lines provide new functions during the ultra DMA mode. At termination of an ultra DMA burst, the host negates DMACK and the lines revert to the definitions used for non-ultra DMA transfers. Table 11-39.
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ATA I/O Cable Specifications tM RESET Can set BSY=0 if Drive 1 not present tN BSY Drive 0 tP tR Drive 0 Can assert DASP to indicate active if Drive 1 not present DASP Control Registers tN BSY tQ Drive 1 tP PDIAG tS tR Drive 1 DASP Figure 11-10. Timing Diagram—Reset Timing Table 11-40.
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ATA Controller Notes MPC5200B Users Guide, Rev.
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Overview Chapter 12 Universal Serial Bus (USB) 12.1 Overview The following sections are contained in this document: • Section 12.2, Data Transfer Types • Section 12.4, Host Control (HC) Operational Registers, includes: — Section 12.4.2, Control and Status Partition—MBAR + 0x1000 — Section 12.4.3, Memory Pointer Partition—MBAR + 0x1018 — Section 12.4.4, Frame Counter Partition—MBAR + 0x1034 — Section 12.4.
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Host Controller Interface • Bulk Transfers—Non-periodic data transfers used to communicate large amounts of information between client software and the USB device. In OpenHCI the data transfer types are classified into two categories: periodic and nonperiodic. Periodic transfers are interrupt and isochronous since they are scheduled to run at periodic intervals. Non-periodic transfers are control and bulk since they are not scheduled to run at any specific time, but rather on a time-available basis. 12.
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Host Controller Interface The HCCA includes the “virtual” registers HccaFrameNumber and HccaPad1. The offsets shall be 0x80 (for HccaFrameNumber) and 0x82 (for HccaPad1). In the USB module of the MPC5200B these two “virtual” registers are swapped. The HccaFrameNumber is a copy of the Frame Number field at the USB HC Timing Reference Register. 12.3.2 Data Structures The basic building blocks for communication across the interface are the endpoint descriptor (ED) and transfer descriptor (TD).
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Host Controller Interface Interrupt Headpointers 0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 Interrupt Endpoint Descriptor Placeholder 32 16 8 4 2 1 Endpoint Poll Interval (ms) Figure 12-4. Interrupt ED Structure Figure 12-5 shows a sample interrupt endpoint schedule.
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Host Control (HC) Operational Registers Interrupt Headpointers 0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 Interrupt Endpoint Descriptor 32 16 8 4 2 1 Endpoint Poll Interval (ms) Figure 12-5. Sample Interrupt Endpoint Schedule 12.4 Host Control (HC) Operational Registers Host Control contains a set of on-chip operational registers which are mapped into a non-cacheable portion of the system addressable space. These registers are used by the HCD.
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Host Control (HC) Operational Registers 12.4.2 Control and Status Partition—MBAR + 0x1000 This HC partition uses 6 32-bit registers. These registers are located at an offset from MBAR of 0x1000. Register addresses are relative to this offset.
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Host Control (HC) Operational Registers Bits Name 0:20 — 21 RWE Description Reserved RemoteWakeUpEnable—HCD uses bit to enable or disable the remote WakeUp feature on detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote WakeUp is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. 22 RWC RemoteWakeUpConnected—bit indicates whether HC supports remote WakeUp signaling.
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Host Control (HC) Operational Registers Bits Name Description 29 PLE PeriodicListEnable—setting bit enables periodic list processing in next Frame. If cleared by HCD, periodic list processing does not occur after the next SOF. HC checks this bit prior to starting list processing. 30:31 CBSR ControlBulkServiceRatio—field specifies the service ratio between Control and Bulk EDs.
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Host Control (HC) Operational Registers Bits Name Description 29 BLF BulkListFilled—bit indicates whether there are Bulk List TDs. HCD sets this bit when it adds a TD to a Bulk List ED. When HC begins processing the Bulk List head, it checks BF. • • • • 30 CLF ControlListFilled—bit indicates whether there are Control List TDs. HCD sets this bit when it adds a TD to a Control List ED. When HC begins processing the Control List head, it checks CLF.
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Host Control (HC) Operational Registers Bits Name 25 RHSC 26 FNO FrameNumberOverflow—bit is set when HcFmNumber msb (bit 15) changes value (from 0 to 1, or from 1 to 0) and after HccaFrameNumber is updated. 27 UE UnrecoverableError—bit is set when HC detects a system error not related to USB. HC should not proceed with processing or signaling prior to the system error being corrected. HCD clears this bit after HC is reset.
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Host Control (HC) Operational Registers Bits Name 0 MIE Description Master Interrupt Enable—used by HCD. 0 - writing to this bit is ignored by HC. 1 - writing to this bit enables interrupt generation, due to events specified in other bits of this register. 1 OC OwnershipChange 0 - writing to this bit is ignored by HC. 1 - writing to this bit enables interrupt generation, due to ownership.
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Host Control (HC) Operational Registers 16 17 18 19 R 20 21 22 23 24 Reserved 25 26 27 28 29 30 31 lsb RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 W RESET: 0 0 Bits Name 0 MIE 0 0 0 0 0 0 0 Description Master Interrupt Enable—bit is set after a hardware or software reset. 0 written to this bit is ignored by HC. 1 written to this bit disables interrupt generation, due to events specified in other bits of this register.
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Host Control (HC) Operational Registers • • USB HC Bulk Current Endpint Descriptor Register (0x102C) USB HC Done Head Register (0x1030) 12.4.3.1 USB HC HCCA Register—MBAR + 0x1018 The HC HCCA register contains the physical address of the Host Controller Communication Area. HCD determines alignment restrictions by writing all 1s to HcHCCA and reading the HcHCCA content. Alignment is evaluated by examining the number of 0s in the lower order bits. Minimum alignment is 256Bytes.
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Host Control (HC) Operational Registers 12.4.3.3 USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020 The HC Control Head Endpoint Descriptor register contains the physical address of the first endpoint descriptor of the Control list. Table 12-9.
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Host Control (HC) Operational Registers Table 12-11. USB HC Bulk Head Endpoint Descriptor Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 BHED W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R BHED Reserved W RESET: 0 0 Bits Name 0:27 BHED 28:31 — 12.4.3.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description BulkHeadED—HC traverses the Bulk List starting with the HcBulkHeadED pointer.
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Host Control (HC) Operational Registers Table 12-13. USB HC Done Head Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 DH W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R DH Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0:27 DH DoneHead—When a TD is complete, HC writes the HcDoneHead content to the TD NextTD field.
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Host Control (HC) Operational Registers Bits Name 0 FIT 1:15 FSMPS 16:17 — Reserved 18:31 FI FrameInterval—specifies the bit-time interval between two consecutive SOFs. Nominally, this value is set to 11,999. HCD should store the field’s current value before resetting HC. Setting the HcCommandStatus HostControllerReset field causes the HC to reset this field to its nominal value. HCD may choose to restore the stored value when the reset sequence completes. 12.4.4.
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Host Control (HC) Operational Registers 16 17 18 19 20 21 22 23 R 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 FN W RESET: 0 0 Bits Name 16:31 FN 0 0 0 0 0 0 0 Description FrameNumber—is incremented when HcFmRemaining is re-loaded. FN rolls over to 0 after ffff. When entering the USBOPERATIONAL state, this is automatically incremented.
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Host Control (HC) Operational Registers 16 17 R 18 19 20 21 22 23 24 25 Reserved 26 27 28 29 30 31 lsb 1 0 0 0 0 LST W RESET: 0 0 Bits Name 0:19 — 20:31 LST 12.4.5 0 0 1 1 0 0 0 1 0 Description Reserved LSThreshold—field contains a value which is compared to the FrameRemaining field prior to initiating a low speed transaction. The transaction is started only if FrameRemaining is greater than or equal to this field.
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Host Control (HC) Operational Registers 16 R 17 18 Reserved 0 20 NOC OCP P M W RESET: 19 0 0 1 0 21 22 23 DT NPS PSM 0 1 0 24 25 26 27 28 29 30 31 lsb 0 1 0 NDP 0 0 0 0 0 Bits Name Description 0:7 POTPGT PowerOnToPowerGoodTime—specifies the duration HCD must wait before accessing a Root Hub powered-on port. POTPGT is implementation-specific. The time unit is 2ms. Duration is calculated as POTPGT x 2ms.
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Host Control (HC) Operational Registers Table 12-20. USB HC Rh Descriptor B Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 PPCM W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R DR W RESET: 0 0 Bits Name 0:15 PPCM 0 0 0 0 0 0 0 Description PortPowerControlMask—each bit indicates whether a port is affected by a global power control command when PSM is set.
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Host Control (HC) Operational Registers Bits Name 0 CRWE Description ClearRemoteWakeUpEnable (write) • • 1:13 — 14 OCIC Reserved OverCurrentIndicatorChange—is set by hardware when a change occurs to the OCI field of this register. • • 15 LPSC Writing 1 clears DRWE. Writing 0 has no effect. Writing 1 causes HCD to clear this bit. Writing 0 has no effect. LocalPowerStatusChange (read)—Root Hub does not support the local power status feature. Thus, this bit is always read as 0.
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Host Control (HC) Operational Registers Table 12-22.
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Host Control (HC) Operational Registers Bits Name 15 CSC Description ConnectStatusChange—bit is set whenever a connect or disconnect event occurs. • Writing 1 causes HC to clear this bit. • Writing 0 has no effect. If CCS is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected.
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Host Control (HC) Operational Registers Bits Name Description 28 POCI PortOverCurrentIndicator (read)—bit is only valid when root hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 = No overcurrent condition.
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Host Control (HC) Operational Registers Bits Name 30 PES Description PortEnableStatus (read)—indicates whether the port is enabled or disabled. The Root Hub may clear this bit when the following conditions are detected: • an overcurrent condition • disconnect event • switched-off power • operational bus error (such as babble) This change causes PESC to be set. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. PES cannot be set when CurrentConnectStatus is cleared.
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Host Control (HC) Operational Registers Bits Name 0:10 — 11 PRSC Description Reserved PortResetStatusChange—bit is set at the end of the 10ms port reset signal. • • Writing 1 clears this bit. Writing 0 has no effect. 0 = Port reset not complete 1 = Port reset complete 12 OCIC PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. • • Writing 1 clears this bit.
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Host Control (HC) Operational Registers Bits Name 23 PPS Description PortPowerStatus (read)—bit reflects the port power status, regardless of the type of power switching implemented. If an overcurrent condition is detected, this bit is cleared. HCD sets this bit by writing SetPortPower or SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP].
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Host Control (HC) Operational Registers Bits Name Description 29 PSS PortSuspendStatus (read)—bit indicates port is suspended or in resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CCS. This bit is cleared when: • PortResetStatusChange is set at the end of the port reset, or • when HC is placed in the USBRESUME state. If an upstream resume is in progress, it should propagate to the HC.
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Universal Serial Bus (USB) Notes MPC5200B Users Guide, Rev.
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Overview Chapter 13 BestComm 13.1 Overview The following sections are contained in this document: • Section 13.2, BestComm Functional Description • Section 13.15, BestComm DMA Registers—MBAR+0x1200 • Section 13.16, On-Chip SRAM BestComm provides an efficient, integrated approach to gathering and manipulating data sets from a broad range of communication interfaces. The DMA controller reduces the workload on the microprocessor, allowing it to continue execution of system software.
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Features summary NOTE It is possible for the BESTComm DMA to produce misaligned word addresses on its Slave and Comm bus. These accesses occur due to incorrect program code executed by the BestComm unit. Any misaligned access will be incorrectly processed on the internal SRAM bus and the Comm bus. The work around is to avoid using misaligned accesses. That is, BestComm program code must be written such that misaligned word accesses will not occur. BestComm DMA performs general purpose DMA transfers.
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Task Table (Entry Table) Each task has an entry (8 long words) that contains information about the microcode’s location (start address and stop address) in memory as well as pointers to the variable table to be used in the task, the Function Descriptor Table for the logic functions used within the task, the Context Save area used during task switch/swap and some specific flags to enable performance affecting modes such as speculative reads, prefetch enable, readline and combined write.
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BestComm XLB Address Snooping 13.14 BestComm XLB Address Snooping BestComm prefetches data from the XLB into 4 32-Byte wide Read Line Buffers. A buffer will be invalidated, if the BestComm XLB Address Snooping (BSDIS) is enabled, see XLB Arbiter Configuration Register, and a write operation on the XLB to the prefetched data address happens. No invalidation of the buffer will happen if the BSDIS bit is set. BestComm will still use the old prefetched data. 13.
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BestComm DMA Registers—MBAR+0x1200 13.15.2 SDMA Current Pointer Register—MBAR + 0x1204 Table 13-2. SDMA Current Pointer Register msb 0 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 CurrentPointer W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R CurrentPointer W RESET: 0 0 Bit Name 0:31 currentPointer 13.15.
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BestComm DMA Registers—MBAR+0x1200 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 VariablePointer W RESET: 0 0 0 Bit Name 0:31 variablePointer 13.15.5 0 0 0 0 0 0 Description VariablePointer contains the starting address of the variable table for the currently executing task. SDMA Interrupt Vector, PTD Control Register—MBAR + 0x1210 Table 13-5.
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BestComm DMA Registers—MBAR+0x1200 Bit Name Description 0:7 IntVect1 The Interrupt Vector register is used during interrupt acknowledge read cycles. The high order four bits are programmed by the user, and the low order four bits are decoded from either the current task number or execution unit. If any task interrupts are asserted, Interrupt Vector 1 is driven during the interrupt acknowledge cycle.
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BestComm DMA Registers—MBAR+0x1200 Bit Name 0 DBG 1:2 — 3 TEA Description Debug Reserved A TEA has been received by the currently running task. The corresponding task number is written in the Error Task Number field 4:7 Etn[3:0] Error Task Number: when a TEA is received by the currently executing task its corresponding number is indicated here . If the TEA bit of the PtdControl register is set then the task will not be halted.
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BestComm DMA Registers—MBAR+0x1200 13.15.8 SDMA Task Control 0 Register—MBAR + 0x121C SDMA Task Control 1 Register—MBAR + 0x121E Table 13-8.
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BestComm DMA Registers—MBAR+0x1200 Bit Name 9 High En Description High-Enable - High Priority Task Enable 0 = Normal task enable control 1 = High priority task enable control This bit can be set or cleared by the programmer at any time. This bit enables the SDMA to give priority to the enabled task function over running a task. At system reset, this bit is cleared.
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BestComm DMA Registers—MBAR+0x1200 13.15.10 SDMA Task Control 4 Register—MBAR + 0x1224 SDMA Task Control 5 Register—MBAR + 0x1226 Table 13-10.
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BestComm DMA Registers—MBAR+0x1200 13.15.12 SDMA Task Control 8 Register—MBAR + 0x122C SDMA Task Control 9 Register—MBAR + 0x122E Table 13-12.
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BestComm DMA Registers—MBAR+0x1200 13.15.14 SDMA Task Control C Register—MBAR + 0x1234 SDMA Task Control D Register—MBAR + 0x1236 Table 13-14.
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BestComm DMA Registers—MBAR+0x1200 13.15.16 SDMA Initiator Priority 0 Register—MBAR + 0x123C SDMA Initiator Priority 1 Register—MBAR + 0x123D SDMA Initiator Priority 2 Register—MBAR + 0x123E SDMA Initiator Priority 3 Register—MBAR + 0x123F Table 13-16.
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BestComm DMA Registers—MBAR+0x1200 13.15.17 SDMA Initiator Priority 4 Register—MBAR + 0x1240 SDMA Initiator Priority 5 Register—MBAR + 0x1241 SDMA Initiator Priority 6 Register—MBAR + 0x1242 SDMA Initiator Priority 7 Register—MBAR + 0x1243 Table 13-17.
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BestComm DMA Registers—MBAR+0x1200 16 17 18 R 19 20 21 22 23 24 25 26 27 IPR10 28 29 30 31 lsb 0 0 0 13 14 15 IPR11 W RESET: 0 0 Bit Name 0:7 IPR8 0 0 0 0 0 0 0 0 0 0 0 Description Initiator Priority register for initiator 8 (or Task8 if PtdControl[16]=1) Same bit layout as IPR0 8:15 IPR9 Initiator Priority register for initiator 9 (or Task9 if PtdControl[16]=1) Same bit layout as IPR0 16:23 IPR10 Initiator Priority register for initiator 10 (or Task10 if Ptd
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BestComm DMA Registers—MBAR+0x1200 Bit Name 16:23 IPR14 Description Initiator Priority register for initiator 14 (or Task14 if PtdControl[16]=1) Same bit layout as IPR0 24:31 IPR15 Initiator Priority register for initiator 15 (or Task15 if PtdControl[16]=1) Same bit layout as IPR0 13.15.20 SDMA Initiator Priority 16 Register—MBAR + 0x124C SDMA Initiator Priority 17 Register—MBAR + 0x124D SDMA Initiator Priority 18 Register—MBAR + 0x124E SDMA Initiator Priority 19 Register—MBAR + 0x124F Table 13-20.
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BestComm DMA Registers—MBAR+0x1200 13.15.21 SDMA Initiator Priority 20 Register—MBAR + 0x1250 SDMA Initiator Priority 21 Register—MBAR + 0x1251 SDMA Initiator Priority 22 Register—MBAR + 0x1252 SDMA Initiator Priority 23 Register—MBAR + 0x1253 Table 13-21.
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BestComm DMA Registers—MBAR+0x1200 16 17 18 R 19 20 21 22 23 24 25 26 27 IPR26 28 29 30 31 lsb 0 0 0 0 12 13 14 15 IPR27 W RESET: 0 0 Bit Name 0:7 IPR24 0 0 0 0 0 0 0 0 0 0 Description Initiator Priority register for initiator 24. Same bit layout as IPR0 8:15 IPR25 Initiator Priority register for initiator 25. Same bit layout as IPR0 16:23 IPR26 Initiator Priority register for initiator 26.
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BestComm DMA Registers—MBAR+0x1200 Bit Name 16:23 IPR30 Description Initiator Priority register for initiator 30. Same bit layout as IPR0 24:31 IPR31 Initiator Priority register for initiator 31. Same bit layout as IPR0 13.15.24 SDMA Requestor MuxControl—MBAR + 0x125C Table 13-24.
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BestComm DMA Registers—MBAR+0x1200 Bit Name 12:13 Req25 Description 00: Requestor IrDA RX (PSC_6) 01: GPIO_PSC1_1 10: GPIO_USB_3 11: Always Requestor 25 14:15 Req24 00: Requestor I2C1_TX 01: GPIO_PSC1_0 10: GPIO_USB_2 11: Always Requestor 24 16:17 Req23 00: Requestor I2C1_RX 01: GPIO_SINT_7 10: GPIO_USB_1 11: Always Requestor 23 18:19 Req22 00: Requestor I2C2_TX 01: GPIO_SINT_6 10: GPIO_USB_0 11: Always Requestor 22 20:21 Req21 00: Requestor I2C2_RX 01: GPIO_SINT_5 10: GPIO_PSC3_5 11: Always
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BestComm DMA Registers—MBAR+0x1200 Table 13-25. FIxed REquestors Table REQUESTORS Peripheral REQ15 (RESERVED) REQ14 PSC1_TX REQ13 PSC1_RX REQ12 PSC2_TX REQ11 PSC2_RX REQ10 PSC3_TX REQ9 PSC3_RX REQ8 PCI TX REQ7 PCI RX REQ6 ATA TX REQ5 ATA RX REQ4 FEC TX REQ3 FEC RX REQ2 (RESERVED) REQ1 (RESERVED) REQ0 ALWAYS 13.15.25 SDMA task Size0—MBAR + 0x1260 SDMA task Size 1—MBAR + 0x1264 Table 13-26.
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BestComm DMA Registers—MBAR+0x1200 Bit Name Description srcSize[1:0] Each of the 16 tasks can be programmed to use the source and destination sizes contained in one of the Task Size Registers. The task size information is used by the SDMA module to determine the source and destination transfer size of the operands. When the size contained the task descriptor is set to 2’b11 then the size field from the Task Size Control register is selected.
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BestComm DMA Registers—MBAR+0x1200 13.15.28 SDMA Reserved Register 2—MBAR + 0x126C Table 13-29. SDMA Reserved Register 2 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 res2 W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 R res2 W RESET: 0 0 Bit Name 0:31 res2 0 0 0 0 0 0 0 Description Reserved 13.15.29 SDMA Debug Module Comparator 1, Value1 Register—MBAR + 0x1270 Table 13-30.
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BestComm DMA Registers—MBAR+0x1200 16 17 18 19 20 21 22 23 R 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 0 0 Value2 W RESET: 0 0 Bit Name 0:31 Value2 0 0 0 0 0 0 0 Description Debug Module Comparator 2 Value. 13.15.31 SDMA Debug Module Control Register—MBAR + 0x1278 Table 13-32.
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BestComm DMA Registers—MBAR+0x1200 Bit 25:28 Name Description EU breakpoints euBreakpoint: These bits indicate that a breakpoint has occurred in one of the four execution units. Each execution unit has one bit dedicated to it. A 1 in any of these bits indicates that the associated execution unit has issued breakpoint. These bits are sticky and must be overwritten to continue. These bits are cleared to zero at reset. See Table 13-35 for the bit encoding.
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BestComm DMA Registers—MBAR+0x1200 Table 13-35. EU Breakpoint encoding Reset EU3 EU2 EU1 EU0 0 0 0 0 It must be noted that even if a breakpoint is issued at a specific address the SDMA engine will halt ONLY at a “data aligned” boundary (for instance, if the task moves 32 bits of data per transaction and a breakpoint is set at address 0x02 then the task will be halted at offset 0x04). 13.15.32 SDMA Debug Module Status Register—MBAR + 0x127C Table 13-36.
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On-Chip SRAM 13.16 On-Chip SRAM MPC5200B contains 16KBytes of on-chip SRAM. This memory is directly accessible by the BestComm DMA unit. It is used primarily as storage for task table and buffer descriptors used by BestComm DMA to move peripheral data to and from SDRAM or other locations. These descriptors must be downloaded to the SRAM at boot. This SRAM resides in the MPC5200B internal register space and is also accessible by the processor core.
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Programming Model 0 1 1 4 5 4 5 1 2 9 0 3 1 Task Descriptor Start Pointer Task Descriptor End Pointer Variable Table Pointer Function Descriptor Base Address R P E P I S C R S I P W L V R Task 0 Reserved Reserved Base Address for Context Save Space Literal Base 0 Reserved Literal Base 1 Reserved ....................
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BestComm Table 13-37. BehaviorNotes of Task Table Control Bits Control Function Precise Increment No Error Code Reset Pack Integer Mode Speculative Reads Combined Write Enable Read Line Buffer Enable 13.17.1.
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Programming Model task’s Variable Table is desired. In addition, if a task does not use the last 16 variables, another Variable Table could start immediately after that task’s increment values, so as to not waste memory. Table 13-38.
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Programming Model MPC5200B Users Guide, Rev.
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Overview Chapter 14 Fast Ethernet Controller (FEC) 14.1 Overview The fast Ethernet controller (FEC) is an Ethernet MAC plus two 1 Kbyte FIFOs that work under the control of the processor and BestComm DMA engine to support 10/100 Mbps Ethernet/802.3 networks. Table 14-1 shows a block diagram. A brief introduction and overview of the major functional blocks aid in understanding and programming the FEC.
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Overview CommBus CLK/CNTL IP bus Interrupt FEC SIF tbus_addr tbus requests tbus_addr Bus Controller CSR tbusd_addr FIFO Controller Tx FIFO (1KByte) Rx FIFO (1KByte) RISC Controller (RISC + microcode) T-bus MIB Counters MII MDO MDEN Transmit Receive MDI I/O Pad MDIO TX_EN TX_CLK TXD[3:0] CRS,COL TX_ER MDC RX_CLK RX_DV RXD[3:0] RX_ER MII/7-wire Data Option Figure 14-1. Block Diagram—FEC 14.1.
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Modes of Operation • Automatic internal flushing of the Rx FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization). Address recognition — Frames with broadcast address may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode • 14.
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I/O Signal Overview Table 14-1.
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I/O Signal Overview Tx_EN . . . . . . . . . . . . . Assertion of this signal indicates valid nibbles are being presented on the MII. This signal is asserted with the first nibble of preamble and is negated prior to the first Tx_CLK following the final nibble of the frame. TxD. . . . . . . . . . . . . . . . TxD[0:3] represent a nibble of data when Tx_EN is asserted and have no meaning when Tx_EN is de-asserted. Table 14-2 summarizes the permissible encoding of TxD. Tx_ER . . . . . . . . . . . . .
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FEC Memory Map and Registers Table 14-4. MMI Format Definitions Name Description Optional—consists of a sequence of 32 continuous logic 1s. Start of frame—indicated by a <01> pattern. Operation code: Read instruction is <10> Write instruction is <01> A 5-bit field that lists up to 32 PHYs be addressed. The first address bit transmitted is the msb of the address. A 5-bit field that lets 32 registers be addressed within each PHY.
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FEC Memory Map and Registers Table 14-6. Module Memory Map Address 14.4.1 Function 000–1FF Control/Status Registers 200–3FF MIB Block Counters, see Table 14-8 400–7FF Reserved Control and Status (CSR) Memory Map Table 14-7.
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FEC Memory Map and Registers Table 14-7.
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FEC Memory Map and Registers Table 14-8.
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FEC Registers—MBAR + 0x3000 Table 14-8. MIB Counters (continued) 14.
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FEC Registers—MBAR + 0x3000 • • • • • • • • • • • • • • • • • • • 14.5.
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FEC Registers—MBAR + 0x3000 Bits Name 0:15 FEC_ID 16:20 — 21 DMA Description Value identifying the FEC Reserved DMA function is included in the FEC 0 = FEC does not include DMA (BestComm is the DMA engine) 22 FIFO FIFO function included in the FEC 1 = FEC does include a FIFO 24:31 14.5.
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FEC Registers—MBAR + 0x3000 R Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 0 HBERR Heartbeat Error— interrupt bit indicates HBC is set in the X_CNTRL register and COL input was not asserted within the heartbeat window following a transmission. 1 BABR Babbling Receive Error—bit indicates frame was received with a length in excess of R_CNTRL.MAX_FL bytes. 2 BABT Babbling Transmit Error—bit indicates transmitted frame length exceeded R_CNTRL.
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FEC Registers—MBAR + 0x3000 14.5.3 FEC Interrupt Enable Register—MBAR + 0x3008 The IMASK register provides control over the interrupt events allowed to generate an interrupt. All implemented bits in this CSR are R/W. This register is cleared by a hardware reset. If corresponding bits in both the IEVENT and IMASK registers are set, the interrupt is signalled to the CPU. The interrupt signal remains asserted until 1 is written to the IEVENT bit (write 1 to clear) or a 0 is written to the IMASK bit.
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FEC Registers—MBAR + 0x3000 The R_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN. Table 14-12.
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FEC Registers—MBAR + 0x3000 Bits Name 0:6 — 7 Reserved X_DES_ACTIVE Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “ready” descriptors remain in the transmit ring. 8:31 14.5.6 Description — Reserved FEC Ethernet Control Register—MBAR + 0x3024 The ECNTRL register is a read/write user register that can enable/disable the FEC. Some fields may be altered by hardware. Table 14-14.
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FEC Registers—MBAR + 0x3000 14.5.7 FEC MII Management Frame Register—MBAR + 0x3040 This MII_DATA register does not reset to a defined value. The MII_DATA register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to the MII registers. Writing to the MII_DATA register causes a management frame to be sourced unless the MII_SPEED register has been programmed to 0.
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FEC Registers—MBAR + 0x3000 user. When the write management frame operation is complete, the MII_DATAIO_COMPL interrupt is generated. At this time the MII_DATA register contents match the original value written.
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FEC Registers—MBAR + 0x3000 Bits Name Description 0:23 — 24 DIS_PREAMBLE 25:30 MII_SPEED Reserved Asserting this bit causes preamble (32 1s) to not be prepended to the MII management frame. The MII standard allows the preamble to be dropped, if not required by the attached PHY device(s). Controls the frequency of the MII management interface clock (MDC) relative to ipb_clk. A 0 value in this field “turns off” the MDC and leaves it in low voltage state.
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FEC Registers—MBAR + 0x3000 Bits Name 0 MIB_DISABLE A read/write control bit. If set, MIB logic halts and MIB counters do not update. 1 MIB_IDLE A read-only status bit. If set, MIB block is not currently updating MIB counters. 2:31 — 14.5.10 Description Reserved FEC Receive Control Register—MBAR + 0x3084 The R_CNTRL register is user programmable. It controls the operational mode of the receive block and should be written only when ETHER_EN = 0 (initialization time). Table 14-19.
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FEC Registers—MBAR + 0x3000 Bits Name 30 DRT Description Disable Receive on Transmit 0 = Rx path operates independently of Tx (use for full-duplex or to monitor Tx activity in half-duplex mode). 1 = Disable frames reception while transmitting (normally used for half-duplex mode). 31 14.5.11 LOOP Internal Loopback—If set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. The system clock is substituted for TX_CLK when LOOP is asserted.
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FEC Registers—MBAR + 0x3000 16 R 17 18 19 20 21 22 23 24 25 26 27 28 29 RESET: 0 0 0 0 0 0 0 0 0 0 0 TFC_PAUSE W RFC_PAUSE Reserved 0 0 30 31 lsb FDEN HBC GTS 0 0 0 Bits Name Description 0:26 — 27 RFC_PAUSE This read-only status bit is asserted when a full-duplex flow control pause frame is received. The transmitter is paused for the duration defined in this pause frame. Bit automatically clears when the pause duration is complete.
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FEC Registers—MBAR + 0x3000 16 17 18 19 20 21 22 23 R 24 25 26 27 28 29 30 31 lsb X X X X X X X PADDR1 W RESET: X X X X X X X X X Note: X: Bit is not reset and must be initialized. Bits Name 0:31 PADDR1 14.5.14 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address used for an exact match, and the Source Address field in PAUSE frames.
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FEC Registers—MBAR + 0x3000 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb X X X X X X X PAUSE_DUR W RESET: X X X X X X X X X Note: X: Bit is not reset and must be initialized. Bits Name 0:15 OPCODE 16:31 PAUSE_DUR 14.5.16 Description Opcode field used in PAUSE frames. Bits are a constant value, hex 0001. Pause Duration field used in PAUSE frames. FEC Descriptor Individual Address 1 Registe—MBAR + 0x3118 The IADDR1 register is written by the user.
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FEC Registers—MBAR + 0x3000 16 17 18 19 20 21 22 23 R 24 25 26 27 28 29 30 31 lsb X X X X X X X IADDR2 W RESET: X X X X X X X X X Note: X: Bit is not reset and must be initialized. Bits Name Description 0:31 IADDR2 The lower 32bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. • Bit 31 contains hash index bit 31. • Bit 0 contains hash index bit 0. 14.5.
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FEC Registers—MBAR + 0x3000 16 17 18 19 20 21 22 23 R 24 25 26 27 28 29 30 31 lsb X X X X X X X GADDR2 W RESET: X X X X X X X X X Note: X: Bit is not reset and must be initialized. Bits Name Description 0:31 GADDR2 The GADDR2 register contains the lower 32bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. • Bit 31 contains hash index bit 31. • Bit 0 contains hash index bit 0. 14.5.
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FIFO Interface Bits Name 0:28 — 28:31 X_WMRK Description Reserved Transmit FIFO Watermark—Frame transmission begins: • If the number of bytes selected by this field are written into the transmit FIFO, or • if an EOF is written to the FIFO, or • if the FIFO is full before the selected number of bytes are written. Options are: 0000 = 64Bytes written to FIFO. 0001 = 128Bytes written to FIFO. 0010 = 192Bytes written to FIFO. 0011 = 256Bytes written to FIFO. 0100 = 320Bytes written to FIFO.
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FEC Tx FIFO Data Register—MBAR + 0x31A4 Table 14-30. FIFO Interface Register Map (continued) Address 14.6.1 byte0 byte1 byte2 byte3 Description 0x1B4 LWF LWF Transmit Last Write Frame Pointer 0x1B8 Alarm Alarm Transmit (High/Low) Alarm Pointer 0x1BC Read Read Transmit FIFO Read Pointer 0x1C0 Write Write Transmit FIFO Write Pointer FEC Rx FIFO Data Register—MBAR + 0x3184 14.
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FEC Tx FIFO Status Register—MBAR + 0x31A8 Bits Name 10 UF Description UF FIFO Underflow – Sticky, Write To Clear This bit signifies the read pointer has surpassed the write pointer. This bit will remain set until this bit of the FIFO status register has been written with a 1. 11 OF OF FIFO Overflow – Sticky, Write To Clear This bit signifies the write pointer has surpassed the read pointer. This bit will remain set until this bit of the FIFO status register has been written with a 1.
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FEC Tx FIFO Status Register—MBAR + 0x31A8 Table 14-32.
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FEC Tx FIFO Status Register—MBAR + 0x31A8 16 17 18 R 19 20 21 22 23 24 25 26 Reserved 27 28 29 30 31 lsb 0 0 0 0 LRFP[9:0] W RESET: 0 0 Bits Name 0:21 — 22:31 LRFP[9:0] 0 0 0 0 0 0 0 0 0 0 Description Reserved LRFP Last Read Frame Pointer. This pointer indicates the start of the last data frame read from the FIFO by the peripheral. 14.8.
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FEC Tx FIFO Status Register—MBAR + 0x31A8 Table 14-35. FEC Rx FIFO Alarm Pointer Register FEC Tx FIFO Alarm Pointer Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 R Reserved Alarm[9:0] W RESET: 0 0 Bits Name 0:21 — 22:31 Alarm[9:0] 0 0 0 0 0 0 0 0 0 0 Description Reserved Alarm Pointer.
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FEC Tx FIFO Status Register—MBAR + 0x31A8 14.8.6 FEC Rx FIFO Write Pointer Register—MBAR + 0x31A0 FEC Tx FIFO Writer Pointer Register—MBAR + 0x31C0 The RFIFO_WRPTR and TFIFO_WRPTR are a FIFO-maintained pointer which point to the next FIFO location to be written. The write pointer can be both read and written. Table 14-37.
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Initialization Sequence Table 1-1. Bits Name 7 RCTL[0] Description 0 = Disable fec_enable as a reset to FIFO controllers. 1 = Enable fec_enable as a reset to FIFO controllers. 8:31 14.8.8 --- Reserved FEC Transmit FSM Register—MBAR + 0x31C8 The transmit finite state machine register (XMIT_FSM) controls operation of appending CRC. Typical use is enabled and CRC is appended. Table 14-39.
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Initialization Sequence 14.9.2 User Initialization (Prior to Asserting ETHER_EN) The user needs to initialize portions of the FEC prior to setting the ETHER_EN bit. The exact values depend on the particular application; the sequence of writing the registers is not important. Ethernet MAC registers requiring initialization are defined in Table 14-41. Table 14-41.
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Initialization Sequence Bits Name Description 0:3 — Reserved 4 L Last in Frame, written by the FEC The buffer is not the last in a frame. The buffer is the last in a frame. 5:7 Reserved 8 BC Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF) 9 MC Will be set if the DA is multicast and not BC 10 LG Rx Frame Length Violation, written by the FEC. A frame length greater than R_CNTRL.MAX_FL was recognized. This bit is valid only if the L-bit is set.
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Initialization Sequence Bits 31-27, 24-0—Reserved Bits Name Description 0:4 — Reserved 5 TC Transmit CRC, written by user 0 = End transmission immediately after the last data byte. 1 = Transmit the CRC sequence after the last data byte. 6 ABC Append Bad CRC, written by user 0 = No affect 1 = Transmit the CRC sequence inverted after the last data bye (regardless of TC value). 7:31 14.9.
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Initialization Sequence In MII mode the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored. After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
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Initialization Sequence Accept/Reject Frame True Broadcast Addr ? False Receive Address Recognition False Receive Frame Set BC bit in RCV BD True AR_HM_B = 0 ? BC_REJ = 1 ? False True Receive Frame Set MC bit in RCV BD if multicast AR_EM_B = 0 ? True False Pause Frame True ? False Reject Frame Flush from FIFO PROM = 1 ? True Receive Frame Set M (Miss) bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast False Reject Frame Flush from FIFO Receive Frame NOTE
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Initialization Sequence Receive Address Recognition Group Individual False True FCE ? False I/G Address ? False Pause Address ? Hash Search Group Table Match ? False ar_em_b = 1 ar_hm_b = 1 Exact Match ? True Hash Search Individual Table ar_em_b = 0 ar_hm_b = 1 ar_em_b = 0 ar_hm_b = 1 True True True Match ? False ar_em_b = 1 ar_hm_b = 0 ar_em_b = 1 ar_hm_b = 0 ar_em_b = 1 ar_hm_b = 1 NOTES: FCE - field in R_CNTRL register (Flow Control Enable) AR_EM_B - bit in RECV.
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Initialization Sequence Table 14-45.
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Initialization Sequence Table 14-45. Destination Address to 6-Bit Hash (continued) 14.9.
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Initialization Sequence Table 14-46. PAUSE Frame Field Specification 48-bit destination address 0180_c200_0001 or Physical ADDRESS 48-bit Source Address any 16-bit type 8808 16-bit opcode 0001 16-bit PAUSE duration 0000 to ffff Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields.
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Initialization Sequence If a collision occurs within 64 byte times the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512 bit times. If a collision occurs after 64 byte times no retransmission is performed and the end of frame buffer is closed with an LC error indication. 14.9.10 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller.
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Initialization Sequence Non-Octet Error (Dribbling Bits) — The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, then the frame nonoctet aligned (NO) error is reported in the Receive Frame Status Word . If there is no CRC error, then no error is reported.
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Fast Ethernet Controller (FEC) Notes MPC5200B Users Guide, Rev.
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Overview Chapter 15 Programmable Serial Controller (PSC) 15.1 Overview The following sections are contained in this document: • Section 15.2, PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 • Section 15.3, PSC Operation Modes • Section 15.
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Overview System Integration Unit (SIU) Interrupt Controller Internal Channel Control Logic Interrupt Control Logic Internal C-/ IP Bus System Serial Communications Channel FIFO System Control lines RxD TxD Programmable Tx/Rx Clock Generation Internal Clock Source External Clock Source PSC 15.1.1 PSC Functions Overview The PSC module of the MPC5200 provide different groups of interfaces to connect the MPC5200 to other devices. Figure 15-1.
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Overview 3. 4. 15.1.2 PSC detect a “codec not ready” status the PSC will stop sending and receiving data. In the enhanced AC97 mode, only the data slots must be in the FIFO. The PSC generate the slot0,1 and slot2 values depend on data to send. In both AC97 modes the PSC reads only 32 bits from the FIFO. For more information about the AC97 mode see Section 15.3.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 • Selectable pulse width: either 3/16 bit duration or 1.6 µs IrDA MIR mode: • Baud rate: 0.576 Mbps to 1.152 Mbps IrDA FIR mode: • Baud rate: 4 Mbps 15.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-2.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-4. Mode Register 1 (0x00) for SIR Mode R msb 0 1 2 RxRTS RxIRQ/FFUL L 0 0 3 4 5 6 7 lsb 0 1 1 5 6 7 lsb 0 1 1 Reserved W RESET: 1 1 0 Table 15-5.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-6. Parity Mode/Parity Type Definitions 01 Force parity 10 No parity 11 Multidrop mode 15.2.2 Low parity High parity n/a Data character Address character Mode Register 2 (0x00) — MR2 MR2 can be read or written when the Mode register pointer points to it, which occurs after any access to MR1. An MR2 access does not update the mode register address. Table 15-7.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit 3 Name Description TxCTS UART / SIR—Transmitter clear-to-send—If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. TxCTS is not used in Codec mode. 0 = CTS has no effect on the transmitter. 1 = Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-12.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 3 ORERR Description Overrun Error Indicates whether an overrun occurs. For purposes of overrun, FIFO full means all FIFO space is occupied; the Rx FIFO threshold is irrelevant to overrun. 0 = No overrun occurred. 1 = One or more characters in Rx data stream were lost. ORERR sets on receipt of a new character when FIFO is full and a character is already in the shift register waiting for an empty FIFO position.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 8 CDE DEOF Description UART—DCD Error 0 = The DCD input is negated while receiving data. 1 = No error MIR / FIR—Detect End of Frame 0 = Rx did not receive an EOF after the last read SR command. 1 = Rx received the EOF in the frame. In this case, the interrupt and request can be asserted even if the Rx FIFO number is less than the threshold and MR1[1]=1.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.4 Clock Select Register (0x04) — CSR The MPC5200B supports only the internal clock as source for the UART / SIR clock generation. For the UART clock generation a prescaler by 32 or 4 is available. For the SIR clock generation only the prescaler by 32 is valid. After reset, the prescaler by 4 for the UART mode and the prescaler by 32 for the SIR mode is selected.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-16. Command Register (0x08) for all Modes msb 0 1 2 3 R Reserved RESET: 0 Value 0 1:3 5 6 7 lsb Reserved W Bit 4 MISC 0 0 0 Command — TC 0 RC 0 0 0 Description Reserved 000 no command — 001 reset mode register pointer 010 reset receiver Immediately disables receiver, clears SR[FFULL,RxRDY], and re-initializes receiver FIFO pointer. No other registers are altered.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Value Command 4:5 00 no action taken 01 transmitter enable Description Causes Tx to stay in current mode. • If Tx is enabled, it remains enabled. • If Tx is disabled, it remains disabled. Enables operation of Tx channels. SR[TxEMP,TxRDY] sets. If Tx is already enabled, this command has no effect. In UART mode, TxRDY and TxEMP bits in SR become asserted.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.6 Rx Buffer Register (0x0C) — RB Data are read from the Rx FIFO by reading from this read-only register. The Rx FIFO size is 512 bytes. To read data from the RX FIFO you can also use the RFDATA register, see Section 15.2.30, Rx FIFO Data (0x60)—RFDATA. Table 15-17.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name Description 0:19 (AC97) or 0:31 (other) RB AC97 (0:19)—Received data—AC97 data must be read one complete sample at a time, where all samples except time slot #0 are 20 bits. Time slot #0 data is in bits 0:15. Bit 20 is 1 in the first sample of a new frame. Bit 20 contains the “Start of Frame Indicator” SOF: 0 = RB[0:19] is not the first sample in the frame. 1 = RB[0:15] is the first sample in a new frame.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-22.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0 SYNC Description Codec—Sync detected. 0 = Has not detected sync. 1 = Detected sync (Frame = 1 in Codec Modes or Sync = 1 in AC97 mode) other Modes—Reserved 1 — Reserved 2 D_DCD Delta DCD. 0 = No change-of-state has occurred since the last time the CPU read the IPCR. A read of the IPCR also clears the IPCR D_DCD bit.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 6 IEC1 Description Interrupt enable control for D_DCD. 0 = D_DCD has no effect on the IPC in the ISR. 1 = When the D_DCD becomes high, IPC bit in the ISR sets (causing an interrupt if mask is set). 7 IEC0 Interrupt enable control for D_CTS. 0 = D_CTS has no effect on the IPC in the ISR. 1 = When the D_CTS becomes high, IPC bit in the ISR sets (causing an interrupt if mask is set).
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 4 TxEMP/ URERR Description UART / SIR—TxEMP This bit is identical to the URERR bit in the SR register. other Modes—Underrun Error This bit is identical to the URERR bit in the SR register. To clear this interrupt use the reset error status command in the CR register. 5 DB UART / SIR—Delta Break Receiver detect an Delta Break state. other Modes—Reserved 6 RxRDY FFULL Rx FIFO over threshold.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-28. Interrupt Mask Register (0x14) for UART / SIR Mode msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 lsb 0 0 0 13 14 15 lsb 0 0 0 0 0 0 Reserved 0 DB TxRDY RESET: Reserved RxRDY FFULL IPC TxEMP W ORERR Reserved 0 Error 0 0 Reserved 0 0 0 Table 15-29.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 8 DEOF Description MIR / FIR Detect End of Frame 0 = DEOF has no effect on the interrupt. 1 = Enable the interrupt for DEOF. other Modes—Reserved 9 Error Error 0 = Error bit in the ISR register has no effect on the interrupt. 1 = Enable the interrupt for Error 10:11 — 12 CMD_SEND Reserved Enhanced AC97 Mode—Command Send ready 0 = CMD_SEND bit in the ISR register has no effect on the interrupt.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.13 Counter Timer Lower Register (0x1C)—CTLR This write-only register hold the lower bytes of the preload value used by the timer to provide a given Baud rate. Reading from this register shows the current value of the Baud rate generation counter. Table 15-31.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-32. Codec Clock Register (0x20)—CCR for Codec Mode R FrameSyncDiv[0:7] BitClkDiv[8:15] W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 msb 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 13 14 15 lsb R Reserved BitClkDiv[0:7] W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15-33.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0:7 FrameSyncDiv Description Codec—Frame Sync Divider FrameSync is generated internally by dividing down the Bit Clock. The FrameSyncDiv defines the number of Bit clock cycles between two active frame edges: FrameSync Length = FrameSyncDiv[0:7] + 1 For more information see also Section 15.3.2.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.15 AC97 Slots Register (0x24)—AC97Slots This write only register defines which slots are expected in a receive AC97 frame and which slots will be send in a AC97 TX frame. If the received frame doesn’t match the expected slots the SR[UNEXP_RX_SLOTS] bit will be set. This register has affect only if the and AC97 mode is selected in the SICR register and if the EnAC97 bit is active. Table 15-35.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name Description 0 AC97 CMD Enhanced AC97 Mode—AC97 Command This bit indicates if the access to the Control Register is a read or write access. It will be paste to the Slot1 bit 19. 0 = write access 1 = read access other Modes—Reserved 1:7 AC97 Control Register Index Enhanced AC97 Mode—AC97 address Register This register contains target control register address. It will be paste to the Slot1 bit 18 to 12.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-38. Interrupt Vector Register (0x30) for all Modes msb 0 1 2 3 R 4 5 6 7 lsb 0 0 0 IVR[0:7] W RESET: 0 0 Bit Name 0:7 IVR 15.2.19 0 0 0 Description Interrupt Vector— Not applicable for MPC5200. Input Port Register (0x34)—IP This read-only IP register shows the current state of the input ports. Table 15-39.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 6 DCD Description Current state of the DCD input. 0 = DCD input is low. 1 = DCD input is high. 7 CTS Current state of the CTS input 0 = Input port CTS is low. 1 = Input port CTS is high. 15.2.20 Output Port 1 Bit Set (0x38)—OP1 This is a write-only register. Output ports are asserted by writing to this register. Table 15-42.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 6 RES Description Assert RES output. 0 = No operation 1 = Negates output port RES, (RES becomes 1). 7 RTS AC97—Reserved other Modes—Assert RTS output. 0 = No operation 1 = Negates output port RTS, (RTS becomes 1). 15.2.22 Serial Interface Control Register (0x40)—SICR This register sets the main operation mode. Table 15-44.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 3 SHDIR Description Codec—Shift Direction. 0 = msb first 1 = lsb first other Modes—Reserved 4:7 SIM[3:0] PSC operation mode. CAUTION: When the operating mode change occurs, all Rx/Tx and error statuses are reset. Rx and Tx are disabled.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 13 Cell2xClk Description Codec —Cell Slave 2x Clock Frequency - takes effect only when bit 12 CellSlave = 1 0 = PSC Mclk frequency = Bit Clock from PSC1 master 1 = PSC Mclk frequency = 2x the Bit Clock from PSC1 master other Modes—Reserved 14 ESAI Codec—Enhanced Serial Audio Interface 0 = PSC doesn’t support the ESAI mode. 1 = PSC support the ESAI mode.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name Description 21 Disable_ EOF UART/SIR —Disable EOF generation 0 = The UART receiver generate an EOF tag if an UART error was detected. For more information’s regarding the UART errors (RB, FE,PE, CDE,) see register SR. 1 = The UART receiver doesn’t generate an EOF tag if an UART error was detected other modes—Reserved 22:23 15.2.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-47. Infrared Control 2 (0x48) for MIR/FIR Modes msb 0 1 R 2 3 4 Reserved 5 6 7 lsb SIPREQ ABORT NXTEOF 0 0 0 5 6 7 lsb 0 0 0 W RESET: 0 0 0 0 0 Table 15-48.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-49. Infrared SIR Divide Register (0x48) for SIR Mode msb 0 1 2 3 R 4 5 6 7 lsb 1 1 0 IRSTIM[0:7] W RESET: 0 0 1 1 0 Table 15-50. Infrared SIR Divide Register (0x48) for other Modes msb 0 1 2 3 R 4 5 6 7 lsb 0 0 0 Reserved W RESET: 0 0 Bit Name 0:7 IRSTIM 0 0 0 Description SIR—Timer counter value for 1.6us pulse In SIR mode, this is used to make 1.6 µs pulse when SPUL in the IRCR1 is high.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0 FREQ Description MIR—0.576 M bps mode. 0 = The Baud rate is 1.152 M bps. 1 = If the Baud rate is 0.576 Mbps, this bit should be set high in order to output 1. For more informations about the SIP pulse see also Figure 15-20. other Modes—Reserved 1:7 M_FDIV MIR—Clock divide ratio in MIR mode. The bit frequency is derived by: f IrdaClk f bit = ------------------------------M_FDIV + 1 This bit frequency should be 0.576 or 1.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0:3 — 4:7 F_FDIV Description Reserved FIR—Clock divide ratio in FIR mode. The bit frequency is derived by: f IrdaClk f bit = -----------------------------F_FDIV + 1 This bit frequency should be 8 MHz. In order to receive the minimum pulse width described in the IrDA spec, (F_FDIV + 1) should be larger than or equal to 4. Table 15-56 shows several frequency selection.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.28 Rx FIFO Number of Data (0x58)—RFNUM Table 15-57. RX FIFO Number of DATA (0x58) msb 0 1 2 R 3 4 5 6 7 8 9 10 Reserved 13 14 15 lsb Reserved 0 0 Bit Name 0:6 — 7:15 COUNT 15.2.29 12 COUNT[0:8] W RESET: 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 12 13 14 15 lsb 0 0 0 Description Reserved Number of data bytes in the Rx FIFO. Tx FIFO Number of Data (0x5C)—TFNUM Table 15-58.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0:3 — 4:7 Frame[3:0] 8 — 9 Error FIFO error. A FIFO error has occurred due to either underflow, overflow, or read or write pointer out of bounds.This bit is cleared by writing a ‘1’ to it. 10 UF Underflow. The read pointer has surpassed the write pointer due to the FIFO having been read when it contained no data. This bit is cleared by writing a ‘1’ to it. 11 OF Overflow.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0:3 — 4:15 ALARM 15.2.34 Description Reserved “Almost full” threshold level. Amount of empty space remaining in the Rx FIFO at which the ALARM bit in the status register goes high/active. See Section 15.4, PSC FIFO System for details. Rx FIFO Read Pointer (0x72)—RFRPTR Table 15-62.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.37 Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR Table 15-65. Rx FIFO Last Write Frame PTR (0x7C) msb 0 1 2 3 4 5 6 7 8 9 Reserved R 10 11 12 13 14 15 lsb 0 0 0 0 0 LFP W RESET: 0 0 Bit Name 0:3 — 4:15 LFP 15.2.38 0 0 0 0 0 0 0 0 0 Description Reserved Last Frame Pointer. Not applicable to PSC FIFOs, since the PSCs do not recognize frame formats in the serial data stream.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name Description 14 ALARM The FIFO is requesting service from either BestComm or CPU. See Section 15.4, PSC FIFO System for a detailed description. 15 EMPTY FIFO Empty. The FIFO is completely empty. 15.2.40 Tx FIFO Control (0x88)—TFCNTL Table 15-67. Tx FIFO Control (0x88) msb 0 R 1 Reserved 2 3 4 5 WFR COMP FRAME 0 0 1 6 7 lsb GR[2:0] W RESET: 0 0 0 0 1 Bit Name 0:1 — 2 WFR Write frame.
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PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Bit Name 0:3 — 4:15 R_PTR 15.2.43 Description Reserved Read pointer.This FIFO-maintained pointer points to the next FIFO location to be read Tx FIFO Write Pointer (0x96)—TFWPTR Table 15-70. Tx FIFO Write Pointer (0x96) msb 0 R 1 2 3 4 5 6 7 8 9 Reserved 10 11 12 13 14 15 lsb 0 0 0 0 0 W_PTR W RESET: 0 0 Bit Name 0:3 — 4:15 W_PTR 15.2.44 0 0 0 0 0 0 0 0 0 Description Reserved Write pointer.
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PSC Operation Modes 15.3 PSC Operation Modes This section describes the different PSC operation modes including the pin muxing, the module configuration, signal definition and some programming examples. All PSC are independent and can be used at the same time in different modes. But not all PSCs support all modes, Table 15-73 shows an overview. Table 15-73.
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PSC Operation Modes PSC DCD Port Control Logic Clock Generation Unit CSR {CTUR:CTLR} IPB Clock IPB Interface Rx FIFO Receiver Tx FIFO Transmitter RTS CTS RxD External Interface Signals CommBus Interface IRQ Controller BestComm Request TxD Figure 1-1PSC UART Block Diagram An internal interrupt request signal (IRQ) is provided to notify the Interrupt Controller of an interrupt condition. The output is the logical NOR of unmasked ISR bits.
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PSC Operation Modes RS-232 Transceiver PSC RTS DI2 CTS DO2 TxD DI1 RxD DO1 Figure 15-2. Signal configuration for a PSC/RS-232 interface 15.3.1.2 UART Clock Generation IPB clock serves as the basic timing reference for the clock source generator logic, which consists of a Clock Generator and a programmable 16-bit divider dedicated to the PSC and a fix prescaler.
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PSC Operation Modes After the stop bits are sent, if no new character is in the Tx holding register, the TxD output remains high (mark condition) and the Tx empty bit, SR[TxEMP], is set. Transmission resumes and TxEMP is cleared when the CPU loads a new character into the PSC Tx buffer (TB). • If the transmitter receives a disable command, it continues until any character in the Tx shift register is completely sent. • If the transmitter is reset through a software command, operation stops immediately.
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PSC Operation Modes TxD C1 C2 C3 C4 C5 C6 C7 C8 C6, C7, and C8 are lost Receiver Enabled SR [RxRDY] SR [FFULL] Internal Module Select Status Data C5 is lost (C1) (C2) (C3) (C4) Reset by command Overrun SR [ORERR ] RTS Status Status Status Data Data Data Manually asserted first time, automatically negated if overrun occurs OP0[RTS] = 1 Automatically deasserted when FIFO reached the alarm level Automatically asserted when ready to receive Figure 15-5.
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PSC Operation Modes Table 15-76. General Configuration Sequence for UART mode Register Value Setting CR 0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
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PSC Operation Modes 15.3.2.1 Block Diagram and Signal Definition for Codec Mode CDM PSC Mclk BitClk fsystem Mclk Divider Clock Generation Unit Mclk MclkDiv[8:0]+1 Frame BitClkDiv[0:15]+1 IPB Interface Rx FIFO Receiver Tx FIFO Transmitter RxD External Interface Signals CommBus Interface IRQ Controller TxD Figure 15-6. PSC Codec Block Diagram NOTE Here is important difference between PSC6 and the other PSCs.
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PSC Operation Modes Table 15-78. PSC Signal Description for Codec Mode Signal Description TxD Transmitter Serial Data Output—Data is shifted out on TxD on the falling or rising edge of the clock source. Transfers can be specified as either lsb or msb first. TxD is held low when Tx is disabled or idle.
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PSC Operation Modes The source for the internal clock generation is the MclkDiv clock divider in CDM module. The CDM provides for each Codec PSC (1, 2, 3 and 6) a separate Mclk and MclkDiv clock divider. For more information about the fsystem clock see also Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228. The PSC provides the clock to the external Codec divided independently whether the PSC configured as a master (provide BitClk and FrameSync) or as a slave (receive the clock signals).
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PSC Operation Modes • Data shift direction SICR[SHDIR], data shifted out LSB first if SICR[SHDIR] = 1 otherwise data shifted out MSB first if SICR[SHDIR] = 0 In the Codec “Soft Modem” mode the PSC send only one data word per frame. BitClk polarity Frame Sync Polarity Frame Sync frame sync width BitCLK DATA RX / TX delay of time slot 1 data bit shift direction data length frame length start of next Frame start of Frame Figure 15-9.
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PSC Operation Modes • • • • • • • • • FrameSync is low true lsb first, transfer starts one cycle after the leading edge of FrameSync set Mclk frequency to 33MHz set Bitclk frequency to 250 KHz FrameSync every 35 BitClk set FrameSync width to 3 BitClk set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO enable TxRDY interrupt Table 15-80.
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PSC Operation Modes Frame CLK DATA first Data word last Data word empty Data until the next frame starts Frame length start of Frame Figure 15-10. ESAI Data Transmission Table 15-80 shows an example how to configure the PSC1 as ESAI master. For the slave mode the bit SICR[GenClk] must be cleared and the configuration of the CCR register can be ignored. In this configuration example the PSC will send 3 data words with 16 bit data in the 52 BitClk frame length.
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PSC Operation Modes 15.3.2.5 Transmitting and Receiving in “Cell Phone” Mode The transmission protocol for the “Cell Phone” mode is the same like in the “Soft Modem” mode. The PSC use the configure and clock generation registers is the same as described in the section before, see Section 15.3.2.3, Transmitting and Receiving in “Soft Modem” Codec Mode. The goal for this mode is, that PSC2, 3 or 6 can generate a BitClk which is synchronous to in the BitClk input on PSC1.
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PSC Operation Modes Table 15-82. 24-Bit Cell Phone Master Mode for PSC1 Register Value Setting CR 0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
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PSC Operation Modes LRCK (Frame) SCLK (CLK) SDATA DTS1 Data width empty data bits until the new data starts (zero) Frame length start of Frame start of Frame Figure 15-12. I2S-Data Transmission Table 15-84 shows an example how to configure the PSC1 as I2S master. For the slave mode the bit SICR[GenClk] must be cleared and the configuration of the CCR register can be ignored.
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PSC Operation Modes 15.3.2.7 Transmitting and Receiving in SPI Mode An other available Codec mode is the SPI mode. The PSC support a full duplex SPI interface. This mode is chosen by setting SICR[SPI] = 1, which must be true in order for the MSTR, CPOL, CPHA and UseEOF bits in the SICR register to take effect. In SPI mode, the SICR[SIM] bits must also be set to select the data width.
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PSC Operation Modes SCK SS MOSI MISO DSCKL TX FIFO EMPTY TX ENABLE DTL NEXT FRAME The PSC starts to generate the SCK if the transmitter is enabled and the Tx FIFO is not empty! Figure 15-13. SPI Parameter Table 15-85 shows an example how to configure the PSC3 as SPI master. • 32bit data • clock is active high, CPOL = 1; • the first SCK edge is issued one half cycle into the data transfer; CPHA = 0 • msb first • Baud Rate 1MBit • DSCLK delay = 0.5 µs • DTL delay = 2.
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PSC Operation Modes Register Value Setting Port_Config 0x00000600 Select the Pin-Muxing for PSC3 Codec mode, see: Chapter 2, Signal Descriptions CR 0x05 Enable Tx and Rx Table 15-86 shows an example how to configure the PSC2 as SPI slave.
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PSC Operation Modes 15.3.3.1 Block Diagram and Signal Definition for AC97 Mode PSC BitClk Clock Generation Unit IPB Interface Rx FIFO Sync Receiver Sdata_in CommBus Interface IRQ Controller Tx FIFO Transmitter Sdata_out Reset Logic External Interface Signals Res Figure 15-14. PSC AC97 Block Diagram Figure 15-14 shows the simplified PSC Block Diagram for AC97 mode. The BitClk is an input from the external Codec.
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PSC Operation Modes AC97 Controller PSC1/PSC2 AC97 Codec FRAME SYNC Sync BIT_CLK BitCLK SDATA_OUT SDATA_OUT SDATA_IN SDATA_IN RES RESET Figure 15-15. PSC - AC97 Interface Figure 15-16 shows the Timing diagram for the AC97 interface. For more AC97 Controller interface information, see the Audio Codec’97 Component Specification.
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PSC Operation Modes Low-power mode can be left through either a warm or cold reset. The CPU does a warm reset by setting SICR[AWR] for at least 1µs. This asserts the FRAME frame sync output in AC97 mode. The CPU does a cold reset in two steps: 1. Writes 0 to whichever GPIO is being used as the active low AC97 reset pin for the minimum time specified in the AC97 specification. 2. Writes 0 to PSC1 or PSC2 SICR[ACRB]. CPU should set this bit after writing 1 to the GPIO used for the AC97 reset pin.
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PSC Operation Modes the slot request for the specified slots was active (slot request bit was zero in the previous frame). If the AC97 Codec set a slot request to one, then the transmitter will send a complete empty frame because the transmitter is not able to send a port of the required slots without changing the order of the data in the FIFO.
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PSC Operation Modes Table 15-90. Signal Description for IrDa Mode Signal Description IRDA_TX Transmitter Serial Data Output—Transfers must be specified as msb first. IRDA_RX Receiver Serial Data Input—Transfers must be specified as msb first. PSC IPB Clock Clock Generation Unit {CTUR:CTLR} IPB Interface Rx FIFO Receiver Tx FIFO Transmitter IRDA_RX External Interface Signals CommBus Interface IRQ Controller BestComm Request IRDA_TX Figure 15-17. PSC SIR Block Diagram 15.3.4.1.
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PSC Operation Modes 15.3.4.1.3 Configuration Sequence Example for SIR Mode The Table 15-91 shows the configuration sequences. This list includes the SIR mode related registers only, not the other configure values like interrupt and FIFO configurations. PSC module registers can be accessed by word or byte operations. Table 15-91. Configuration Sequence Example for SIR Mode Register Value Setting CR 0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
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PSC Operation Modes CDM fsystem PSC Mclk Divider IR_USB_CLK Clock divider Mclk MclkDiv[8:0]+1 0 1 BitClkDiv[0:7]+1 Clock Generation Unit IrdaClk IRMDR[1:7] for MIR mode IRFDR[4:7] for FIR mode SICR[GenClk] IPB Interface IRDA_RX Receiver Rx FIFO CommBus Interface IRQ Controller BestComm Request IRDA_TX Transmitter Tx FIFO External Interface Signals Figure 15-19.
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PSC Operation Modes The STA represents the start of the frame and the STO represents the end of the frame. Both of STA and STO are defined as 01111110 in binary format. Like the UART mode, the MIR mode sends the lsb first.The FCS is a 16 bit CRC defined as CRC ( x ) = x 16 +x 12 5 +x +1 NOTE The MIR module doesn’t support the CRC generation. If the transfer require a CRC Field use the CRC generation from the BestComm module. See also Chapter 13, BestComm. 15.3.4.2.
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Programmable Serial Controller (PSC) Table 15-92. Configuration Notes Sequence Example for MIR Mode 15.3.4.3 Register Value Setting IMR 0xXXXX Port_Config 0x00F00000 CR 0x05 select the desired interrupt Select the Pin-Muxing for IrDA mode, see Chapter 2, Signal Descriptions Enable Tx and Rx PSC in FIR Mode The FIR mode is also a supported IrDA mode. This section will give some more informations about this mode.
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PSC FIFO System NOTE The FIR module doesn’t support the CRC generation. If the transfer require a CRC Field use the CRC generation from the BestComm module. See also Chapter 13, BestComm.
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PSC FIFO System Depending on whether the FIFO is set for Tx or Rx, “Alarm” and “Granularity” are measured differently, either: • valid data bytes (Tx FIFO) • empty bytes (Rx FIFO) For both Tx and Rx FIFOs: • “Alarm” specifies a threshold at which the FIFO generates an interrupt to either: — BestComm — CPU (alternate) • “Granularity” specifies a threshold at which the interrupt goes away. Each PSC provide two control lines to the BestComm system, control the transfer from and to the PSC FIFO.
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PSC FIFO System CommBus or IPB Interface Address: 1FF Granularity Level (value multiply by 4) (example: 0x005) 0 first received Byte Granularity Level (example: 0x004) empty FIFO Space last received Byte last Byte to send empty FIFO Space Alarm Level “almost Empty” (example: 0x010) first Byte to send 0 Alarm Level “almost Full” 1FF (example: 0x008) Transmitter Receiver Tx Line Rx Line Figure 15-22. PSC FIFO System 15.4.1 RX FIFO The RX FIFO space is 512 Byte.
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PSC FIFO System When using BestComm you must specify a non-zero “Granularity” to get FIFO underrun errors. This is due to its internal pipelining. BestComm does not immediately stop accessing the FIFO when the FIFO interrupt goes away. 15.4.2 TX FIFO The TX FIFO space is 512 Byte. For a Tx FIFO, the “Alarm” value specifies a threshold in terms of DATA bytes, not in terms of empty space as with the Rx FIFO. Once the amount of data in the Tx FIFO falls below the “Alarm” level, an interrupt activates.
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PSC FIFO System Rx Disabled RxD Input Disabled TxD Input CPU Tx Figure 15-24. Local Loop-Back Features of this local loop-back mode are: • Transmitter and CPU-to-receiver communications continue normally. • RxD input data is ignored. • TxD data is held marking. • The receiver is clocked by the transmitter clock. • Transmitter must be enabled, but the receiver need not be enabled. 15.4.3.
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PSC FIFO System Master Station A/D TxD ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled SR [TxRDY] internal module select MR1n[PM] = 11 MR1n[PT] = 1 ADD 1 C0 MR1n[PT] = 0 ADD 2 MR1n[PT] = 2 Peripheral Station RxD A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled SR[RxRDY] internal module select MR1n[PM] = 11 MR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 15-26.
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Overview Chapter 16 XLB Arbiter 16.1 Overview This document contains the following section: • Section 16.1, Overview • Section 16.2, XLB Arbiter Registers—MBAR + 0x1F00 16.1.1 Purpose The purpose of the XLB Arbiter is to manage bus requests from the XLB masters (USB, PCI, BestComm, and e300 core), and determine which master should be granted the bus at any one time.
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Overview Multiple masters at level 0 will only be able to perform one tenure before the bus is passed to the next master at level 0 using the LRU algorithm. The priority level of each master may be changed while the arbiter is running. This allows dynamic changes in priority such as an aging scheme. It is possible for the e300 core to control priority by enabling the Master Priority Enable bits for a master.
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XLB Arbiter Registers—MBAR + 0x1F00 16.1.1.4.2 Other Tenure Ending Conditions In addition to the watchdog timers, this function will terminate tenures with or without TEA depending on the following conditions: • AACK the address tenure for eciwx and ecowx transfer types, then TEA the ensuing data tenure. This sets the External Control Word Read/Write Status bit in the Arbiter Status Register. • AACK the address tenure for address only and reserved transfer types.
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XLB Arbiter Registers—MBAR + 0x1F00 Table 16-1. Arbiter Configuration Register msb 0 R 1 2 3 4 5 6 7 PLDIS 8 9 10 11 12 13 14 Rsvd 15 BSDIS W RESET: R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb Rsvd BA DT AT Rsvd 0 0 1 1 0 SE W RESET: USE_ TBEN Rsvd WWF 0 0 0 0 WS 0 SP 0 0 Rsvd 0 0 PM 0 0 Bit Name Description 0 PLDIS Pipeline Disable.
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XLB Arbiter Registers—MBAR + 0x1F00 Bit Name 25:26 PM[1:0] Description Parking Mode. 00 = No parking (default). 01 = Reserved. 10 = Park on most recently used master. 11 = Park on programmed master as specifed by the Select Parked Master bits 21:23 above. 27 — Reserved 28 BA Bus Activity Time-out Enable. If enabled, the arbiter will set the Bus Activity Time-out Status bit (Arbiter Status Register, bit 29) when the Bus Activity Time-out is reached.
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XLB Arbiter Registers—MBAR + 0x1F00 Table 16-3. Arbiter Status Register msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Rsvd W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb SEA MM TTA TTR ECW TTM BA DT AT 0 0 0 0 0 0 0 0 0 R Rsvd W RESET: 0 0 0 0 0 0 0 Bit Name 0:22 — 23 SEA Slave Error Acknowledge. This bit is set when an error is detected by any slave devices during the transfer.
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XLB Arbiter Registers—MBAR + 0x1F00 Table 16-4.
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XLB Arbiter Registers—MBAR + 0x1F00 Bit Name Description 0:31 ADRCAP Address Capture Value. This is the address that is captured when a bus error occurs. This happens after an address time-out, data time-out, or any TEA assertion. 16.2.
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XLB Arbiter Registers—MBAR + 0x1F00 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb 1 1 1 1 1 1 1 ADRTO[16:31] W RESET: 1 1 Bit Name 0:3 — 4:31 ADRTO 16.2.8 1 1 1 1 1 1 1 Description Reserved Address Tenure Time-out. Contains the upper 28 bits of the Address Time-out Counter. Values represent increments of 16. Default value is 0xFFFFFFF.
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XLB Arbiter Registers—MBAR + 0x1F00 16 17 18 19 20 21 22 R 23 24 25 26 27 28 29 30 31 lsb 1 1 1 1 1 1 1 BUSTO[16:31] W RESET: 1 1 Bit Name 0:31 BUSTO 16.2.10 1 1 1 1 1 1 1 Description Bus Activity Time-out. Contains the value of the Bus Activity Time-out Counter. Values represent increments of 1. Default value is 0xFFFFFFFF.
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XLB Arbiter Registers—MBAR + 0x1F00 Table 16-11. Hardware Assignments of Master Priority Master Priority M2 1 BestComm M1 2 USB M0 7 e300 Core 16.2.11 Description Arbiter Master Priority Register (R/W)—MBAR + 0x1F68 The Arbiter Master N Priority Register is used to set the software-programmable priority of each master.
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XLB Arbiter Registers—MBAR + 0x1F00 16.2.12 Arbiter Snoop Window Register (RW)—MBAR + 0x1F70 The Arbiter Snoop Window Register is used by the PCI, BestComm, and USB Host interfaces to the XLB. This register dictates the size of an address range in memory that will allow or prohibit address snooping. Each master interface (MBI) monitors this register and determines if the master’s address transferred to the XLB should be sent with gbl_b signal assertion.
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XLB Arbiter Registers—MBAR + 0x1F00 Bit Name Description 25:26 — 27:31 WINSIZE Reserved Window Size - Defines the size of window. The lower bits of WINBASE are effecttively ignored/masked from snooping address comparison depending on the value set in this field.
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XLB Arbiter Notes MPC5200B Users Guide, Rev.
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Overview Chapter 17 Serial Peripheral Interface (SPI) 17.1 Overview The following sections are contained in this document: • Section 17.2, SPI Signal Description • Section 17.3, SPI Registers—MBAR + 0x0F00 • Section 17.4, Functional Description The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. Figure 17-1 shows the SPI block diagram.
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SPI Signal Description 17.1.2 Modes of Operation The SPI functions in the following three modes: • Run Mode—The normal mode of operation. • Wait Mode—The SPI can be configured to operate in low-power mode. Based on the internal bit state, the SPI can operate normally when the CPU is in wait mode or the SPI clock generation can be turned off and the SPI module enters a power conservation state during wait mode. During wait mode, any master transmission in progress stops.
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SPI Registers—MBAR + 0x0F00 The SS pin is the mode fault input when the SPI is in master mode and the associated data direction bit is clear. When the data direction bit is clear and SSOE = 1, the SS pin is a general-purpose input. SS is always an input when the SPI is in slave mode, regardless of the state of the data direction bit for that pin.
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SPI Registers—MBAR + 0x0F00 Bit Name Description 6 SSOE Slave Select (SS) Output Enable—bit is enabled only in master mode by asserting SSOE and SPIDDR bit 3 as shown in Table 17-3. 7 LSBFE SPI LSB-First Enable—bit does not affect the position of the msb and lsb in the data register. Reads and writes of the data register always have the msb in bit 7. 0 = Data is transferred most significant bit first. 1 = Data is transferred least significant bit first. Table 17-3.
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SPI Registers—MBAR + 0x0F00 Table 17-5. Bidirectional Pin Configurations Pin Mode A Normal SPC0 MSTR MISO1 MOSI2 SCK3 SS4 0 0 Slave Out Slave In SCK in SS In 1 Master In Master Out SCK out SS I/O 0 Slave I/O GP I/O5 SCK in SS In 1 GP I/O Master I/O SCK out SS I/O B C Bidirectional 1 D Note: 1. 2. 3. 4. 5. 17.3.3 Slave output is enabled if SPIDDR bit 0 = 1, SS = 0, and MSTR = 0 (A, C). Master output is enabled if SPIDDR bit 1 = 1 and MSTR = 1 (B, D).
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SPI Registers—MBAR + 0x0F00 Table 17-7. SPI Baud Rate Selection SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPI Module Clock Divisor Baud Rate IPB 33.0 MHz Baud Rate IPB 66.0 MHz Baud Rate IPB 132.0 MHz 0 0 0 0 0 0 2 16.50 MHz 33.00 MHz 66.00 MHz 0 0 0 0 0 1 4 8.250 MHz 16.50 MHz 33.00 MHz 0 0 0 0 1 0 8 4.125 MHz 8.250 MHz 16.50 MHz 0 0 0 0 1 1 16 2.063 MHz 4.125 MHz 8.250 MHz .... 1 1 1 1 0 0 256 128.9 KHz 257.8 KHz 512.6 KHz 1 1 1 1 0 1 512 64.
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SPI Registers—MBAR + 0x0F00 17.3.5 SPI Data Register—MBAR + 0x0F09 Table 17-9. SPI Data Register R msb 0 1 2 3 4 5 6 7 lsb D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 W RESET: Bit Name 0:7 D[0:7] Description The SPI Data register is both an input and output register for SPI data. Attempts to write to this register while data transfers are in progress sets the WCOL flag and disables the attempted write. Review the WCOL bit description in Table 17-8 for more information.
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Functional Description Bit Name 0:7 DDR[0:7] Description In SPI slave mode, SPIDDR bit 3 has no meaning or effect. In SPI master mode, SPIDDR bit 3 determines if SPI port pin 3 is: • an error-detect input to SPI • a general-purpose output • a slave select output line Note: When SPI is Enabled, MISO, MOSI, and SCK are: • inputs if expected to be inputs, regardless of associated data direction bit state. • outputs if expected to be outputs, only if associated data direction bit is set.
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Functional Description The SS pin is normally an input which should remain in the inactive high state. However, in the master mode, if the associated data direction bit (SPIDDR bit 4) is set, then the SS pin is a general-purpose output or the slave select output depending on the state of the SSOE bit. General-purpose output (SSOE = 0) or slave select output (SSOE = 1) is specified by the SSOE bit in SPI control register 1.
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Functional Description MASTER SPI SHIFT REGISTER BAUD RATE GENERATOR SLAVE SPI MISO MISO MOSI MOSI SCK SCK SS VDD SHIFT REGISTER SS Figure 17-2. Master/Slave Transfer Block Diagram 17.4.4.1 Clock Phase and Polarity Controls Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format.
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Functional Description Transfer Begin End SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaran
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Functional Description signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
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Functional Description BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) Figure 17-5. Baud Rate Divisor Equation 17.4.6 Special Features 17.4.6.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device.
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Functional Description 17.4.7 Error Conditions The SPI has two error conditions: • Write collision error • Mode fault error 17.4.7.1 Write Collision Error The WCOL status flag in the SPI status register indicates that a serial transfer was in progress when the MCU tried to write new data into the SPI data register. The following list explains valid write times (reference Table 17-3 and Table 17-4 for definitions of tT and tI).
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Functional Description NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode.
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Functional Description MPC5200B Users Guide, Rev.
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Overview Chapter 18 Inter-Integrated Circuit (I 2 C) 18.1 Overview The following sections are contained in this document: • Section 18.2, I2C Controller • Section 18.3, I2C Interface Registers • Section 18.4, Initialization Sequence • Section 18.5, Transfer Initiation and Interrupt The Inter-Integrated Circuit (I 2 C) is a two-wire, bidirectional serial bus that provides a simple, efficient method for data exchange between devices. This two-wire bus minimizes the interconnection between devices.
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I2C Controller IP Bus Registers Start, Stop & Arbitration Control Clock Control In/Out Data Shift Register CommBus SCL SDA Address Compare Figure 18-1. Block Diagram—I2C Module 18.2 I2C Controller The I2C has simple bidirectional two-wire bus for efficient inter-IC control. The two wires, serial data line (SDA) and serial clock line (SCL), carry information between MPC5200B and other devices connected to the bus.
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I2C Controller The master terminates communication by generating a STOP signal, which frees the bus. The master can generate a STOP even if the slave has generated an acknowledge, at which point the slave must release the bus. The master can generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. 18.2.2.
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I2C Controller SCL 1 SDA by Transmitter Bit7 2 3 4 5 6 7 8 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0(R/W) 9 SDA by Receiver Start Figure 18-4. Timing Diagram—Receiver Acknowledgement 18.2.2.4 Repeated Start A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. The master uses this means to communicate with another slave or with the same slave in a different mode without releasing the bus.
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I2C Interface Registers Wait State Start Counting High Period SCL by Master1 SCL by Master2 SCL Figure 18-6. Timing Diagram—Clock Synchronization A data arbitration procedure determines the relative priority of contending masters. A bus master loses arbitration if it transmits logic “1” while another master transmits logic “0”. Losing masters immediately switch to slave-receive mode and stop driving SDA output. In this case, transition from master to slave mode does not generate a STOP condition.
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I2C Interface Registers I2C Address Register (MADR)—MBAR + 0x3D00 / 0x3D40 18.3.1 Table 18-2.
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I2C Interface Registers System Clock SCL SCL Period SDA SDA Hold SDA SCL Hold of STOP SCL Hold of START SCL START condition STOP condition Timing Diagram—SCL Period and SDA Hold Time Figure 18-8. Timing Diagram of I2C Signal Relationships For standard mode I2C, the I2C specification states that (SCL <= 100 kHz) AND (0.3 us <= SDA Hold Time <= 3.
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I2C Interface Registers 1. 2. 3. 4. 5. Identify all rows of Table 18-4 where SCL Period satisfies criteria (5). This set of rows limits the choices of SCL allowed for this particular system clock. Calculate the SCL associated with these rows according to (1), and decide which speeds are “acceptable” (fast enough or slow enough) for the system. Then, find the subset of those rows associated with the “acceptable” I2C clock speeds such that SDA Hold satisfies criteria (6).
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I2C Interface Registers FDR[7,6] FDR[5,1,0] FDR[4,3,2] SCL Period SDA Hold SCL Hold of START SCL Hold of STOP 00 000 011 144 25 70 73 00 000 100 288 49 142 145 00 000 101 576 97 286 289 00 000 110 1152 193 574 577 00 000 111 2304 385 1150 1153 00 001 000 30 9 11 16 00 001 001 48 11 20 25 00 001 010 88 17 38 45 00 001 011 160 25 78 81 00 001 100 320 49 158 161 00 001 101 640 97 318 321 00 001 110 1280 193 638 641 00
PAGE 627
I2C Interface Registers FDR[7,6] FDR[5,1,0] FDR[4,3,2] SCL Period SDA Hold SCL Hold of START SCL Hold of STOP 00 101 110 768 65 382 385 00 101 111 1536 129 766 769 00 110 000 24 8 8 13 00 110 001 36 9 14 19 00 110 010 64 13 26 33 00 110 011 112 17 54 57 00 110 100 224 33 110 113 00 110 101 448 65 222 225 00 110 110 896 129 446 449 00 110 111 1792 257 894 897 00 111 000 26 8 9 14 00 111 001 40 9 16 21 00 111 010 72
PAGE 628
I2C Interface Registers FDR[7,6] FDR[5,1,0] FDR[4,3,2] SCL Period SDA Hold SCL Hold of START SCL Hold of STOP 01 011 001 136 26 60 70 01 011 010 256 42 116 130 01 011 011 480 66 236 242 01 011 100 960 130 476 482 01 011 101 1920 258 956 962 01 011 110 3840 514 1916 1922 01 011 111 7680 1026 3836 3842 01 100 000 40 14 12 22 01 100 001 56 14 20 30 01 100 010 96 18 36 50 01 100 011 160 18 76 82 01 100 100 320 34 156 162
PAGE 629
I2C Interface Registers FDR[7,6] FDR[5,1,0] FDR[4,3,2] SCL Period SDA Hold SCL Hold of START SCL Hold of STOP 10 or 11 000 100 1152 196 568 580 10 or 11 000 101 2304 388 1144 1156 10 or 11 000 110 4608 772 2296 2308 10 or 11 000 111 9216 1540 4600 4612 10 or 11 001 000 120 36 44 64 10 or 11 001 001 192 44 80 100 10 or 11 001 010 352 68 152 180 10 or 11 001 011 640 100 312 324 10 or 11 001 100 1280 196 632 644 10 or 11 001 101 2560 38
PAGE 630
I2C Interface Registers 18.3.
PAGE 631
I2C Interface Registers Bit Name 0 EN Description I2C Enable—bit controls software reset of entire I2C module. If I2C module is enabled in the middle of a byte transfer, interface behaves as follows: • Slave mode ignores current bus transfer and starts operating when a subsequent start condition is detected. • Master mode is not aware if bus is busy. If a start cycle is initiated, current bus cycle may become corrupt.
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I2C Interface Registers I2C Status Register (MSR)—MBAR + 0x3D0C / 0x3D4C 18.3.4 Table 18-6.
PAGE 633
I2C Interface Registers Bit Name Description 5 SRW Slave Read/Write—when set, bit indicates the R/W command bit value of the calling address sent from the master. BE AWARE: Bit is valid only when I2C is in slave mode, a complete address transfer occurred with an address match, and no other transfers were initiated. Checking this bit, the CPU can select slave Tx/Rx mode according to the master command.
PAGE 634
I2C Interface Registers I2C Interrupt Control Register—MBAR + 0x3D20 18.3.6 Table 18-8.
PAGE 635
I2C Interface Registers • To the RX requestor at SDMA, if RE is set to 1. Typically, only one (or none) of the above destinations would be specified. Although, it may be useful to send an interrupt to both the CPU and SDMA. Selecting between TX and RX is based on whether the module is: • sending data (master or slave TX) • receiving data (master or slave RX) Individual requests trigger different SDMA tasks. Reset condition is, IE set and all other enable bits clear.
PAGE 636
Initialization Sequence An I2C glitch filter has been added outside the I2C legacy modules (but within the I2C package). This filter can absorb (or “eat”) glitches on both the I2C clock and data lines for each I2C module. The width of glitch to absorb can be specified in terms on number of IPBUS clock cycles. A single glitch filter control register is provided for both I2C modules.
PAGE 637
Transfer Initiation and Interrupt 18.5.3 Special Note on AKF A new status bit has been added to MSR[4] for the MPC5200B release of this chip. The reason for this is that the legacy I2C module was found to violate, in a merely academic sense, the I2C specification by sending out a very short 9th clock pulse after losing arbitration to another master. According to the I2C specification, the losing I2C master may only complete “one byte’s worth” of clock pulses after losing arbitration.
PAGE 638
Transfer Initiation and Interrupt Figure 18-9.
PAGE 639
Transfer Initiation and Interrupt MPC5200B Users Guide, Rev.
PAGE 640
Overview Chapter 19 Controller Area Network ( MSCAN ) 19.1 Overview The following sections are contained in this document: • Section 19.1, Overview • Section 19.2, Features • Section 19.3, External Signals • Section 19.4, CAN System • Section 19.5, Memory Map / Register Definition • Section 19.6, Programmer’s Model of Message Storage • Section 19.
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Features 19.2 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol - Version 2.
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Memory Map / Register Definition CAN node 1 CAN node 2 CAN node n MCU CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 19-2. The CAN System 19.5 Memory Map / Register Definition The MPC5200B contains 2 independent MSCAN Controller : • MSCAN1 = MBAR + 0x0900 • MSCAN2 = MBAR + 0x0980 19.5.1 Module Memory Map Table 19-1 and Table 19-2 give an overview on all registers and their individual bits in the MSCAN memory map.
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Memory Map / Register Definition Table 19-1. MSCAN Register Organization (continued) $__20 $__3F $__40 $__5F $__60 $__7F IDENTIFIER FILTER 16 BYTES RECEIVE BUFFER 16 BYTES (Window) TRANSMIT BUFFER 16 BYTES (Window) Table 19-1 shows the individual registers associated with the MSCAN and their relative offset from the base address. The detailed register descriptions follow in the order they appear in the register map (see Table 19-2). Table 19-2.
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Memory Map / Register Definition Table 19-2. Module Memory Map (continued) a b 19.5.
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Memory Map / Register Definition Bit Name Description 0 RXFRM Received Frame—flag bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. Once set, it remains set until cleared by software or reset. Clear by writing 1 to the bit. This bit is not valid in loop-back mode.
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Memory Map / Register Definition 19.5.4 MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x981 Table 19-4. MSCAN Control Register 1 RESET: 0 0 0 Rsvd 1 5 0 6 0 7 lsb INITAK 4 SLPAK 3 WUPM W 2 LOOPB CANE CLKSRC R 1 LISTEN msb 0 0 1 The MSCAN Control Register 1 provides for various control and handshake status information of the MSCAN module.
PAGE 647
Memory Map / Register Definition Bit Name Description 6 SLPAK Sleep Mode Acknowledge—flag indicates whether MSCAN module has entered sleep mode. It is used as a handshake flag for SLPRQ sleep mode request. Sleep mode is active when INITRQ=1 and INITAK=1. Depending on the WUPE bit setting, MSCAN clears the flag if it detects bus activity on CAN while in Sleep Mode.
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Memory Map / Register Definition Table 19-6. Baud Rate Prescaler (continued) BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P) 1 1 1 1 1 0 63 1 1 1 1 1 1 64 19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0x0905 / 0x985 Table 19-7. MSCAN Bus Timing Register 1 msb 0 W RESET: 2 3 4 5 TSEG[22:20] SAMP R 1 0 0 0 6 7 lsb TSEG[13:10] 0 0 0 0 0 The MSCAN Bus Timing Register 1 provides for various bus timing control of the MSCAN module.
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Memory Map / Register Definition Table 19-8. Time Segment 1 Values (continued) TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 1 1 4 Tq clock cycles ................................................................................................................................... 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles Table 19-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time segment 2 0 0 0 1 Tq clock cycle (a) 0 0 1 2 Tq clock cycles ........................
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Memory Map / Register Definition Bit Name Description 0 WUPIF WakeUp Interrupt Flag—If MSCAN detects bus activity while in sleep mode and WUPE=1 in CANTCTL0, it sets the WUPIF flag. If not masked, a WakeUp interrupt is pending while this flag is set. 0 = No WakeUp activity observed while in Sleep Mode. 1 = MSCAN detected bus activity and requested WakeUp.
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Memory Map / Register Definition Bit Name Description 7 RXF Receive Buffer Full—flag is set by MSCAN when a new message is shifted into RX FIFO. Flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After CPU reads message from RxFG buffer in Rx FIFO, RxF flag must be cleared to release the buffer. A set RxF flag prohibits shifting of next FIFO entry into foreground buffer (RxFG).
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Memory Map / Register Definition Bit Name Description 4:5 TSTATE[1:0] Transmitter Status Change Enable—bits control sensitivity level in which Tx state changes cause CSCIF interrupts. Independent of the chosen sensitivity level, TSTATE flags still indicate the actual Tx state and are only updated if no CSCIF interrupt is pending. 00 = Do not generate CSCIF interrupt caused by Tx state changes. 01 = Generate CSCIF interrupt only if transmitter enters or leaves “BusOff” state.
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Memory Map / Register Definition 19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)—MBAR+0x090D / 0x098D Table 19-13. MSCAN Transmitter Interrupt Enable Register msb 0 1 R 2 3 4 5 Reserved 6 7 lsb TXEIE[2:0] W RESET: Bit Name 0:4 — 5:7 TXEIE[2:0] 0 0 0 0 0 0 0 0 Description Reserved Transmitter Empty Interrupt Enable 0 = No interrupt request is generated from this event. 1 = Transmitter empty (Tx buffer available) event causes Tx empty interrupt request.
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Memory Map / Register Definition 19.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)—MBAR +0x0911 / 0x0991 Table 19-15. MSCAN Transmitter Message Abort Acknowledgement Register msb 0 1 R 2 3 4 5 Reserved 6 7 lsb ABTAK[2:0] W RESET: 0 0 0 0 0 0 0 0 Note: This register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). READ: Anytime WRITE: Not writable at any time .
PAGE 655
Memory Map / Register Definition 19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0x0915 / 0x0995 Table 19-17.
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Memory Map / Register Definition 19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C Table 19-20. MSCAN Receive Error Counter Register msb 0 1 2 R 3 4 5 6 7 lsb 0 0 0 RxERR[7:0] W RESET: 0 0 0 0 0 READ: Only when in Sleep Mode (SLPRQ = 1 and SLPAK = 1) or Initialization Mode (INITRQ = 1 and INITAK =1). WRITE: Unimplemented Bit Name 0:7 RxERR[7:0] Description This register reflects the status of the MSCAN receive error counter.
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Memory Map / Register Definition 19.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0920 / 0x09A0 Table 19-22.
PAGE 658
Memory Map / Register Definition Table 19-23.
PAGE 659
Memory Map / Register Definition 19.5.18 MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 / 0x09A8 Table 19-24.
PAGE 660
Memory Map / Register Definition Table 19-25.
PAGE 661
Programmer’s Model of Message Storage — CANIDMR7 19.6 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
PAGE 662
Programmer’s Model of Message Storage Table 19-27.
PAGE 663
Programmer’s Model of Message Storage Table 19-28. Standard Identifier Mapping Register IDR0 Read: Bit 7 6 5 4 3 2 1 Bit 0 ADDR ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 $__x0 ID2 ID1 ID0 RTR IDE (=0) Write: IDR1 Read: $__x1 Write: IDR2 Read: $__x4 Write: IDR3 Read: $__x5 Write: = Unuseda a Unused bits are always read ‘x’ 19.6.
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Programmer’s Model of Message Storage 19.6.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3 - DLC0 — Data Length Code bits The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
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Functional Description 19.6.5 MSCAN Time Stamp Register High (TSRH)—MBAR + 0x097C / 0x09FC Table 19-31. MSCAN Time Stamp Register (High Byte) TSR9 6 7 lsb TSR8 5 TSR10 4 TSR11 3 TSR12 2 TSR13 1 TSR14 R TSR15 msb 0 W RESET: 0 0 0 0 0 0 0 0 READ: Anytime WRITE: Unimplemented Bit Name Description 0:7 TSR[15:8] If TIME bit is enabled, MSCAN writes a special time stamp to respective registers in active Tx or Rx buffer as soon as a message is acknowledged on the CAN bus.
PAGE 666
Functional Description 19.7.2 Message Storage Rx0 RXF CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx3 Receiver TxBG Tx0 TXE0 PRIO Tx1 CPU bus TxFG MSCAN TXE1 PRIO Transmitter TxBG Tx2 TXE2 PRIO Figure 19-3. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 19.7.2.
PAGE 667
Functional Description A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, as such, reduces the reactiveness requirements on the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission and the bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances.
PAGE 668
Functional Description flag, and generates a receive interrupt Section 19.7.9.2, Receive Interrupt to the CPU1. The user’s receive handler has to read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors etc.
PAGE 669
Functional Description CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 0 Hit) Figure 19-4. 32-bit Maskable Identifier Acceptance Filter CAN 2.
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Functional Description CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID Accepted (Filter 1 Hit) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID Accepted (Filter 2 Hit) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID Accepted (Filter 3 Hit) Figure 19-6.
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Functional Description • • • 19.7.5 All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers Section 19.5.
PAGE 672
Functional Description • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. f Tq Bit Þ Rate = ---------------------------------------------------------------------------------------( number Þ of Þ Time Þ Quanta ) NRZ Signal SYNC_SEG Time Segment 1 (PROP_SEG + PHASE_SEG1) Time Segment 2 (PHASE_SEG2) 1 4 ... 16 2 ... 8 8 ...
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Functional Description Table 19-34. CAN Standard Compliant Bit Time Segment Settings (continued) 19.7.6 Synchronization Jump Width Time Segment 1 TSEG1 Time Segment 2 TSEG2 SJW 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 ..
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Functional Description a 19.7.8.1 ‘X’ means don’t care. CPU Run Mode As can be seen in Table 19-35, only MSCAN Sleep Mode is available as low power option, when CPU is in run mode. 19.7.8.2 CPU Sleep Mode While the CPU is in Sleep Mode, the MSCAN can be operated in Normal Mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 19-35. 19.7.8.
PAGE 675
Functional Description NOTE The MCU cannot clear the SLPRQ bit before Sleep Mode (SLPRQ=1 and SLPAK=1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before Sleep Mode was entered.
PAGE 676
Functional Description CPU Clock Domain CAN Clock Domain INITRQ SYNC sync. INITRQ sync. SYNC INITAK CPU Init Request INITAK Flag INITAK INIT Flag Figure 19-11. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN the INITRQ has to be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay ().
PAGE 677
Controller Area Network ( MSCAN ) 19.7.9.1 Transmit Interrupt Notes At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. 19.7.9.2 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set.
PAGE 678
Functional Description 19.7.9.4 Error Interrupt An overrun of the receiver FIFO, error, warning or Bus-Off condition occurred. The Section 19.5.7, MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 / 0x988 indicates one of the following conditions: • Overrun • An overrun condition of the receiver FIFO as described in Section 19.7.2.3, Receive Structures occurred. CAN Status Change The actual value of the Transmit and Receive Error Counters control the bus state of the MSCAN.
PAGE 679
Functional Description MPC5200B Users Guide, Rev.
PAGE 680
Overview Chapter 20 Byte Data Link Controller (BDLC) 20.1 Overview The BDLC module is a serial communication module which allows the user to send and receive messages across a Society of Automotive Engineers (SAE) J1850 serial communication network. The user’s software handles each transmitted or received message on a byte-by-byte basis, while the BDLC performs all of the network access, arbitration, message framing and error detection duties.
PAGE 681
Modes of Operation Power Off Vdd > Vdd(Min.) and Any MCU reset source asserted Vdd ≤ Vdd(Min.) Reset Any MCU reset source asserted (from any mode) No MCU reset source asserted BDLC Disabled BDLCE cleared in DLCSCR Network activity or other MCU wake-up BDLC Stop BDLCE set in DLCSCR Run STOP instruction or (WAIT instruction and WCM=1) Network activity or other MCU wake-up (WAIT instruction and WCM=0) BDLC Wait Figure 20-1.
PAGE 682
Modes of Operation • Run This mode is entered from the BDLC Disabled mode when the BDLCE bit in the BDLC Control Register is set. It is entered from the BDLC Wait mode whenever activity is sensed on the J1850 bus or some other MCU source wakes the CPU out of Wait mode. • It is entered from the BDLC Stop mode whenever network activity is sensed or some other MCU source wakes the CPU out of Stop mode.
PAGE 683
Block Diagram • Low Power Options The BDLC module can save power in Disabled, Wait, and Stop modes. A complete description of what the BDLC module does while in a low power mode can be found in Section 20.3, Modes of Operation. 20.
PAGE 684
Signal Description and reception. The MUX Interface provides the link between the BDLC digital section and the analog Physical Interface. The wave shaping, driving and digitizing of data is performed by the Physical Interface. NOTE The Physical Interface is not implemented in the BDLC module and must be provided externally. The main functional blocks of the BDLC module are explained in greater detail in the following sections.
PAGE 685
Memory Map and Registers Table 20-2. BDLC Control Register 1 R msb 0 1 2 3 4 5 6 7 lsb IMSG CLKS 0 0 0 0 IE WCM 1 1 0 0 0 0 0 0 W RESET: = Unimplemented or Reserved READ: any time WRITE: IMSG, IE, and WCM any time. CLKS write once in normal and emulation modes. CLKS bit has modified functionality in special test mode. Writes to unimplemented bits 5-2 are ignored.
PAGE 686
Memory Map and Registers 1 = Stop BDLC internal clocks during CPU wait mode (BDLC_STOP) 0 = Run BDLC internal clocks during CPU wait mode (BDLC_WAIT) 20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300 This register is provided to substantially decrease the CPU overhead associated with servicing interrupts while under operation of a MUX protocol.
PAGE 687
Memory Map and Registers • • If the CPU executes a STOP all clocks to the BDLC as well as the clocks in the MCU are turned off including clocks to the BDLC. The message which generates a Wake-up interrupt of the BDLC and the CPU will not be received correctly. Symbol Invalid or Out of Range CRC Error • The Cyclical Redundancy Check Byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message.
PAGE 688
Memory Map and Registers 0 = When cleared, digital filter input is connected to receive pin (RXB) and the transmitter output is connected to the transmit pin (TXB). The BDLC module is taken out of Digital Loopback Mode and can now drive and receive from the J1850 bus normally. After writing DLOOP to zero, the BDLC module requires the bus to be idle for a minimum of an End of Frame symbol time before allowing a reception of a message.
PAGE 689
Memory Map and Registers The BDLC supports the In-frame Response (IFR) feature of J1850 by setting these bits correctly. The four types of J1850 IFR are shown in Figure 20-3. The purpose of the in-frame response modes is to allow single or multiple nodes to acknowledge receipt of the data by responding to a received message after they have seen the EOD symbol.
PAGE 690
Memory Map and Registers After the byte in the BDLC Data Register has been loaded into the transmit shift register, the TDRE flag will be set in the BDLC State Vector Register register, similar to the main message transmit sequence. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated.The programmer should then load the next byte of the IFR into the BDLC Data Register for transmission.
PAGE 691
Memory Map and Registers NOTE The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition fault. This is helpful in preventing noise on the J1850 bus from corrupting a message. 20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305 This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC module. It is also used to pass data received from the J1850 bus to the CPU. Table 20-5.
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Memory Map and Registers Table 20-6. BDLC Analog Round Trip Delay Register R msb 0 1 2 3 4 5 6 7 lsb 0 RXPOL 0 BO4 BO3 BO2 BO1 BO0 0 1 0 1 0 0 0 0 W RESET: = Unimplemented READ: any time WRITE: write once in normal and emulation modes. Register functionality modified in special test mode. Writes to unimplemented bits 7, 5 are ignored. RXPOL — Receive Pin Polarity (Bit 6) The Receive pin Polarity bit is used to select the polarity of incoming signal on the receive pin.
PAGE 693
Memory Map and Registers Table 20-7. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment (continued) BARD Offset Bits BO[4:0] Corresponding Expected Transceiver’s delays (µs) Transmitter Symbol Timing Adjustment (tbdlc)1 01111 15 15 10000 16 16 10001 17 17 10010 18 18 10011 19 19 10100 20 20 10101 21 21 10110 22 22 10111 23 23 11000 24 24 11001 25 25 11010 26 26 11011 27 27 11100 28 28 11101 29 29 11110 30 30 11111 31 31 Note: 1.
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Memory Map and Registers Table 20-9. BDLC Rate Selection for Binary Frequencies [CLKS = 1] IP bus clock frequency R[7:0] division fbdlc fCLOCK=1.048576 MHz $00 1 1.048576 MHz Table 20-10. BDLC Rate Selection for Integer Frequencies [CLKS = 0] 20.7.3.7 IP bus clock frequency R[7:0] division fbdlc fCLOCK=132.00000 MHz $83 132 1.000000 MHz fCLOCK=66.00000 MHz $41 66 1.000000 MHz fCLOCK=54.00000 MHz $35 54 1.000000 MHz fCLOCK=33.00000 MHz $20 33 1.000000 MHz fCLOCK=27.
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Functional Description Table 20-12. BDLC Status Register R msb 0 1 2 3 4 5 6 7 lsb 0 0 0 0 0 0 0 IDLE W Unimplemented RESET: 0 0 0 Reserved 0 0 Unimplemented 0 0 0 = Unimplemented READ: any time WRITE: ignored in normal and emulation modes Register functionality is modified in special test mode. IDLE Idle (Bit 0) This bit indicates when the BDLC module is idle. 1 = BDLC module has received IFS and no data is being transmitted or received.
PAGE 696
Functional Description • Messages transmitted by the BDLC module onto the J1850 bus must contain at least one data byte, and therefore can be as short as one data byte and one CRC byte. Each data byte in the message is 8 bits in length, transmitted MSB to LSB. CRC - Cyclical Redundancy Check Byte This byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message.
PAGE 697
Functional Description Active 128µs OR 64µs OR 64µs Passive Logic “0” (a) Active 128µs Passive Logic “1” (b) Active 200µs 200µs Start of Frame (c) End of Data (d) Passive Active ≥ 240µs 280µs Passive End of Frame (e) Break (f) Active 20µs EOD EOF Passive 300µs Inter-Frame Seperator (IFS) (g) Figure 20-5.
PAGE 698
Functional Description • The SOF symbol is defined as passive to active transition followed by an active period 200µs in length (Figure 20-5(c)). This allows the data bytes which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic one or a logic zero. EOD - End of Data Symbol • The EOD symbol is defined as an active to passive transition followed by a passive period 200µs in length (Figure 20-5(d)).
PAGE 699
Functional Description Table 20-13. BDLC Transmitter VPW Symbol Timing for Integer Frequencies (continued) Number Characteristic Symbol Min Typ Max Unit 5 Start of Frame (SOF) Ttva3 198 200 202 tbdlc 6 End of Data (EOD)1 Ttvp3 162 164 166 tbdlc Ttv4 238 240 242 tbdlc Ttv5 298 300 302 tbdlc 1 7 End of Frame (EOF) 8 Inter-Frame Separator (IFS)1 Note: 1. The transmitter timing for this symbol depends upon the minimum detection time of the symbol by the receiver.
PAGE 700
Functional Description Table 20-16.
PAGE 701
Functional Description The min and max symbol limits shown in the following sections (Invalid Passive Bit - Valid BREAK Symbol) and figures (Figure 20-6 Figure 20-9) refer to the values listed in Table 20-13 throughTable 20-18. • Invalid Passive Bit If the passive to active transition beginning the next data bit or symbol occurs between the active to passive transition beginning the current data bit or symbol and Trvp1(Min), the current bit would be invalid. See Figure 20-6(1).
PAGE 702
Functional Description 300µs 280µs Active (1) Valid EOF Symbol Passive Trv4(Min) Trv4(Max) Active Passive (2) Valid EOF+ IFS Symbol Trv5(Min) Figure 20-7. J1850 VPW EOF and IFS Symbols • Valid EOF & IFS Symbol In Figure 20-7(1), if the passive to active transition beginning the SOF symbol of the next message occurs between Trv4(Min) and Trv4(Max), the current symbol will be considered a valid EOF symbol.
PAGE 703
Functional Description 200µs 128µs 64µs Active (1) Invalid Active Bit Passive Active Trva2(Min) (2) Valid Active Logic One Passive Active Trva2(Min) Trva2(Max) (3) Valid Active Logic Zero Passive Trva1(Min) Active Trva1(Max) (4) Valid SOF Symbol Passive Trva3(Min) Trva3(Max) Figure 20-8.
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Functional Description • Valid BREAK Symbol • If the next active to passive transition does not occur until after Trv6(Min), the current symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a SOF symbol beginning the next message to be transmitted onto the J1850 bus. See Figure 20-9.
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Functional Description 20.8.1.4 J1850 Bus Errors The BDLC module detects several types of transmit and receive errors which can occur during the transmission of a message onto the J1850 bus. • Transmission Error • If the BDLC module is transmitting a message and the message received contains a symbol error, a framing error, a bus fault, a BREAK symbol, or a logic ‘1’ symbol when a logic “0” is being transmitted, this constitutes a transmission error.
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Functional Description If a BREAK symbol is received while the BDLC module is transmitting or receiving, the symbol invalid or out of range flag (in BDLC State Vector Register) is set. Further transmission/reception will be disabled until the J1850 bus returns to the passive state and a valid EOF symbol is detected on the J1850 bus. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated.
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Functional Description Input Sync Rx Data from RXB pad Filtered Rx Data Out 4-Bit Up/Down Counter 4 d q up/down out Edge & Count Comparator d q MUX Interface Clock Figure 20-11. BDLC Module Rx Digital Filter Block Diagram • Operation The clock for the digital filter is provided by the MUX Interface clock.At each positive edge of the clock signal, the current state of the Receiver input signal from the RXB pad is sampled.
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Functional Description 20.8.3.1 Protocol Architecture The Protocol Handler contains the State Machine, Rx Shadow Register, Tx Shadow Register, Rx Shift Register, Tx Shift Register, and Loopback Multiplexer as shown in Figure 20-12. Each block will now be described in more detail.
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Functional Description • Digital Loopback Multiplexer • The Digital Loopback Multiplexer connects the input of the receive digital filter (See Figure 20-12) to either the transmit signal out to the pad (TXB) or the receive signal from the pad (RXB), depending on the state of the DLOOP bit in BDLC Control Register 2 register. State Machine • All of the functions associated with performing the protocol are executed or controlled by the State Machine.
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Functional Description NOTE Due to the byte-level architecture of the BDLC module, the 12-byte limit on message length as defined in SAE J1850 must be enforced by the user’s software. The number of bytes in a message (transmitted or received) has no meaning to the BDLC module. — Step 1: Write the First Byte into the BDLC Data Register To initiate a message transmission, the CPU simply loads the first byte of the message to be transmitted into the BDLC Data Register.
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Functional Description Similar to a loss of arbitration, if any error (except a CRC error) is detected on the SAE J1850 bus during a transmission, the BDLC module will stop transmitting immediately. The byte which was being transmitted will be discarded, and the “Symbol Invalid or Out of Range” status will be reflected in the BDLC State Vector Register.
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Functional Description Enter BDLC module Transmit Routine C A Write first message byte to be transmitted into DLCBDR No Is this the last byte? Yes For interrupt driven systems, this marks the beginning of the transmit section of the BDLC module interrupt service routine Go to BDLC module BREAK/Error Handling Routine Yes Is DLCBSVR = $00? No Yes Set TEOD bit in DLCBCR2 Is DLCBSVR = $1C? (Invalid Symbol) IFR Received? No Jump to Receive IFR Handling Routine No B Jump to BDLC module Receive Routi
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Functional Description 20.8.5.1 BDLC Reception Control Bits The only control bit which is used for message reception, the IMSG bit, is actually used to prevent message reception. When the IMSG bit is set BDLC module interrupts of the CPU are inhibited until the next SOF symbol is received. This allows the BDLC module to ignore the remainder of a message once the CPU has determined that it is of no interest.
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Functional Description Once a message byte has been received, the CPU must service the BDLC Data Register before the next byte is received, or the first byte will be lost. If the BDLC Data Register is not serviced quickly enough, the next byte received will be written over the previous byte in the BDLC Data Register. No receiver overrun indication is made to the CPU.
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Functional Description Enter BDLC module Receive Routine Is DLCBSVR = $1C/$18? (Error Detected) Yes Go to BDLC module BREAK/Error Handling Routine B No Is DLCBSVR = $0C? (RDRF) Yes Read byte in DLCBDR No Jump to Receive IFR Handling Routine Is this a transmit reflection? Yes Is this an IFR reception? No Filter received byte Yes No Store received byte (in case of LOA) B Once BDLC module Detects EOF, message reception is complete Yes Is DLCBSVR = $04? (EOF) Yes No Is this message of any i
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Functional Description 20.8.6.1 IFR Types Supported by the BDLC module SAE J1850 defines four distinct types of IFR. The first (and most basic) IFR is Type 0, or no IFR. IFR types 1, 2 & 3 are each made up of one or more bytes and, depending upon the type used, may be followed by a CRC byte. The BDLC module is designed to allow the user to transmit and receive all types of SAE J1850 IFRs, but only the network framing/error checking/bus acquisition duties are performed by the BDLC module.
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Functional Description Table 20-20. IFR Control Bit Priority Encoding READ/WRITE 20.8.6.3 ACTUAL TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0 0 0 0 0 0 0 1 X X 1 0 0 0 1 X 0 1 0 0 0 1 0 0 1 Transmit Single Byte IFR The Transmit Single Byte IFR (TSIFR) bit in BDLC Control Register 2 is used to transmit Type 1 and Type 2 IFRs onto the SAE J1850 bus.
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Functional Description • Transmitting a Type 1 IFR • To transmit a Type 1 IFR, the user loads the byte to be transmitted into the BDLC Data Register and sets both the TSIFR bit and the TEOD bit. This will direct the BDLC module to attempt transmitting the byte written to the BDLC Data Register one time, preceded by the appropriate Normalization Bit. If the transmission is not successful, the byte will be discarded and no further transmission attempts will be made.
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Functional Description Enter Type 1 IFR Transmit Routine Load IFR byte into DLCBDR Set TSIFR and TEOD No Is DLCBSVR = $1C? (Error Detected) Is DLCBSVR = $14? (LOA) Yes Yes IFR byte is discarded No IFR byte is discarded Jump to Receive IFR Handling Routine Once BDLC module detects, or EOF, IFR transmit attempt is complete Exit Type 1 IFR Transmit Routine Figure 20-15.
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Functional Description byte when TEOD is set, the BDLC module will continue the transmission until it is successful or it loses arbitration to another transmitter. At this point it will then discard the byte and make no more transmit attempts. NOTE When transmitting a Type 2 IFR, the user should monitor the number of IFR bytes received to ensure that the overall message length does not exceed the 12-byte limit for the length of SAE J1850 messages.
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Functional Description The user begins initiation of a Type 3 IFR, as with each of the other IFR types, by loading the desired IFR byte into the BDLC Data Register. If a byte has already been written into the BDLC Data Register for transmission as a new message, the user can simply write the first IFR byte to the BDLC Data Register, replacing the previously written byte. This must be done before the first EOD symbol is received.
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Functional Description Enter Type 3 IFR Transmit Routine Write first IFR byte to be transmitted into DLCBDR A Set desired TMIFR bit in DLCBCR2 Load next byte to be transmitted into DLCBDR (clears TDRE) Set TEOD bit in DLCBCR2 Yes Only one byte to transmit? No No Yes Yes Is DLCBSVR = $00? For interrupt driven systems, this marks the beginning of the transmit Type 3 IFR section of the BDLC module interrupt service routine Abandon IFR transmit attempt Is this the last byte? No Yes Set TEOD bit in
PAGE 723
Functional Description NOTE As with a message transmission, the IMSG bit should never be used to ignore the BDLC module’s own IFR transmissions. This is again due to the BDLC State Vector Register bits being inhibited from updating until IMSG is cleared, preventing the CPU from detecting any IFR-related state changes which may be of interest. 20.8.7.
PAGE 724
Functional Description .
PAGE 725
Functional Description Because of the BDLC module’s architecture, it can both transmit and receive messages of unlimited length. The CRC calculations, both for transmitting and receiving, are not limited to eight bytes, but will instead be calculated and verified using all bytes in the message, regardless of the number. All control bits, including TEOD and IMSG, also work in an identical manner, regardless of the length of the message.
PAGE 726
Functional Description Enter BDLC module Transmit Routine C A Write first message byte to be transmitted into DLCBDR No Is this the last byte? Yes Go to BDLC module BREAK/Error Handling Routine Yes Is DLCBSVR = $00? For interrupt driven systems, this marks the beginning of the transmit section of the BDLC module interrupt service routine No Yes Set TEOD bit in DLCBCR2 Is DLCBSVR = $1C? (Invalid Symbol) IFR Received? No Jump to Receive IFR Handling Routine No B Jump to BDLC module Receive Rou
PAGE 727
Functional Description 20.8.9.2 Initializing the Configuration Bits The first step necessary for initializing the BDLC module following an MCU reset is to write the desired values to each of the BDLC module control registers. This is best done by storing predetermined initialization values directly into these registers. The following description outlines a basic flow for initializing the BDLC module.
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Functional Description time passes between the exit from loopback modes and enabling the BDLC module and the enabling of interrupts. It is a good practice to always clear any source of interrupts before enabling interrupts on any MCU subsystem. • If any interrupts are pending (BDLC State Vector Register not %00000000), then each interrupt source should be dealt with accordingly.
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Resets BDLC module enters Run mode from Reset mode Write desired config. data into DLCBARD Write desired divisor - 1 into DLCBRSR Write desired config. data into DLCBCR2 Write desired config.
PAGE 730
Overview Chapter 21 Debug Support and JTAG Interface 21.1 Overview The following sections are contained in this document: • Section 21.2, TAP Link Module (TLM) and Slave TAP Implementation • Section 21.3, TLM and TAP Signal Descriptions • Section 21.4, Slave Test Reset (STRST) • Section 21.5, TAP State Machines • Section 21.6, e300 Core JTAG/COP Serial Interface • Section 21.7, TLM Link DR Instructions • Section 21.8, TLM Test Instructions, includes: — Section 21.8.1, IDCODE — Section 21.8.1.
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TAP Link Module (TLM) and Slave TAP Implementation TRST- TRSTTCK TMS TDI SEL[0:n] ENA[0:n] ENA[0:n] STRST- TDI STRST- TDO TAP Link Module (TLM) [0] ENA SEL TRSTTCK TCK TMS TAP TDO TMS TDI [1] ENA [1] SEL TRSTTCK TMS TDI TCK [0] SEL[0:n] TDI [0] STDO[0:n] TMS STD0[0:n] TCK TAP TMS TDO [1] TDI Figure 21-1. Generic TLM/TAP Architecture Diagram MPC5200B Users Guide, Rev.
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TAP Link Module (TLM) and Slave TAP Implementation ENA[0:n] TLMENA Link & & & & ShiftDR ClockDR UpdateDR STDO[0:n] DeviceID BdyScan Bypass & edoce ShiftDR ClockDR UpdateDR TLMSEL SEL[0:n] TDO TDI IR & TMS TCK TRST- TAP State Machine ShiftDR ClockDR UpdateDR ShiftIR ClockIR UpdateIR STRST- Figure 21-2. Generic TAP Link Module (TLM) Diagram MPC5200B Users Guide, Rev.
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TLM and TAP Signal Descriptions DeviceID BdyScan ShiftDR ClockDR UpdateDR TDI ENA TMS TCK edoce Bypass SEL IR Update-DR or Run-Test/Idle & TDO 1 0 TAP State Machine TRST- ShiftDR ClockDR UpdateDR ShiftIR ClockIR UpdateIR Figure 21-3. Generic Slave TAP 21.3 21.3.1 TLM and TAP Signal Descriptions Test Reset (TRST) JTAG reset, active low. When asserted, any on-going JTAG operation is immediately aborted. All TAP state machines, including the TLM, immediately enter the Test-Logic-Reset state.
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Slave Test Reset (STRST) 21.3.5 Test Data Out (TDO) Serial test data output is routed from the active shift register to this pin. To ensure setup and hold time for TDO when connected to TDI (of another device), TDO switches at the TCK falling edge. TDO is driven while the TLM state machine is in the Shift-IR or Shift-DR states only; it is tri-stated in all other TAP states. Except, for the first half clock after exiting the shift state, because of its falling edge timing. 21.
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e300 Core JTAG/COP Serial Interface 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift_IR 0 1 Exit1-DR 1 Exit1-IR 0 Exit2-DR Pause-IR Update-DR 0 1 0 Exit2-IR 1 1 1 0 1 0 0 1 0 Pause-DR 1 1 Update-IR 0 1 0 Figure 21-4.
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TLM Link DR Instructions Long Shift Register Latch Boundry Scan External Memory Scan RunN Counter COP_PVR TDI TDO D Q Instruction/Status Register TCK TMS TRST TAP Controller COP Controller Figure 21-5. e300 Core JTAG/COP Serial Interface 21.7 TLM Link DR Instructions — CAUTION — 1. 2. 3. For the following registers, only the instruction codes listed should be used. All other codes must be considered private and potentially damaging.
PAGE 737
TLM Test Instructions 21.7.1 TLM:TLMENA The TLM:TLMENA pseudo-instruction selects the 6-bit TLM IR. 21.7.2 TLM:PPCENA The TLM:PPCENA pseudo-instruction selects the 8-bit microprocessor CPU test IR. 21.8 TLM Test Instructions The TLM IR activates device-level functions, including the mandatory JTAG instructions and private device test data registers. Table 21-2.
PAGE 738
e300 COP/BDM Interface Preload: To shift an initial value into the boundary scan register prior to loading the EXTEST or CLAMP instruction into the Instruction register. Capture value may be examined or ignored. Update value has no effect until EXTEST/CLAMP instruction is loaded. It is then presented at the device pins. 21.8.4 EXTEST The EXTEST instruction selects the Boundary Scan DR to be logically connected between TDI and TDO during DR shift operations.
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Debug Support and JTAG Interface Notes MPC5200B Users Guide, Rev.
PAGE 740
A Appendix A Acronyms and Terms This section contains an alphabetical list of terms, phrases, acronyms, and abbreviations used in this book. Some terms and definitions included are reprinted from IEEE Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of Electrical and Electronics Engineers, Inc. with permission of the IEEE. A AAL . . . . . . . . . . . . . . . . . . . ATM Adaptation Layer ABR . . . . . . . . . . . . . . . . . . . Available Bit-Rate.
PAGE 741
C BIP . . . . . . . . . . . . . . . . . . . . Bit Interleaved Parity BIST . . . . . . . . . . . . . . . . . . . Built-In Self Test BISYNC . . . . . . . . . . . . . . . . Binary Synchronous communication Blockage . . . . . . . . . . . . . . . . A pipeline stall that occurs when an instruction occupies an execution unit and prevents a subsequent instruction from being dispatched. Boundedly undefined . . . . . . A characteristic of certain operations results not rigidly prescribed by the PowerPC architecture.
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D Context synchronization . . . . An operation that ensures: • all instructions in execution complete past the point where they can produce an exception • all instructions in execution complete in the context in which they began execution • all subsequent instructions are fetched and executed in the new context. . . . . . . . . . . . . . . . . . . . . . . . Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain events occur (such as an exception). COP.
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E E EA . . . . . . . . . . . . . . . . . . . . . Effective Address—The 32- or 64-bit address specified for a load, store, or instruction fetch. This address is then submitted to the MMU for translation to either a physical memory address or an I/O address. ED . . . . . . . . . . . . . . . . . . . . . Endpoint Descriptor EEST . . . . . . . . . . . . . . . . . . . Enhanced Ethernet Serial Transceiver en. . . . . . . . . . . . . . . . . . . . . . enable EPROM. . . . . . . . . . . . . . . . .
PAGE 744
H H Harvard architecture . . . . . . . An architectural model featuring separate caches for instruction and data. HC, Hc . . . . . . . . . . . . . . . . . Host Controller HCD . . . . . . . . . . . . . . . . . . . Host Controller Driver HDLC . . . . . . . . . . . . . . . . . . High-level Data Link Control—a transmission protocol used at the data link layer (layer 2) of the OSI seven layer model for data communications.
PAGE 745
J J JAVA™ . . . . . . . . . . . . . . . . . From Sun Microsystems, Inc.—a robust and versatile programming language that enables developers to: • Write software on one platform and run it on another. • Create programs to run within a web browser. • Develop server-side applications for online forums, stores, polls, processing HTML forms, and more. • Write applications for cell phones, two-way pagers, and other consumer devices. JTAG . . . . . . . . . . . . . . . . . . . Joint Test Action Group K Kbps . . .
PAGE 746
N MAC/PHY . . . . . . . . . . . . . . Multiply-and-ACcumulate/Physical Layer Device Master . . . . . . . . . . . . . . . . . . Name given to a bus device granted control, or mastership, of the bus. MBAR. . . . . . . . . . . . . . . . . . Module Base Address Register Mb, Mbit . . . . . . . . . . . . . . . . Megabit (written with lowercase b; 1024 Kilobits) MB, MByte . . . . . . . . . . . . . . MegaByte (written with uppercase B; 1024 KiloBytes) Mbps . . . . . . . . . . . . . . . . . . .
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O O OC. . . . . . . . . . . . . . . . . . . . . Output Compare OE . . . . . . . . . . . . . . . . . . . . . Output Enable signal OEA . . . . . . . . . . . . . . . . . . . Operating Environment Architecture—the level of PowerPC architecture that describes memory management model, supervisor-level registers, synchronization requirements, and the exception model. It also defines the time-base feature from a supervisor-level perspective. OHCI. . . . . . . . . . . . . . . . . . .
PAGE 748
Q PTE . . . . . . . . . . . . . . . . . . . . Page Table Entry PTI. . . . . . . . . . . . . . . . . . . . . Payload Type Identifier PTP . . . . . . . . . . . . . . . . . . . . Port-To-Port switching PTR . . . . . . . . . . . . . . . . . . . . Program Trace PVR. . . . . . . . . . . . . . . . . . . . Processor Version Register PWM . . . . . . . . . . . . . . . . . . . Pulse Width Modulator Q QNX . . . . . . . . . . . . . . . . . . .
PAGE 749
S Scalability . . . . . . . . . . . . . . . The capability of an architecture to generate implementations specific for a wide range of purposes, and in particular implementations of significantly greater performance and/or functionality than at present, while maintaining compatibility with current implementations. Scan chain . . . . . . . . . . . . . . . The peripheral buffers of a device, linked in JTAG test mode, that are addressed in a shift-register fashion. SCC. . . . . . . . . . . . . . . . . . . .
PAGE 750
T stp . . . . . . . . . . . . . . . . . . . . . stop str . . . . . . . . . . . . . . . . . . . . . start STS . . . . . . . . . . . . . . . . . . . . Special Transfer Start Superscalar machine . . . . . . . A machine that can issue multiple instructions concurrently from a conventional linear instruction stream. Supervisor mode . . . . . . . . . . The privileged operation state of a processor.
PAGE 751
W VBR . . . . . . . . . . . . . . . . . . . Variable Bit-Rate VC. . . . . . . . . . . . . . . . . . . . . Virtual Channel, Circuit, Call, or Connection VCC . . . . . . . . . . . . . . . . . . . Virtual Channel Connection VCI . . . . . . . . . . . . . . . . . . . . Virtual Circuit Identifier VCO . . . . . . . . . . . . . . . . . . . Voltage-Controlled Oscillator VEA . . . . . . . . . . . . . . . . . . .
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Appendix B List of Registers Section 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.5.12 5.5.13 5.5.14 CDM Registers ............................................................................................................................................5-11 CDM JTAG ID Number Register—MBAR + 0x0200 ......................................................................... 5-12 CDM Power On Reset Configuration Register—MBAR + 0x0204 .............................................
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7.3.2.1.13 7.3.2.1.14 7.3.2.1.15 7.3.2.1.16 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ...................................... 8-44 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34........................................ 8-45 GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 ......................................... 8-45 GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C ....................................................... 8-46 Section 7.3.2.
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Section 9.7.2 9.7.2.1 9.7.2.2 9.7.2.3 9.7.2.4 9.7.2.5 SCLPC Registers—MBAR + 0x3C00 ....................................................................................................... 9-23 SCLPC Packet Size Register—MBAR + 0x3C00 ............................................................................... 9-23 SCLPC Start Address Register—MBAR + 0x3C04 ............................................................................ 9-24 SCLPC Control Register—MBAR + 0x3C08...............................
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10.3.3.1.6 10.3.3.1.7 10.3.3.1.8 10.3.3.1.9 10.3.3.1.10 10.3.3.1.11 10.3.3.1.12 10.3.3.1.13 10.3.3.1.14 10.3.3.2.15 Tx Last Word PCITLWR(R) —MBAR + 0x3814.............................................................................. 10-28 Tx Bytes Done Counts PCITDCR(R) —MBAR + 0x3818 ............................................................... 10-28 Tx Packets Done Counts PCITPDCR(R) —MBAR + 0x3820 .......................................................... 10-28 Tx Status PCITSR(RWC) —MBAR + 0x381C ...
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Section 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.3.3.6 11.3.3.7 11.3.3.8 11.3.3.9 11.3.3.10 11.3.3.11 11.3.3.12 ATA Drive Registers—MBAR + 0x3A00.................................................................................................11-12 ATA Drive Device Control Register—MBAR + 0x3A5C ..................................................................11-12 ATA Drive Alternate Status Register—MBAR + 0x3A5C .................................................................
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13.15.8 13.15.9 15.2.10 13.15.11 13.15.12 13.15.13 13.15.14 13.15.15 13.15.16 13.15.17 13.15.18 13.15.19 13.15.20 13.15.21 13.15.22 13.15.23 13.15.24 13.15.25 13.15.26 13.15.27 13.15.28 13.15.29 13.15.30 13.15.31 13.15.32 SDMA Task Control 0 Register—MBAR + 0x121C ........................................................................... 13-9 SDMA Task Control 2 Register—MBAR + 0x1220.......................................................................... 13-10 Interrupt Status Register (0x14) — ISR ...
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Section 14.8 14.8.1 14.8.2 14.8.3 14.8.4 14.8.5 14.8.6 14.8.7 14.8.8 FEC Tx FIFO Status Register—MBAR + 0x31A8.................................................................................. 14-28 FEC Rx FIFO Control Register—MBAR + 0x318C ......................................................................... 14-29 FEC Rx FIFO Last Read Frame Pointer Register—MBAR + 0x3190 .............................................. 14-30 FEC Rx FIFO Last Write Frame Pointer Register—MBAR + 0x3194..................
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15.2.43 15.2.44 15.2.45 Tx FIFO Write Pointer (0x96)—TFWPTR ........................................................................................ 15-43 Tx FIFO Last Read Frame (0x9A)—TFLRFPTR .............................................................................. 15-43 Tx FIFO Last Write Frame PTR (0x9C)—TFLWFPTR..................................................................... 15-43 Section 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 16.2.7 16.2.8 16.2.9 16.2.10 16.2.11 16.2.12 16.2.
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19.5.16 19.5.17 19.5.18 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D.................... 19-17 MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0920 / 0x09A0 .......................... 19-18 MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 / 0x09A8..................................... 19-20 Section 19.6.1 19.6.2 19.6.3 19.6.4 19.6.5 19.6.6 Identifier Registers (IDR0-3) ............................................................................................................
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MPC5200B Users Guide, Rev.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.