Circuit Board Reference Manual

MCF548x Reference Manual, Rev. 3
20-2 Freescale Semiconductor
20.1.3 Features
• Direct support for up to five external PCI bus masters
• Fair arbitration scheme
• Hidden bus arbitration
• Bus parking
• Master time-out
• Interface with 33 MHz and 66 MHz PCI
20.2 External Signal Description
This section defines the PCI arbiter and corresponding external I/O signals. Table 20-1 summarizes this
information.
20.2.1 Frame (PCIFRM)
The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is deasserted
when the initiator is ready to complete the final data phase.
20.2.2 Initiator Ready (PCIIRDY)
The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
20.2.3 PCI Clock (CLKIN)
The CLKIN signal serves as a reference clock for generation of the internal PCI clock.
20.2.4 External Bus Grant (PCIBG[4:1])
The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI
arbiter is enabled, it asserts one of the PCIBG
[4:1] lines to grant ownership of the PCI bus to an external
master. When the PCI arbiter module is disabled, PCIBG[4:1] are driven high and should be ignored.
Table 20-1. PCI Arbiter External Signals
Name Type Function MCF548x Reset
PCIFRM I/O Frame Tristate
PCIIRDY I/O Initiator Ready Tristate
CLKIN I Clock Toggling
PCIBG0 / PCIREQOUT O External Bus Grant / Request Output Tristate
PCIBG[4:1] O External Bus Grant Tristate
PCIBR0 / PCIGNTIN I External Request / Grant Input Tristate
PCIBR[4:0] I External Bus Request Tristate