Circuit Board Reference Manual

MCF548x Reference Manual, Rev. 3
19-36 Freescale Semiconductor
19.3.3.2.1 Rx Packet Size Register (PCIRPSR)
19.3.3.2.2 Rx Start Address Register (PCIRSAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Packet_Size[15:2] Packet_Size
[1:0]
W
Reset0000000000000000
1514131211109876543210
R0000000000000000
W
Reset0000000000000000
Reg
Addr
MBAR + 0x8480
Figure 19-34. Rx Packet Size Register (PCIRPSR)
Table 19-33. PCIRPSR Field Descriptions
Bits Name Description
31–18 Packet_Size Packet_Size [15:2]. The Packet_Size field indicates the number of bytes for the receive controller
to read over PCI. Only bits [15:2] are writable. Only 32-bit data transfers to the FIFO are allowed.
Writing to this register also completes a Restart Sequence as long as the Master Enable bit,
PCIRER[ME], is high and Reset Controller bit, PCIRER[RC], is low.
17-16 Packet_Size [1:0] The two low bits are hardwired low.
15–0 — Reserved, should be cleared. No Bus Error is generated.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RStart_Add
W
Reset0000000000000000
1514131211109876543210
RStart_Add
W
Reset0000000000000000
Reg
Addr
MBAR + 0x8484
Figure 19-35. Rx Start Address Register (PCIRSAR)