Circuit Board Reference Manual

MCF548x Reference Manual, Rev. 3
18-24 Freescale Semiconductor
18.8 SDRAM Example
This example interfaces two 16M × 16-bit × 4 bank DDR SDRAM components to an MCF548x operating
at a 120 MHz SDCLK frequency. Table 18-14 lists design specifications for this example.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BRD2PRE BWT2RW BRD2WT
BL
W
Reset Uninitialized
1514131211109876543210
R0000000000000000
W
Reset0000000000000000
Reg
Addr
MBAR + 0x010C
Figure 18-13. SDRAM Configuration Register 2 (SDCFG2)
Table 18-13. SDCFG2 Field Descriptions
Bits Name Description
31–28 BRD2PRE Burst Read to Read/Precharge delay. Limiting case is Read to Read.
For DDR, suggested value = 0x4 (BurstLength/2)
For SDR, suggested value = 0x8 (BurstLength)
27–24 BWT2RW Burst Write to Read/Write/Precharge delay. Limiting case is Write to Precharge.
For DDR, suggested value = 0x6 (BurstLength/2 + t
WR
)
For SDR, suggested value = 0x8 (BurstLength + t
WR
- 2 Clocks)
23–20 BRD2WT Burst Read to Write delay.
For DDR, suggested value = 0x7
For SDR:
If CASL = 2, suggested value = 0xB
If CASL = 3, suggested value = 0xC
19–16 BL Burst Length. Write 0x7 (Burst Length - 1)
15–0 — Reserved. Should be cleared.
Table 18-14. SDRAM Example Specifications
Parameter Specification
13 row and 9 column addresses
Two bank-select lines to access four internal banks
Allowable burst lengths 2, 4, or 8
CAS latency 2
Clock cycle time (t
CK
) 7.5ns (min)
ACTV-to-read/write delay (t
RCD
) 15 ns (min) 18ns (max)