Circuit Board Reference Manual

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MCF548x Reference Manual

Devices Supported:

MCF5485 MCF5482

MCF5484 MCF5481

MCF5483 MCF5480

Document Number: MCF5485RM

Rev. 3

01/2006

Summary of content (1032 pages)

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MCF548x Reference Manual Devices Supported: MCF5485 MCF5484 MCF5483 MCF5482 MCF5481 MCF5480 Document Number: MCF5485RM Rev.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.
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Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Controller (PCI) PCI Bus Arbiter (PCIARB) FlexCAN Integrated Secuity Engine (SEC) IEEE 1149.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A IND Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Contro
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Contents Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.4.1 1.4.4.2 1.4.5 1.4.6 1.4.6.1 1.4.6.2 1.4.6.3 1.4.6.4 1.4.6.5 1.4.6.6 1.4.6.7 1.4.7 1.4.8 1.4.9 1.4.10 1.4.11 1.4.11.1 1.4.11.2 1.4.11.3 MCF548x Family Overview ........................................................................................... 1-1 MCF548x Block Diagram ..............................................................................................
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Contents Paragraph Number 2.2.1.4 2.2.1.5 2.2.1.6 2.2.1.7 2.2.1.8 2.2.1.9 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.2.2.7 2.2.2.8 2.2.2.9 2.2.2.10 2.2.2.11 2.2.2.12 2.2.2.13 2.2.2.14 2.2.3 2.2.3.1 2.2.3.2 2.2.3.3 2.2.3.4 2.2.3.5 2.2.3.6 2.2.3.7 2.2.3.8 2.2.3.9 2.2.3.10 2.2.3.11 2.2.3.12 2.2.3.13 2.2.3.14 2.2.3.15 2.2.3.16 2.2.4 2.2.4.1 2.2.5 Title Page Number Read/Write (R/W) .................................................................................................
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Contents Paragraph Number 2.2.5.1 2.2.5.2 2.2.5.3 2.2.6 2.2.6.1 2.2.6.2 2.2.6.3 2.2.6.4 2.2.6.5 2.2.6.6 2.2.7 2.2.7.1 2.2.7.2 2.2.7.3 2.2.7.4 2.2.7.5 2.2.7.6 2.2.7.7 2.2.7.8 2.2.7.9 2.2.7.10 2.2.7.11 2.2.7.12 2.2.7.13 2.2.7.14 2.2.8 2.2.8.1 2.2.8.2 2.2.8.3 2.2.8.4 2.2.8.5 2.2.9 2.2.9.1 2.2.9.2 2.2.9.3 2.2.9.4 2.2.9.5 2.2.9.6 2.2.10 2.2.10.1 2.2.10.2 Title Page Number Reset In (RSTI) .....................................................................................................
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Contents Paragraph Number 2.2.11 2.2.11.1 2.2.11.2 2.2.12 2.2.12.1 2.2.12.2 2.2.12.3 2.2.12.4 2.2.13 2.2.13.1 2.2.13.2 2.2.14 2.2.14.1 2.2.14.2 2.2.15 2.2.15.1 2.2.15.2 2.2.15.3 2.2.15.4 2.2.15.5 2.2.15.6 2.2.15.7 2.2.16 2.2.16.1 2.2.17 2.2.17.1 2.2.17.2 2.2.17.3 2.2.17.4 2.2.17.5 2.2.17.6 2.2.17.7 2.2.17.8 2.2.17.9 2.2.17.10 2.2.17.11 Title Page Number I2C I/O Signals .......................................................................................................... 2-27 Serial Clock (SCL) ......
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Contents Paragraph Number Title Page Number Chapter 3 ColdFire Core 3.1 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.2 3.3.2.1 3.3.2.2 3.3.3 3.3.4 3.3.5 3.3.5.1 3.3.5.2 3.3.5.3 3.3.5.4 3.3.5.5 3.3.5.6 3.3.6 3.4 3.4.1 3.4.1.1 3.4.1.2 3.4.2 3.4.2.1 3.5 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.3 Core Overview ................................................................................................................ 3-1 Features ......................................................
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Contents Paragraph Number 3.7.4 3.7.5 3.7.6 3.7.7 3.8 3.8.1 3.8.2 3.9 Title Page Number Miscellaneous Instruction Execution Timing ........................................................... 3-32 Branch Instruction Execution Timing ....................................................................... 3-33 EMAC Instruction Execution Times ........................................................................ 3-34 FPU Instruction Execution Times .........................................................
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Contents Paragraph Number 5.2.3.9 5.2.3.10 5.2.3.11 5.3 5.4 5.4.1 5.4.2 5.4.3 5.5 5.5.1 5.5.2 5.5.3 5.5.3.1 5.5.3.2 5.5.3.3 5.5.3.4 5.5.3.5 5.5.3.6 5.5.3.7 5.5.4 5.5.5 5.6 5.6.1 5.6.2 5.6.3 5.7 Title Page Number Changes to ACRs and CACR ................................................................................. 5-5 ACR Address Improvements .................................................................................. 5-6 Supervisor Protection ....................................................
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Contents Paragraph Number 6.2.3.5 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.1.3 6.6.1.4 6.6.1.5 6.6.1.6 6.6.1.7 6.6.1.8 6.6.2 6.7 6.7.1 6.7.2 6.7.3 Title Page Number Denormalized Numbers .......................................................................................... 6-5 Register Definition .......................................................................................................... 6-7 Floating-Point Data Registers (FP0–FP7) ........
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Contents Paragraph Number 7.8.1 7.8.2 7.9 7.9.1 7.9.1.1 7.9.1.2 7.9.2 7.9.2.1 7.9.2.2 7.9.2.3 7.9.2.4 7.9.3 7.9.4 7.9.4.1 7.9.4.2 7.9.5 7.10 7.10.1 7.10.2 7.11 7.12 7.12.1 7.12.2 7.13 Title Page Number Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8 The Cache at Start-Up ................................................................................................. 7-8 Cache Operation ........................................................................
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Contents Paragraph Number 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 8.4.11.1 8.5 8.5.1 8.5.2 8.5.2.1 8.5.2.2 8.5.3 8.5.3.1 8.5.3.2 8.5.3.3 8.6 8.6.1 8.6.1.1 8.6.2 8.7 8.7.1 8.7.2 8.8 8.8.1 8.8.2 8.8.3 8.8.3.1 8.9 Title Page Number Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16 Trigger Definition Register (TDR) ........................................................................... 8-17 Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ..
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Contents Paragraph Number 9.3.1.4 Title Page Number JTAG Device Identification Number (JTAGID) .................................................... 9-5 Chapter 10 Internal Clocks and Bus Architecture 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.6.1 10.1.6.2 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.3.2.1 10.3.2.2 10.3.2.3 10.3.3 10.3.3.1 10.3.3.2 10.3.3.3 10.3.3.4 10.3.3.5 10.3.3.6 10.3.3.7 10.3.3.8 10.3.3.9 10.3.3.10 10.3.3.11 Introduction ........................................................
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Contents Paragraph Number 11.1.1 11.1.2 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 Title Page Number Overview ................................................................................................................... 11-1 Modes of Operation .................................................................................................. 11-1 External Signals ............................................................................................................
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Contents Paragraph Number Title Page Number Chapter 14 Edge Port Module (EPORT) 14.1 14.2 14.3 14.3.1 14.3.2 14.3.2.1 14.3.2.2 14.3.2.3 14.3.2.4 14.3.2.5 14.3.2.6 Introduction ................................................................................................................... 14-1 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1 Memory Map/Register Definition ....................................................................
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Contents Paragraph Number 15.4 15.4.1 Title Page Number Functional Description ................................................................................................ 15-32 Overview ................................................................................................................. 15-32 Chapter 16 32-Kbyte System SRAM 16.1 16.1.1 16.1.2 16.1.3 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.3 Introduction ................................................................................
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Contents Paragraph Number 17.5.1.2 17.5.2 17.5.2.1 17.5.2.2 17.5.2.3 17.6 17.6.1 17.6.2 17.6.3 17.6.4 17.6.4.1 17.6.5 17.6.5.1 17.6.5.2 17.6.5.3 17.6.5.4 17.6.6 17.6.7 17.6.8 Title Page Number Global Chip-Select Operation ............................................................................... 17-6 Chip-Select Registers ................................................................................................ 17-7 Chip-Select Address Registers (CSAR0–CSAR5) ..................................
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Contents Paragraph Number 18.3.13 18.3.14 18.3.15 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.5.1 18.5 18.5.1 18.5.1.1 18.5.1.2 18.5.1.3 18.5.1.4 18.5.1.5 18.5.1.6 18.5.1.7 18.5.2 18.5.2.1 18.5.2.2 18.6 18.6.1 18.6.2 18.7 18.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 18.8 18.8.1 18.8.2 18.8.3 18.8.4 18.8.5 18.8.6 18.8.7 18.8.8 Title Page Number SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4 SDRAM Memory Supply (SDVDD) ................................
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Contents Paragraph Number 18.8.9 18.8.10 18.8.11 18.8.12 Title Page Number Perform Two Refresh Cycles .................................................................................. 18-31 Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32 Enable Automatic Refresh and Lock Mode Register ............................................ 18-33 Initialization Code .............................................................................................
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Contents Paragraph Number 19.3.2.2 19.3.2.3 19.3.2.4 19.3.2.5 19.3.2.6 19.3.2.7 19.3.2.8 19.3.2.9 19.3.2.10 19.3.2.11 19.3.3 19.3.3.1 19.3.3.2 19.4 19.4.1 19.4.1.1 19.4.1.2 19.4.1.3 19.4.1.4 19.4.1.5 19.4.2 19.4.2.1 19.4.3 19.4.4 19.4.4.1 19.4.4.2 19.4.4.3 19.4.4.4 19.4.4.5 19.4.5 19.4.5.1 19.4.5.2 19.4.5.3 19.4.5.4 19.4.5.5 19.4.6 19.4.6.1 19.4.6.2 19.4.6.3 19.4.6.4 19.4.6.5 Title Page Number Target Base Address Translation Register 0 (PCITBATR0) .............................
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Contents Paragraph Number 19.4.6.6 19.4.6.7 19.4.6.8 19.4.6.9 19.4.7 19.4.8 19.4.8.1 19.4.8.2 19.5 19.5.1 19.5.2 19.5.2.1 19.6 Title Page Number PCI Commands ................................................................................................... 19-69 FIFO Considerations ........................................................................................... 19-69 Alarms .................................................................................................................
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Contents Paragraph Number 20.6 Title Page Number Interrupts ..................................................................................................................... 20-10 Chapter 21 FlexCAN 21.1 21.1.1 21.1.2 21.1.3 21.1.4 21.1.4.1 21.1.4.2 21.1.4.3 21.1.4.4 21.1.4.5 21.2 21.2.1 21.2.2 21.3 21.3.1 21.3.2 21.3.2.1 21.3.2.2 21.3.2.3 21.3.2.4 21.3.2.5 21.3.2.6 21.3.2.7 21.3.2.8 21.4 21.4.1 21.4.2 21.4.3 21.4.4 21.4.5 21.4.5.1 21.4.6 21.4.6.1 21.4.6.2 21.4.6.3 21.4.6.4 Introduction ...........
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Contents Paragraph Number 21.4.7 21.4.7.1 21.4.7.2 21.4.8 21.4.9 21.4.9.1 21.4.10 21.5 21.5.1 Title Page Number CAN Protocol Related Frames ............................................................................... 21-27 Remote Frames ................................................................................................... 21-27 Overload Frames ................................................................................................. 21-28 Time Stamp ................................
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Contents Paragraph Number 22.6.4.8 22.7 22.7.1 22.7.1.1 22.7.1.2 22.7.1.3 22.7.1.4 22.7.1.5 22.8 22.8.1 22.8.2 22.8.3 22.8.4 22.8.5 22.9 22.9.1 22.9.2 22.9.3 22.9.4 22.9.5 22.10 22.10.1 22.10.2 22.10.3 22.10.4 22.10.5 22.11 22.11.1 22.11.2 22.11.3 22.11.4 22.11.5 22.12 22.12.1 22.12.2 22.12.3 22.12.4 22.12.5 22.13 22.13.1 22.13.1.1 Title Page Number Master Error Address Register (MEAR) ............................................................ 22-18 Channels ............................................
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Contents Paragraph Number 22.13.1.2 22.13.1.3 22.13.1.4 22.13.2 22.13.3 22.13.4 22.13.4.1 22.13.4.2 22.14 22.14.1 22.14.1.1 22.14.1.2 22.14.2 22.14.2.1 22.14.2.2 22.14.3 22.14.3.1 22.14.3.2 22.14.3.3 22.14.4 22.14.5 22.14.5.1 22.14.5.2 22.14.5.3 22.14.6 22.14.6.1 22.14.6.2 22.14.6.3 22.14.6.4 Title Page Number Descriptor Length and Pointer Fields ................................................................. 22-60 Null Fields ............................................................................
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Contents Paragraph Number 23.2.1.3 23.2.1.4 23.2.1.5 23.2.1.6 23.3 23.3.1 23.3.2 23.3.2.1 23.3.2.2 23.3.2.3 23.3.2.4 23.3.2.5 23.3.2.6 23.4 23.4.1 23.4.2 23.4.3 23.4.3.1 23.4.3.2 23.4.3.3 23.4.3.4 23.4.3.5 23.4.3.6 23.4.3.7 23.5 23.5.1 23.5.2 Title Page Number Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3 Test Data Input/Development Serial Input (TDI/DSI) .........................................
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Contents Paragraph Number 24.2.1 24.2.2 24.3 24.3.1 24.3.1.1 24.3.1.2 24.3.1.3 24.3.1.4 24.3.1.5 24.3.2 24.3.3 24.3.3.1 24.3.3.2 24.3.3.3 24.3.3.4 24.3.3.5 24.3.3.6 24.3.3.7 24.3.3.8 24.3.3.9 24.3.3.10 24.3.3.11 24.3.3.12 24.3.3.13 24.3.3.14 24.3.3.15 24.3.3.16 24.3.4 24.3.4.1 24.3.4.2 24.3.4.3 24.3.4.4 24.4 24.4.1 24.4.2 24.4.3 24.4.4 24.4.5 24.4.6 24.4.7 24.4.8 Title Page Number DREQ[1:0] ...............................................................................................................
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Contents Paragraph Number 24.4.8.1 24.4.9 24.4.9.1 24.4.9.2 24.4.9.3 24.4.10 24.4.11 24.4.12 24.5 24.5.1 24.5.2 24.5.2.1 24.6 24.6.1 24.6.2 24.6.3 Title Page Number LURC Features ................................................................................................... 24-25 Line Buffers ............................................................................................................ 24-26 Combine Write Enable ...........................................................................
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Contents Paragraph Number 26.1.1 26.1.2 26.1.3 26.1.4 26.2 26.2.1 26.2.2 26.2.3 26.2.4 26.2.5 26.3 26.3.1 26.3.2 26.3.3 26.3.3.1 26.3.3.2 26.3.3.3 26.3.3.4 26.3.3.5 26.3.3.6 26.3.3.7 26.3.3.8 26.3.3.9 26.3.3.10 26.3.3.11 26.3.3.12 26.3.3.13 26.3.3.14 26.3.3.15 26.3.3.16 26.3.3.17 26.3.3.18 26.3.3.19 26.3.3.20 26.3.3.21 26.3.3.22 26.3.3.23 26.3.3.24 26.3.3.25 26.3.3.26 26.3.3.27 Title Page Number Block Diagram ................................................................................................
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Contents Paragraph Number 26.3.3.28 26.3.3.29 26.4 26.4.1 26.4.2 26.4.3 26.4.4 26.4.5 26.4.5.1 26.4.5.2 26.4.5.3 26.4.6 26.4.7 26.4.7.1 26.4.7.2 26.4.8 26.4.8.1 26.4.9 26.4.9.1 26.4.9.2 26.4.10 26.4.10.1 26.4.10.2 26.4.10.3 26.5 26.5.1 26.5.2 26.5.2.1 26.5.2.2 26.5.2.3 26.5.2.4 26.6 26.6.1 26.6.1.1 26.7 26.7.1 26.7.2 26.7.2.1 26.7.2.2 26.7.2.3 26.7.2.4 Title Page Number Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) .........
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Contents Paragraph Number 26.7.2.5 26.7.2.6 26.7.2.7 26.7.3 26.7.3.1 26.7.3.2 Title Page Number SIR Mode ............................................................................................................ 26-52 MIR Mode .......................................................................................................... 26-53 FIR Mode ............................................................................................................ 26-54 Programming ...............................
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Contents Paragraph Number 27.7.2.4 27.7.2.5 27.7.3 27.7.3.1 27.7.3.2 27.7.3.3 27.7.3.4 27.7.3.5 27.7.4 27.7.4.1 27.7.4.2 27.7.4.3 27.7.4.4 27.7.4.5 27.7.5 27.7.6 27.7.6.1 27.7.6.2 27.7.6.3 27.7.6.4 27.7.6.5 27.7.6.6 27.8 27.8.1 27.8.2 27.8.3 27.8.4 27.8.4.1 27.8.4.2 Title Page Number Tx FIFO Buffering Mechanism .......................................................................... 27-21 Rx FIFO Buffering Mechanism ..........................................................................
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Contents Paragraph Number 28.3.2.1 28.3.2.2 28.3.2.3 28.3.2.4 28.3.2.5 28.3.2.6 28.4 28.4.1 28.4.2 28.4.3 28.4.4 28.4.5 28.4.6 28.4.7 28.4.8 28.5 28.5.1 28.5.2 28.5.3 28.5.4 28.5.5 28.5.6 28.5.7 Title Page Number I2C Address Register (I2ADR) ............................................................................. 28-3 I2C Frequency Divider Register (I2FDR) ............................................................ 28-4 I2C Control Register (I2CR) ...................................................
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Contents Paragraph Number 29.2.2.3 29.2.2.4 29.2.2.5 29.2.2.6 29.2.2.7 29.2.2.8 29.2.2.9 29.2.2.10 29.2.2.11 29.2.2.12 29.2.2.13 29.2.2.14 29.2.2.15 29.2.2.16 29.2.3 29.2.3.1 29.2.3.2 29.2.3.3 29.2.3.4 29.2.3.5 29.2.3.6 29.2.3.7 29.2.3.8 29.2.4 29.2.4.1 29.2.4.2 29.2.4.3 29.2.4.4 29.2.4.5 29.2.4.6 29.2.4.7 29.2.4.8 29.2.4.9 29.2.4.10 29.2.5 29.2.5.1 29.2.5.2 29.2.5.3 29.2.5.4 29.2.5.5 Title Page Number USB Descriptor RAM Control Register (DRAMCR) ........................................
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Contents Paragraph Number 29.2.5.6 29.2.5.7 29.2.5.8 29.2.5.9 29.2.5.10 29.2.5.11 29.2.5.12 29.3 29.3.1 29.4 29.4.1 29.4.1.1 29.4.1.2 29.4.1.3 29.4.1.4 29.4.1.5 29.4.2 29.4.2.1 29.4.2.2 29.4.3 29.4.3.1 29.4.3.2 29.4.3.3 29.4.3.4 29.4.3.5 29.4.3.6 29.4.3.7 29.4.3.8 Title Page Number USB Endpoint n FIFO Status Register (EPnFSR) ............................................. 29-40 USB Endpoint n FIFO Control Register (EPnFCR) ...........................................
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Contents Paragraph Number 30.1.5.4 30.2 30.2.1 30.2.2 30.2.3 30.2.4 30.2.5 30.2.6 30.2.7 30.2.8 30.2.9 30.2.10 30.2.11 30.2.12 30.3 30.3.1 30.3.2 30.3.3 30.3.3.1 30.3.3.2 30.3.3.3 30.3.3.4 30.3.3.5 30.3.3.6 30.3.3.7 30.3.3.8 30.3.3.9 30.3.3.10 30.3.3.11 30.3.3.12 30.3.3.13 30.3.3.14 30.3.3.15 30.3.3.16 30.3.3.17 30.3.3.18 30.3.3.19 30.3.3.20 30.3.3.21 30.3.3.22 30.3.3.23 Title Page Number Internal Loopback .................................................................................................
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Contents Paragraph Number 30.3.3.24 30.3.3.25 30.3.3.26 30.3.3.27 30.3.3.28 30.3.3.29 30.3.3.30 30.3.3.31 30.3.3.32 30.3.3.33 30.3.3.34 30.3.3.35 30.4 30.4.1 30.4.1.1 30.4.1.2 30.4.2 30.4.2.1 30.4.2.2 30.4.3 30.4.4 30.4.5 30.4.6 30.4.7 30.4.8 30.4.9 30.4.10 30.4.11 30.4.12 30.4.12.1 30.4.12.2 30.4.13 30.4.14 Title Page Number FEC Receive FIFO Read Pointer Register (FECRFRP) ..................................... 30-32 FEC Receive FIFO Write Pointer Register (FECRFWP) ...................................
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Contents Paragraph Number 31.3.2 31.4 31.5 31.6 Title Page Number MCF5483/5482 Mechanical Diagram .................................................................... 31-12 MCF5481/5480 Mechanical Diagram ........................................................................ 31-16 Mechanicals 388-pin PBGA Package Outline ............................................................ 31-20 Case Drawing ........................................................................................................
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About This Book The primary objective of this reference manual is to define the functionality of the MCF548x processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation.
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• • — Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e local memory specification. — Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions.
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Suggested Reading • • — Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network (CAN) protocol. This chapter describes FlexCAN module operation and provides a programming model. — Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x security encryption controller. — Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the MCF548x JTAG test implementation.
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General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general: • ColdFire Programmers Reference Manual (CFPRM) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson.
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Acronyms and Abbreviations longword x n ¬ & | A 32-bit data unit In some contexts, such as signal encodings, x indicates a don’t care. Used to express an undefined numerical value NOT logical operator AND logical operator OR logical operator Register Conventions This reference manual uses the register diagram format shown below.
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Table ii. .
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Terminology and Notational Conventions Table ii. . Acronyms and Abbreviated Terms (continued) Term Meaning UART Universal asynchronous/synchronous receiver transmitter XLB bus Internal 64-bit bus Terminology and Notational Conventions Table iii shows notational conventions used throughout this document. Table iii.
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Table iii.
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Terminology and Notational Conventions Table iii. Notational Conventions (continued) Instruction Address Operand Syntax Calculated effective address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero Table iv.
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Table iv. MCF548x Revision History (continued) Section/Page Substantive Changes Table 2-1/2-3 Add column to indicate whether the signal has a pull-up resistor.
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Terminology and Notational Conventions Table iv. MCF548x Revision History (continued) Section/Page 2.2.6.1/2-22 Substantive Changes Add the following after Table 2-4: Figure 1 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers. Internal Clock CLKIN Core Clock 2x 2x 25.0 50.0 50.0 100.0 100.0 200.0 2x 4x 25.0 100.0 200.
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Table iv. MCF548x Revision History (continued) Section/Page Substantive Changes 10.2/10-5 Insert the following section before section 10.2 “XL Bus Arbiter”. 10.2 PLL 10.2.1 PLL Memory Map/Register Descriptions Table 2. System PLL Memory Map MBAR Offset Name Byte0 0x300 System PLL Control Register Byte1 Byte2 Byte3 Access SPCR R/W 10.2.2 System PLL Control Register (SPCR) The system PLL control register (SPCR) defines the clock enables used to control clocks to a set of peripherals.
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Terminology and Notational Conventions Table iv. MCF548x Revision History (continued) Section/Page Substantive Changes Table 10-3/10-5 Bits BA, DT, and AT: The 0 and 1 are switched. Setting each bit enables operation, while clearing disables operation. The 0 and 1 (or the corresponding descriptions) need to be swapped for all three bits. 11.4.2/11-8 Remove all text from bullet item #2 starting with “This scenario works for all pulses except....” This errata does not apply to this processor. 13.1.
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Table iv. MCF548x Revision History (continued) Section/Page Substantive Changes 21.4.9/21-28 Add the following table below the note at the end of the section and correct the cross-reference pointing to it: Table 21-19. CAN Standard Compliant Bit Time Segment Settings Table 23-5/23-7 Time Segment 1 Time Segment 2 Re-synchronization Jump Width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 ..
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Terminology and Notational Conventions Table iv. MCF548x Revision History (continued) Section/Page 25.1.2/25-2 Substantive Changes Add the following section after section 24.1.2: 24.1.3 Comm Timer External Clock[7:0] The comm timer external clock is the alternate clock signal and is provided by the user. The user must write a 1 to CTCR[S] in the variable channel and write a 1001 to CTCR[S] within the fixed channel to select this signal.
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Table iv. MCF548x Revision History (continued) Section/Page 27.6.1/27-5 Substantive Changes Remove instances of MDIS bit as it is not present on this version of the DSPI. Table 29-3/29-11 USBCR[APPLOCK] bit description, the bit setting numbers are incorrrect. When cleared (0), APPLOCK is deasserted. When set (1), APPLOCK is asserted. Table 29-29/29-30 Endpoint status register’s PSTALL entry: the last sentence should be “Setting this bit also sets USBAISR[EPSTALL].
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Terminology and Notational Conventions Table iv. MCF548x Revision History (continued) Section/Page Substantive Changes Figure 31-3/Page 31-10 Remove overbar from ALE at location AD6. Figure 31-7/Page 31-14 Remove overbar from ALE at location AD6. Figure 31-11/Page 31-18 Remove overbar from ALE at location AD6. MCF548x Reference Manual, Rev.
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MCF548x Reference Manual, Rev.
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Chapter 1 Overview This chapter provides an overview of the MCF548x microprocessor features, including the major functional components. 1.1 MCF548x Family Overview The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4 central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit (MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers for caches and local data memories.
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With on-chip support for multiple common communications interfaces, MCF548x products require only the addition of memories and certain physical layer transceivers to be cost-effective system solutions for many applications. Such applications include industrial routers, high-end POS terminals, building automation systems, and process control equipment. MCF548x products require four supply voltages: 1.5V for the high-performance, low power, internal core logic, 2.5V for the DDR SDRAM bus interface, 1.
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MCF548x Family Products 1.3 MCF548x Family Products Table 1-1 summarizes the products available within the MCF548x product family. All products are available in pin-compatible, 388-pin PBGA packaging allowing for ease of migration between products within the family. A printed circuit board designed using the MCF5485/4 footprint is compatible with any of the MCF548x family devices. Table 1-1. MCF548x Family Products 1.
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• • • • • • — Memory management unit (MMU) – Separate, 32-entry, fully-associative instruction and data translation lookahead buffers — Floating point unit (FPU) – Double-precision support that conforms to IEEE-754 standard – Eight floating point registers Internal master bus (XLB) arbiter — High performance split address and data transactions — Support for various parking modes 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller — 66–133 MHz operation — Supports both DDR and SDR DRAM —
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MCF548x Family Features • • • • • • 1.4.
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The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE) Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit, double-precision floating point data and supports single-precision and signed integer input operands. The FPU programming model is like that in the MC68060 microprocessor.
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MCF548x Family Features boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.
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1.4.6 1.4.6.1 Communications I/O Subsystem DMA Controller The communications subsystem contains an intelligent DMA unit that provides front line interrupt control and data movement interface via a separate peripheral bus to the on-chip peripheral functions, leaving the processor core free to handle higher level activities. This concurrent operation enables a significant boost in overall system performance.
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MCF548x Family Features • 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM 1.4.6.
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• DMA support 1.4.6.7 Controller Area Network (CAN) The FlexCAN modules are communication controllers implementing the CAN protocol. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time processing and reliable operation in a harsh EMI environment, while maintaining cost-effectiveness. Each of the two CAN controllers on the MCF548x family products contains sixteen message buffers.
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MCF548x Family Features frequency from 33–66 MHz. The Flexbus is targeted to support external Flash memories, boot ROMs, gate-array logic, or other simple target interfaces. Up to six chip selects are supported by the FlexBus.
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1.4.11.2 Interrupt Controller The interrupt controller on the MCF548x family can support up to 63 interrupt sources. The interrupt controller is organized as seven levels with nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level.
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Chapter 2 Signal Descriptions 2.1 Introduction This chapter describes the MCF548x signals. NOTE The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term ‘asserted’ indicates that a signal is active, independent of the voltage level. The term ‘negated’ indicates that a signal is inactive. Active-low signals, such as RAS and TA, are indicated with an overbar. 2.1.
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FlexBus AD[31:24] AD[23:16] AD15:8] AD[7:0] FBCS[5:1] / PFBCS[5:1] FBCS0 ALE / PFBCTL0 / TBST R/W / PFBCTL2 / TBST BE/BWE3 / PFBCTL7 / TSIZ1 BE/BWE2 / PFBCTL6 / TSIZ0 BE/BWE1 / PFBCTL5 / FBADDR1 BE/BWE0 / PFBCTL4 / FBADDR0 OE / PFBCTL3 TA / PFBCTL1 SDRAM Controller SDDATA[31:24] SDDATA[23:16] SDDATA[15:8] SDDATA[7:0] SDADDR[12:0] SDBA[1:0] RAS CAS SDCS[3:0] SDDM[3:0] SDDQS[3:0] SDCLK[1:0] SDCLK[1:0] SDWE SDCKE SDRDQS VREF PCI Controller PSCs DSPI PCIAD[31:24] / FBADDR[31:24] PCIAD[23:16] / FBADDR[23:
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Introduction Table 2-1 lists the signals for the MCF548x in functional group order. Drive Reset State Pin Functions Pull-up Table 2-1.
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Description I/O Drive Reset State Pin Functions Pull-up Table 2-1.
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Introduction Description I/O Drive Reset State Pin Functions Pull-up Table 2-1.
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Description I/O Drive Reset State Pin Functions Pull-up Table 2-1.
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Introduction Description I/O Drive Reset State Pin Functions Pull-up Table 2-1.
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Drive Reset State Pin Functions Pull-up Table 2-1.
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Introduction Drive Reset State Pin Functions Pull-up Table 2-1.
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AD164 AE18 I/O GPIO Secondary Tertiary USB_PLLVDD — — — USB PLL supply USBVDD — — — USB supply 4 Reset State Description Primary Drive Pin Functions PBGA Pin Pull-up Table 2-1. MCF548x Signal Description (Continued) 1 Pull-up resistor when configured for general purpose input (default state after reset). This pin is a “no connect” on the MCF5483 and MCF5482 devices. 3 This pin is a “no connect” on the MCF5481 and MCF5480 devices.
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Introduction Pin Functions Primary GPIO Secondary Tertiary A21 PSTDDATA1 — — — A22 PSTDDATA3 — — A23 PSTDDATA7 — A24 PCIBR0 A25 PBGA Pin PBGA Pin Table 2-2.
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Pin Functions Primary GPIO Secondary Tertiary B261 E1RXD2 PFEC1L2 — — C1 SDVDD — — C2 CAS — C3 VSS C4 PBGA Pin PBGA Pin Table 2-2.
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Introduction Pin Functions Primary GPIO Secondary Tertiary D5 SDDATA28 — — — D6 VSS — — D7 SDADDR2 — D8 SDADDR6 D9 PBGA Pin PBGA Pin Table 2-2.
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Pin Functions Primary GPIO Secondary Tertiary F2 SDDQS1 — — — F3 SDVDD — — F4 VSS — F23 PCIPAR F24 PBGA Pin PBGA Pin Table 2-2.
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Introduction Pin Functions Primary GPIO Secondary Tertiary K1 SDWE — — — K2 SDDATA0 — — K3 SDDATA1 — K4 SDDATA11 K23 PBGA Pin PBGA Pin Table 2-2.
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PBGA Pin PBGA Pin Table 2-2.
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MCF548x External Signals 2.2.1.2 Chip Select (FBCS[5:0]) FBCS[5:0] are asserted to indicate which device is being selected. A particular chip select asserts when the transfer address is within the device’s address space as defined in the base and mask address registers. Each chip select can be programmed for a base address location, masking addresses, port size, burst-capability indication, wait-state generation, and internal/external termination.
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Table 2-3. Data Transfer Size (Continued) TSIZ[1:0] Transfer Size 10 2 bytes (word) 11 16 bytes (line) For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers.
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MCF548x External Signals 2.2.2.3 SDRAM Bank Addresses (SDBA[1:0]) Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank. It is also used to select the SDRAM internal mode register during power-up initialization. 2.2.2.4 SDRAM Row Address Strobe (RAS) This output is the SDRAM synchronous row address strobe. 2.2.2.5 SDRAM Column Address Strobe (CAS) This output is the SDRAM synchronous column address strobe. 2.2.2.
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2.2.2.14 SDRAM Reference Voltage (VREF) This is the input reference voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes. 2.2.3 2.2.3.1 PCI Controller Signals PCI Address/Data Bus (PCIAD[31:0]) The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during the address phase while the data is presented on the bus during one or more data phases.
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MCF548x External Signals 2.2.3.9 Reset (PCIRESET) The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after the MCF548x is reset and must be negated to enable usage of the PCI bus. 2.2.3.10 System Error (PCISERR) The PCISERR signal, if enabled, is asserted when an address phase parity error is detected. 2.2.3.11 Stop (PCISTOP) The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the current transaction.
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2.2.5 Clock and Reset Signals The clock and reset signals configure the MCF548x and provide interface signals to the external system. 2.2.5.1 Reset In (RSTI) Asserting RSTI causes the MCF548x to enter reset exception processing. RSTO is asserted automatically when RSTI is asserted. 2.2.5.2 Reset Out (RSTO) After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the PLL regains its lock, RSTO negates again.
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MCF548x External Signals CLKIN Internal Clock Core Clock 2x 2x 25.0 50.0 50.0 100.0 100.0 200.0 2x 4x 25.0 100.0 200.0 25 40 50 60 70 30 40 50 60 70 80 90 100 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 CLKIN (MHz) Internal Clock (MHz) Core Clock (MHz) Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios 2.2.6.
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Table 2-7. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration AD3 2.2.6.5 Boot FBCS0 Byte Strobe Configuration 0 BE[3:0] can assert for both read and write cycles. 1 BWE[3:0] are not asserted for reads; BWE[3:0] only assert for write cycles AD2—Auto Acknowledge Configuration (AACONFIG) At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.
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MCF548x External Signals 2.2.7.2 Management Data Clock (E0MDC, E1MDC) EMDC is an output clock that provides a timing reference to the PHY for data transfers on the EMDIO signal; it applies to MII mode operation. 2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK) This is an input clock that provides a timing reference for ETXEN, ETXD[3:0], and ETXER. 2.2.7.4 Transmit Enable (E0TXEN, E1TXEN) The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII.
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2.2.7.12 Transmit Error (E0TXER, E1TXER) When the ETXER output is asserted for one or more clock cycles while ETXEN is also asserted, the PHY sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies to MII mode operation. 2.2.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) These pins contain the Ethernet input data transferred from the PHY to the media-access controller when ERXDV is asserted in MII mode operation. 2.2.7.
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MCF548x External Signals 2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN) The DSPISIN input provides the serial data to the DSPI and can be programmed to be sampled on the rising or falling edge of DSPISCK. 2.2.9.3 DSPI Serial Clock (DSPISCK) DSPISCK is a serial communication clock signal. In master mode, the DSPI generates the DSPISCK. In slave mode, DSPISCK is an input from an external bus master. 2.2.9.
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2.2.11.1 Serial Clock (SCL) This bidirectional open-drain signal is the clock signal for the I2C interface. It is either driven by the I2C module when the bus is in master mode, or it becomes the clock input when the I2C is in slave mode. 2.2.11.2 Serial Data (SDA) This bidirectional open-drain signal is the data input/output for the I2C interface. 2.2.12 PSC Module Signals The PSC modules use the signals in this section. The baud rate clock inputs are not supported. 2.2.12.
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MCF548x External Signals 2.2.14 Timer Module Signals The signals in the following sections are external interfaces to the four general-purpose MCF548x timers. These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count external events. 2.2.14.1 Timer Inputs (TIN[3:0]) TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause captures on the rising edge, falling edge, or both edges. 2.2.14.
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2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS) If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode. If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state.
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MCF548x External Signals 2.2.17 Power and Reference Pins These pins provide system power, ground, and references to the device. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 2.2.17.1 Positive Pad Supply (EVDD) This pin supplies positive power to the I/O pads. 2.2.17.2 Positive Core Supply (IVDD) This pin supplies positive power to the core logic. 2.2.17.
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MCF548x Reference Manual, Rev.
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Part I Processor Core Part I is intended for system designers who need to understand the operation of the MCF548x ColdFire core and its enhanced multiply/accumulate (EMAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module. Contents Part 1 contains the following chapters: • Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the MCF548x.
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MCF548x Reference Manual, Rev.
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Chapter 3 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF548x. The CF4e implementation of the Version 4 (V4) core includes the floating-point unit (FPU), enhanced multiply-accumulate unit (EMAC), and memory management unit (MMU); all are defined as optional in the V4 architecture. This chapter also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 3.
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3.2.1 Enhanced Pipelines The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes the specified function. The two independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages are shown in Figure 3-1 and are summarized as follows: • Four-stage IFP (plus optional instruction buffer stage) — Instruction address generation (IAG) calculates the next prefetch address.
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Features Instruction Fetch Pipeline IAG Branch Cache Instruction Memory IC1 IC2 Branch Accel. IED IB Operand Execution Pipeline DS Internal Bus secDS OAG Data (Operand) Memory OC1 OC2 Misalignment Module EX DA Debug DSCLK DSI DSO DDATA PSTDDATA PSTCLK Figure 3-1. ColdFire Enhanced Pipeline 3.2.1.
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3.2.1.1.1 Branch Acceleration To maximize the performance of conditional branch instructions, the IFP implements a sophisticated two-level acceleration mechanism. The first level is an 8-entry, direct-mapped branch cache with 2 bits for indicating four prediction states (strongly or weakly; taken or not-taken) for each entry. The branch cache also provides the association between instruction addresses and the corresponding target address.
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Features ColdFire microprocessor family. The MAC features a four-stage execution pipeline, optimized for 32 × 32 multiplies. It is tightly coupled to the OEP, which can issue a 32 x 32 multiply with a 32-bit accumulation and fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires four cycles before the next instruction can be issued. Figure 3-2 shows basic functionality of the EMAC.
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The hardware unit is optimized for real-time execution with exceptions disabled and default results provided for specific operations, operands, and number types. The FPU does not support all IEEE-754 number types and operations in hardware. Exceptions can be enabled to support these cases in software. 3.2.1.2.
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Programming Model • • The ASID is optionally included in the specification of the hardware breakpoint registers. As an example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID value may be programmed as part of the breakpoint instruction address. Likewise, each operand address/data breakpoint register is expanded to include an ASID value. Finally, new control registers define if and how the ASID is to be included in the breakpoint comparison trigger logic.
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31 0 31 Data registers A0 A1 A2 A3 A4 A5 A6 A7 PC CCR Address registers User Registers 0 63 User stack pointer Program counter Condition code register 0 31 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FPCR FPSR FPIAR Floating-point data registers MACSR ACC0 ACC1 ACC2 ACC3 ACCext01 ACCext23 MASK MAC status register MAC accumulator 0 MAC accumulator 1 (EMAC only) MAC accumulator 2 (EMAC only) MAC accumulator 3 (EMAC only) ACC0 and ACC1 extensions ACC2 and ACC3 extensions MAC mask register Floating-point co
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Programming Model 3.3.1 User Programming Model The user programming model, shown in Figure 3-3, consists of the following registers: • 16 general-purpose, 32-bit registers (D7–D0 and A7–A0); A7 is a user stack pointer • 32-bit program counter • 8-bit condition code register • Registers to support the EMAC • Register to support the floating-point unit (FPU) 3.3.1.1 Data Registers (D0–D7) Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations.
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Table 3-1. CCR Field Descriptions 3.3.3 Bits Name Description 7–5 — Reserved, should be cleared. 4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic. 3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared.
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Programming Model • • • • Eight 64-bit floating-point data registers (FP0–FP7) One 32-bit floating-point control register (FPCR) One 32-bit floating-point status register (FPSR) One 32-bit floating-point instruction address register (FPIAR) Figure 3-6 shows the FPU programming model. 63 31 0 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FPCR FPSR FPIAR Floating-point data registers Floating-point control register Floating-point status register Floating-point instruction address register Figure 3-6.
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3.3.5.1 Status Register (SR) The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the entire SR; user software can read or write only SR[7–0], described in Section 3.3.2.2, “Condition Code Register (CCR).” The control bits indicate processor states—trace mode (T), supervisor or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.
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Programming Model 31 30 R 29 28 27 26 25 24 Exception vector table base address 23 22 21 20 1 19 18 17 16 0 0 0 0 W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 0x801 R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr 0x801 1 Written from a BDM serial command or from the CPU using the MOVEC instruction.
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Table 3-4.
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Data Format Summary Table 3-4.
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31 30 1 0 msb lsb 31 8 Not used 31 msb 6 1 0 msb Lower-order byte lsb 16 Not used 31 7 15 msb 14 1 Byte (8 bits) 0 Lower-order word 30 Bit (0 bit number 31) lsb 1 Word (16 bits) 0 Longword lsb Longword (32 bits) Figure 3-9. Organization of Integer Data Format in Data Registers Instruction encodings disallow use of address registers for byte operands.
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Data Format Summary 31 24 23 16 15 8 7 0 Longword 0x0000_0000 . . . Word 0x0000_0000 Word 0x0000_0002 Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003 Longword 0x0000_0004 Word 0x0000_0004 Word 0x0000_0006 Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007 . . . Longword 0xFFFF_FFFC Word 0xFFFF_FFFC Word 0xFFFF_FFFE Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF . . . Figure 3-11. Memory Operand Addressing 3.4.
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3.4.2.1.1 Signed-Integer Data Formats The FPU supports 8-bit byte (B), 16-bit word (W), and 32-bit longword (L) integer data formats. 3.4.2.1.2 Floating-Point Data Formats Figure 3-13 shows the two binary floating-point data formats. 31 S 63 S 62 30 22 8-Bit Exponent Sign of Mantissa 51 11-Bit Exponent 52-Bit Fraction 0 23-Bit Fraction Single 0 Double Sign of Mantissa Figure 3-13.
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Instruction Set Summary Table 3-6. ColdFire Effective Addressing Modes Addressing Modes Mode Field Reg. Field Dn An 000 001 (An) (An)+ –(An) (d16, An) Syntax Category Data Memory Control Alterable reg. no. reg. no. X — — — — — X X 010 011 100 101 reg. no. reg. no. reg. no. reg. no. X X X X X X X X X — — X X X X X (d8, An, Xi*SF) 110 reg. no.
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• • Enhanced support for byte and word-sized operands through new move operations Enhanced support for position-independent code For descriptions of the ColdFire instruction set, see the latest version of the ColdFire Programmer’s Reference Manual. The following list summarizes new and enhanced instructions of ISA_B: • New instructions: — INTOUCH loads blocks of instructions to be locked in the instruction cache. — MOV3Q.L moves 3-bit immediate data to the destination location.
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Instruction Set Summary Table 3-7. V4 New Instruction Summary (Continued) Mnemonic1 Source Destination M68000 move.l Ay USP Yes Move with Sign Extend mvs.{b,w} y Dx Move with Zero-Fill mvz.{b,w} y Dx Instruction Move to USP Signed Saturate sats.l Dx Test and Set an Operand tas.b x Yes EMAC Extensions Move from an Accumulator and Clear movclr.l ACCx Rx No Copy an Accumulator move.l ACCy ACCx No Move from Accumulator 0 and 1 Extensions move.
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Table 3-7. V4 New Instruction Summary (Continued) Mnemonic1 Instruction Save Internal Floating Point State Source Destination M68000 x Yes fsave Floating-Point Square Root fsqrt.{b,w,l,s,d} y FPx Yes Floating-Point Subtract fsub.{b,w,l,s,d} y FPx Yes Test Floating-Point Operand ftst.{b,w,l,s,d} y 1 Yes Operand sizes in this column reflect only newly supported operand sizes for existing instructions (Bcc, BRA, BSR, CMP, CMPA, CMPI, and MOVE) 3.6.
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Instruction Set Summary Table 3-8.
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Table 3-8.
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Instruction Set Summary Table 3-8.
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Table 3-8.
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Instruction Execution Timing Table 3-9. Supervisor-Mode Instruction Set Summary 3.
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• The OEP can complete all memory accesses without memory causing any stalls. Thus, these timings assume an infinite, zero-wait state memory attached to the core. Operand accesses are assumed to be aligned as follows: — 16-bit operands are aligned on 0-modulo-2 addresses — 32-bit operands are aligned on 0-modulo-4 addresses Operands that do not meet these guidelines are misaligned. Table 3-10 shows how the core decomposes a misaligned operand reference into a series of aligned accesses. • Table 3-10.
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Instruction Execution Timing Table 3-11. Move Byte and Word Execution Times (Continued) Destination Source Rx (Ax) (Ax)+ –(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl (Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -(Ay) 1(1/0) 21/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — — (xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (xxx).
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Table 3-13. MAC and Miscellaneous Move Execution Times Effective Address Opcode Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # move.l ,ACC 1(0/0) — — — — — — 1(0/0) move.l ,MACSR 6(0/0) — — — — — — 6(0/0) move.l ,MASK 5(0/0) — — — — — — 5(0/0) move.l ACC,Rx 1(0/0) — — — — — — — move.l MACSR,CCR 1(0/0) — — — — — — — move.l MACSR,Rx 1(0/0) — — — — — — — move.
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Instruction Execution Timing 3.7.3 Two-Operand Instruction Execution Timing Table 3-15 shows standard timings for double operand instructions. Table 3-15. Two-Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # add.l ,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) add.l Dy, — 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) — addi.l #imm,Dx 1(0/0) — — — — — — — addq.
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Table 3-15. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # lsr.l ,Dx 1(0/0) — — — — — — 1(0/0) mac.w Ry,Rx 1(0/0) — — — — — — — mac.l Ry,Rx 3(0/0) — — — — — — — msac.w Ry,Rx 1(0/0) — — — — — — — msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 1(1/0) 1(1/0) 1(1/0) 1(1/0) — — — mac.
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Instruction Execution Timing Table 3-16. Miscellaneous Instruction Execution Times (Continued) Effective Address Opcode Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # move.w SR,Dx 1(0/0) — — — — — — — move.w ,SR 4(0/0) — — — — — — 4(0/0) movec Ry,Rc 20(0/1) — — — — — — — movem.l 1 ,&list — n(n/0) — — n(n/0) — — — movem.
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2 If predicted correctly by the hardware return stack. If mispredicted by the hardware return stack. 4 If not predicted by the hardware return stack. 3 Table 3-18 shows timing for Bcc instructions. Table 3-18. Bcc Instruction Execution Times Opcode Branch Cache Correctly Predicts Taken Prediction Table Correctly Predicts Taken Predicted Correctly as Not Taken 0(0/0) 1(0/0) 1(0/0) bcc 3.7.
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Instruction Execution Timing Table 3-19. EMAC Instruction Execution Times Effective Address Opcode y Rn (An) (An)+ –(An) (d16,An) (d16,PC) (d8,An,Xi*SF) (d8,PC,Xi*SF) xxx.wl #xxx mulu.l y,Dx 4(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) — — — mulu.w y,Dx 4(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 4(0/0) 1 2 Effective address of (d16,PC) not supported.
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Table 3-20.
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Exception Processing Overview If the exception is caused by an FPU instruction, the PC contains the address of either the next floating-point instruction (nextFP) if the exception is pre-instruction, or the faulting instruction (fault) if the exception is post-instruction. 3. The processor acquires the address of the first instruction of the exception handler. The instruction address is obtained by fetching a value from the exception table at the address in the vector base register.
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Table 3-21.
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Exception Processing Overview Table 3-22. Format/Vector Word 1 Bits Name Description 31–28 FORMAT Format field. Written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. FORMAT records any longword stack pointer misalignment when the exception occurred.
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Table 3-23. Processor Exceptions Type Description Access error If the MMU is disabled, access errors are reported only in conjunction with an attempted store to write-protected memory. Thus, access errors associated with instruction fetch or operand read accesses are not possible. The Version 4 processor, unlike the Version 2 and 3 processors, updates the condition code register if a write-protect error occurs during a CLR or MOV3Q operation to memory.
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Exception Processing Overview Table 3-23. Processor Exceptions (Continued) Type Description Unimplemented A line-a opcode results when bits 15–12 of the opword are 1010. This exception is generated by the line-a opcode attempted execution of an undefined line-a opcode. Unimplemented A line-f opcode results when bits 15–12 of the opword are 1111. This exception is generated under the line-f opcode following conditions: • When attempting to execute an undefined line-f opcode.
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3.9 Precise Faults To support a demand-paged virtual memory environment, all memory references require precise, recoverable faults. The ColdFire instruction restart mechanism ensures that a faulted instruction restarts from the beginning of execution; that is, no internal state information is saved when an exception occurs and none is restored when the handler ends.
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Precise Faults NOTE For access errors signaled on instruction prefetches, an access error exception is generated only if instruction execution is attempted. If an instruction fetch access error exception is generated and the FS field indicates the fault occurred on an extension word, it may be necessary for the exception PC to be rounded-up to the next page address to determine the faulting instruction fetch address. MCF548x Reference Manual, Rev.
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Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. 4.1 Introduction The MAC design provides a set of DSP operations which can be used to improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.
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4.1.1 MAC Overview The MAC is an extension of the basic multiplier found in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures.
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Introduction execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or subtraction.
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X Product Extended Product OperandY 32 OperandX 32 8 32 8 8 32 8 8 32 24 + Accumulator Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0] Figure 4-5. Signed and Unsigned Integer Alignment Thus, the 48-bit accumulator definition is a function of the EMAC operating mode.
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Memory Map/Register Definition The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can move large blocks of data efficiently by generating line-sized burst transfers. The ability to simultaneously load an operand from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 OMC S/U F/I R/T N Z V EV 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R PAVx W Reset 0 0 0 0 Reg Addr Figure 4-7. MAC Status Register (MACSR) Table 4-1 describes MACSR fields. Table 4-1.
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Memory Map/Register Definition Table 4-1. MACSR Field Descriptions (Continued) Bits Name Description 5 F/I Operational mode field: Fractional/integer mode Determines whether input operands are treated as fractions or integers. 0 Integers can be represented in either signed or unsigned notation, depending on the value of S/U. 1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to 1- 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions.
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Table 4-2. Summary of S/U, F/I, and R/T Control Bits 4.2.1.1 S/U F/I R/T Operational Modes 0 0 x Signed, integer 0 1 0 Signed, fractional Truncate on MAC.L and MSAC.L No round on accumulator stores 0 1 1 Signed, fractional Round on MAC.L and MSAC.L Round-to-32-bits on accumulator stores 1 0 x Unsigned, integer 1 1 0 Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores 1 1 1 Signed, fractional Round on MAC.L and MSAC.
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Memory Map/Register Definition then Result = R0.U + 1 else if lsb of R0.U = 0 /* R0.L = 0x8000 */ then Result = R0.U else Result = R0.U + 1 The round-to-nearest-even technique is also known as convergent rounding. 4.2.1.1.2 Saving and Restoring the EMAC Programming Model The presence of rounding logic in the output datapath of the EMAC requires that special care be taken during the EMAC’s save/restore process.
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move.l move.l d6,mask d7,macsr ; restore the address mask ; restore the macsr By executing this type of sequence, the exact state of the EMAC programming model can be correctly saved and restored. 4.2.1.1.3 MULS/MULU MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be integers. 4.2.1.1.4 Scale Factor in MAC or MSAC Instructions The scale factor is ignored while the MAC is in fractional mode. 4.2.
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EMAC Instruction Set Summary 4.3 EMAC Instruction Set Summary Table 4-3 summarizes EMAC unit instructions. Table 4-3.
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The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible copy of the accumulator is available. Figure 4-8 shows EMAC timing. Three-cycle regBusy stall mac DSOC mov mov AGEX mac mov EMAC EX1 mac mov mac EMAC EX2 mac EMAC EX3 mac EMAC EX4 Accumulator 0 new old Figure 4-8. EMAC-Specific OEP Sequence Stall In Figure 4-8, the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC pipeline minus 1.
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EMAC Instruction Set Summary This format can represent numbers in the range -1 < operand < 1 - 2(N-1). For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15); the most positive longword is 0x7FFF_FFFF or (1 - 2-31). 4.3.3 EMAC Opcodes EMAC opcodes are described in the ColdFire Programmer’s Reference Manual.
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} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xfff f_ff_1)) then { /* product overflow */ MACSR.PAVx = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.
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EMAC Instruction Set Summary MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVx MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1)) then MACSR.EV = 0 else MACSR.
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/* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1 MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000 } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVx MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.
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EMAC Instruction Set Summary result[47:0] = 0xffff_ffff_ffff } /* zero-fill to 48 bits before performing any scaling */ product[47:40] = 0 /* zero-fill upper byte */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {0, product[39:1]} break; } /* combine with accumulator */ if
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Chapter 5 Memory Management Unit (MMU) This chapter describes the ColdFire virtual memory management unit (MMU), which provides virtual-to-physical address translation and memory access control. The MMU consists of memory-mapped control, status, and fault registers that provide access to translation-lookaside buffers (TLBs). Software can control address translation and access attributes of a virtual address by configuring MMU control registers and loading TLBs.
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• • • • 5.2.2 The address access control logic, address attribute logic, memories, and controller function as in previous ColdFire versions with the addition of the MMU. The MMU, its TLB, and associated control reside in the logic. The MMU appears as a memory-mapped device in the space. Information for access error fault processing is stored in the MMU. A precise fault (transfer error acknowledge) signals the core on translation (TLB miss) and access faults.
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Virtual Memory Management Architecture Instruction Fetch Pipeline J IAG Branch Cache KC1 IC1 KC2 IC2 Branch Accel. Instruction Memory Physical KC1 IED IB Memory Management Unit (MMU) Operand Execution Pipeline DS Physical KC1 DS J OAG Data Memory KC1 OC1 KC2 OC2 EX M Bus K2M EMAC Misalignment Module FPU DA BDM DSCLK DSI DSDO DDATA PSTDDATA PSTCLK Figure 5-1. CF4e Processor Core Block with MMU 5.2.
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5.2.3.1 Precise Faults The MMU architecture performs virtual-to-physical address translation and permission checking in the core. To support demand-paging, the core design provides a precise, recoverable fault for all references. 5.2.3.2 MMU Access The MMU TLB control registers are memory-mapped. The TLB entries are read and written indirectly through the MMU control registers.
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Virtual Memory Management Architecture more bits than the in-page address, one or more of the low-order virtual page number bits are used to address the cache. The MMU translates these bits; the resulting low-order physical page number bits are used to determine cache hits. Address aliasing problems occur when two virtual addresses access one physical page. This is generally allowed and, if the page is cacheable, one coherent copy of the page image is mapped in the cache at any time.
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Table 5-1. New ACR and CACR Bits Bits Name Description ACRn[10] AMM Address mask mode. Determines access to the associated address space. 0 The ACR hit function is the same as previous versions, allowing control of a 16-Mbyte or greater memory region. 1 The upper 8 bits of the address and ACR are compared without a mask function; bits 23–20 of the address and ACR are compared masked by ACR[19–16], allowing control of a 1- to 16-Mbyte region. Reset value is 0. ACRn[3] SP Supervisor protect.
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Debugging in a Virtual Environment 5.2.3.11 Supervisor Protection Each instruction or data reference is either a supervisor or user access. The CPU’s status register supervisor bit (SR[S]) determines the operating mode. New ACR and CACR bits protect supervisor space. See Table 5-1. 5.3 Debugging in a Virtual Environment To support debugging in a virtual environment, numerous enhancements are implemented in the ColdFire debug architecture.
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In addition, the following two privileged M68000 family instructions to load/store the USP are added to the ColdFire instruction set architecture: mov.l mov.l Ay,USP USP,Ax # move to USP: opcode = 0x4E6{0-7} # move from USP: opcode = 0x4E6{8–F} The address register number is encoded in the three low-order bits of the opcode. These instructions are described in detail in Section 5.7, “MMU Instructions.” 5.4.
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MMU Definition 5.5 MMU Definition The ColdFire MMU provides a virtual address, demand-paged memory architecture. The MMU supports hardware address translation acceleration using software-managed TLBs. It enforces permission checking on a per-memory request basis, and has control, status, and fault registers for MMU operation. 5.5.1 Effective Address Attribute Determination The ColdFire core generates an effective memory address for all instruction fetches and data read and write memory accesses.
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• If virtual mode is enabled, any normal mode access that does not hit in the MMUBAR, RAMBARs, ROMBARs, or ACRs is considered a normal mode virtual address request and generates its access attributes from the MMU. For this case, the default CACR address attributes are not used. The MMU also uses TLB contents to perform virtual-to-physical address translation. 5.5.2 MMU Functionality The MMU provides virtual-to-physical address translation and memory access control.
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MMU Definition Table 5-3. MMUBAR Field Descriptions Bits Name Description 31–16 BA Base address. Defines the base address for the 64-Kbyte address space mapped to the MMU. 15–1 — Reserved, should be cleared. Writes are ignored and reads return zeros. 0 V Valid. Indicates when MMUMBAR contents are valid. BA is not used unless V is set. 0 MMUBAR contents are not valid. 1 MMUBAR contents are valid. 5.5.3.
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASM EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MMUBAR + 0x000 Figure 5-4. MMU Control Register (MMUCR) Table 5-5 describes MMUCR fields. Table 5-5. MMUCR Field Descriptions Bits Name 31–2 — 1 ASM 0 EN 5.5.3.
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MMU Definition 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 AA W Reset R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R/W ACC UAA 0 0 0 0 0 0 0 0 0 0 STLB CA CNL CAS ITLB ADR W Reset Reg Addr 0 0 0 0 0 0 MMUBAR + 0x004 Figure 5-5. MMU Operation Register (MMUOR) Table 5-6 describes MMUOR fields. Table 5-6.
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Table 5-6. MMUOR Field Descriptions (Continued) Bits Name 5 CAS Clear all non-locked TLB entries that match ASID. CAS is always reads as a zero. 0 No operation 1 Clear all non-locked TLB entries that match ASID register. 4 ITLB ITLB operation. Used by TLB search and access operations that use the TLB allocation address. 0 The MMU uses the DTLB to search or update the allocation address. 1 The MMU uses the ITLB for searches and updates of the allocation address. 3 ADR TLB address select.
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MMU Definition Table 5-7. MMUSR Field Descriptions Bits Name 31–6 — 5 SPF Supervisor protect fault. Indicates if the last data fault was a user mode access that hit in a TLB entry that had its supervisor protect bit set. 0 Last data access fault did not have a supervisor protect fault. 1 Last data access fault had a supervisor protect fault. 4 RF Read access fault. Indicates if the last data fault was an data read access that hit in a TLB entry that did not have its read bit set.
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Table 5-8. MMUAR Field Descriptions Bits Name Description 31–0 FA Form address. Written by the MMU with the virtual address on DTLB misses and access faults. For this case, all 32 bits are address bits. This register may be written with a virtual address and address attribute information for searching the TLB (MMUCR[STLB]). For this case, FA[31–1] are the virtual page number and FA[0] is the supervisor bit. The current ASID is used for the TLB search.
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MMU Definition Table 5-9. MMUTR Field Descriptions (Continued) Bits Name Description 1 SG Shared global. Indicates when the entry is shared among user address spaces. If an entry is shared, its ASID is not part of the TLB hit determination for user accesses. 0 This entry is not shared globally. 1 This entry is shared globally. Note that the ASID can be used to determine supervisor mode hits to allow two sharing levels.
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Table 5-10. MMUDR Field Descriptions (Continued) 5.5.4 Bits Name Descriptions 7–6 CM Cache mode. If a Harvard TLB implementation is used, CM0 is a don’t care for the ITLB. CM is ignored on writes and always reads as zero for the ITLB. Instruction cache modes: 1x Page is non-cacheable. 0x Page is cacheable. Data cache modes 00 Page is cacheable writethrough. 01 Page is cacheable copyback. 10 Page is non-cacheable precise. 11 Page is non-cacheable imprecise. 5 SP Supervisor protect.
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MMU Definition 5.5.5 MMU Operation The processor sends instruction fetch requests and data read/write requests to the MMU in the instruction and operand address generation cycles (IAG and OAG). The controller and memories occupy the next two pipeline stages, instruction fetch cycles 1 and 2 (IC1 and IC2) and operand fetch cycles 1 and 2 (OC1 and OC2). For late writes, optional data pipeline stages are added to the controller as well as any writable memories.
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Figure 5-10 shows more details of the MMU structure. The TLB is accessed at the beginning of the KC1 pipeline stage so the resulting physical address can be sourced to the cache controllers to factor into the cache hit/miss determination. This is required because caches are virtually indexed but physically mapped.
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MMU Implementation When MMUAR is used for a TLB address, bits FA[5–0] also have this address format for CF4e. The remaining form address bits (FA[31–6]) are ignored when this register is being used for a TLB address. 5.6.2 TLB Replacement Algorithm The instruction and data TLBs provide low-latency access to recently used instruction and operand translation information. CF4e ITLBs and DTLBs are 32-entry fully associative caches.
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Table 5-13.
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MMU Instructions Current address space ID (ASID) J Instruction or data address and attributes TLB Tag Entry 31 TLB Tag Entry 0 TLB Tag Entry 31 TLB Tag Entry 0 KC1 Compare Compare Instruction or data hit select To control for instruction or DTLB miss logic IC1 or OC1 translated address IC1 or OC1 access control Figure 5-11. Version 4 ColdFire MMU Harvard TLB 5.7 MMU Instructions The MOVE to USP and MOVE from USP instructions have been added for accessing the USP.
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Chapter 6 Floating-Point Unit (FPU) 6.1 Introduction This chapter describes instructions implemented in the floating-point unit (FPU) designed for use with the ColdFire family of microprocessors. The FPU conforms to the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE) Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754).
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Table 6-1. Notational Conventions (Continued) Symbol Description & Logical AND | Logical OR → tested sign-extended Source operand is moved to destination operand Any double-operand operation Operand is compared to zero and the condition codes are set appropriately All bits of the upper portion are made equal to the high-order bit of the lower portion Other Operations If then else Test the condition.
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Operand Data Formats and Types Table 6-2. Floating-Point Addressing Modes Addressing Modes Syntax Register direct Address register direct Address register direct 6.
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yields a signed, two’s complement power of two. This represents the magnitude of a normalized floating-point number when multiplied by the mantissa. By definition, a normalized mantissa always takes values starting from 1.0 and going up to, but not including, 2.0; that is, [1.0...2.0). 6.2.3 Floating-Point Data Types Each floating-point data format supports five unique data types: normalized numbers, zeros, infinities, NANs, and denormalized numbers.
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Operand Data Formats and Types 6.2.3.4 Not-A-Number When created by the FPU, NANs represent the results of operations having no mathematical interpretation, such as infinity divided by infinity. Operations using a NAN operand as an input return a NAN result. User-created NANs can protect against uninitialized variables and arrays or can represent user-defined data types. See Figure 6-6. Exponent = Maximum Fraction = Any nonzero bit pattern Sign of Mantissa, 0 or 1 Figure 6-6.
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Table 6-3. Real Format Summary (Continued) Parameter Single-Precision Double-Precision Biased exponent (e) 8 11 Fraction (f) 23 52 Total 32 64 Interpretation of Sign Positive fraction s=0 s=0 Negative fraction s=1 s=1 Normalized Numbers Bias of biased exponent Range of biased exponent Range of fraction +127 (0x7F) +1023 (0x3FF) 0 < e < 255 (0xFF) 0 < e < 2047 (0x7FF) Zero or Nonzero Zero or Nonzero 1.f 1.f (–1)s × 2e–127 × 1.f (–1)s × 2e–1023 × 1.
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Register Definition Table 6-3. Real Format Summary (Continued) Parameter Single-Precision Double-Precision Approximate Ranges Maximum Positive Normalized 3.4 × 1038 1.8 x 10308 Minimum Positive Normalized 1.2 × 10–38 2.2 x 10–308 Minimum Positive Denormalized 1.4 × 10–45 4.9 x 10–324 6.
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The user can read or write to FPCR using FMOVE or FRESTORE. A processor reset or a restore operation of the null state clears the FPCR. When this register is cleared, the FPU never generates exceptions.
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Register Definition 6.3.3 Floating-Point Status Register (FPSR) The FPSR, Figure 6-10, contains a floating-point condition code byte (FPCC), a floating-point exception status byte (EXC), and a floating-point accrued exception byte (AEXC). The user can read or write all FPSR bits. Execution of most floating-point instructions modifies FPSR. FPSR is loaded using FMOVE or FRESTORE. A processor reset or a restore operation of the null state clears the FPSR.
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Table 6-5. FPSR Field Descriptions Bits Field Description 31–28 — Reserved, should be cleared.
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Floating-Point Computational Accuracy For FPU instructions that can generate exception traps, the 32-bit FPIAR is loaded with the instruction PC address before the FPU begins execution. In case of an FPU exception, the trap handler can use the FPIAR contents to determine the instruction that generated the exception. FMOVE to/from FPCR, FPSR, or FPIAR and FMOVEM instructions cannot generate floating-point exceptions; therefore, they do not modify FPIAR. A reset or a null-restore operation clears FPIAR. 6.
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double-precision format. If the destination is a memory location or an integer data register, rounding precision is ignored. In this case, a number in the double-precision format is taken from the source floating-point data register, rounded to the destination format precision, and then written to memory or the integer data register.
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Floating-Point Computational Accuracy Entry Guard, Round and Sticky Bits = 0 INEX 1 Select Rounding Mode Check Intermediate Result RN Pos G and lsb = 1, R and S = 0 or G = 1, R or S = 1 RM Neg RP Pos G, R, or S = 1 N Y RZ Neg G, R, or S = 1 Y N Exact Result G,R, and S are chopped Add 1 to lsb Add 1 to lsb Overflow = 1 Shift mantissa right 1 bit, Add 1 to exponent Guard Round Sticky 0 0 0 Exit Exit Figure 6-12.
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Table 6-6. Tie-Case Example Result Integer 52-Bit Fraction Guard Round Sticky Intermediate x xxx…x00 1 0 0 Rounded-to-Nearest x xxx…x00 0 0 0 The lsb of the rounded result does not increment even though the guard bit is set in the intermediate result. The IEEE-754 standard specifies this way of handling ties.
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Floating-Point Post-Processing rounding precision and mode. After rounding, the inexact bit (INEX) is set as described in Figure 6-12. Lastly, the magnitude of the result is checked to see if it exceeds the current rounding precision. If so, the overflow (OVFL) bit is set, and a correctly signed infinity or correctly signed largest normalized number is returned, depending on the rounding mode. NOTE INEX can also be set by OVFL, UNFL, and when denormalized numbers are encountered. 6.5.
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unordered condition is present when the conditional test is attempted (IEEE nonaware tests). The other 16 do not cause an exception (IEEE-aware tests). The set of IEEE nonaware tests is best used in one of the following cases: • When porting a program from a system that does not support the IEEE standard to a conforming system • When generating high-level language code that does not support IEEE floating-point concepts (that is, the unordered condition).
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Floating-Point Exceptions Table 6-9.
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Table 6-10.
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Floating-Point Exceptions A floating-point arithmetic exception becomes pending when the result of a floating-point instruction sets an FPSR[EXC] bit and the corresponding FPCR[ENABLE] bit is set. A user write to the FPSR or FPCR that causes the setting of an exception bit in FPSR[EXC] along with its corresponding exception enabled in FPCR, leaves the FPU in an exception-pending state. The corresponding exception is taken at the start of the next arithmetic instruction as a pre-instruction exception.
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Table 6-12. BSUN Exception Enabled/Disabled Results Condition BSUN Description Exception disabled 0 The floating-point condition is evaluated as if it were the equivalent IEEE-aware conditional predicate. No exceptions are taken. Exception Enabled 1 The processor takes a floating-point pre-instruction exception. The BSUN exception is unique in that the exception is taken before the conditional predicate is evaluated.
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Floating-Point Exceptions 6.6.1.4 Operand Error (OPERR) The operand error exception encompasses problems arising in a variety of operations, including errors too infrequent or trivial to merit a specific exception condition. Basically, an operand error occurs when an operation has no mathematical interpretation for the given operands. Table 6-15 lists possible operand errors. When one occurs, FPSR[OPERR] is set. Table 6-15.
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Table 6-17. OVFL Exception Enabled/Disabled Results Condition OVFL Description Exception disabled 0 The values stored in the destination based on the rounding mode defined in FPCR[MODE]. RN Infinity, with the sign of the intermediate result. RZ Largest magnitude number, with the sign of the intermediate result. RM For positive overflow, largest positive normalized number For negative overflow, -∞. RP For positive overflow, +∞ For negative overflow, largest negative normalized number.
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Floating-Point Exceptions Table 6-19. DZ Exception Enabled/Disabled Results Condition DZ Exception disabled 0 The destination floating-point data register is written with infinity with the sign set to the exclusive OR of the signs of the input operands. Exception enabled 1 The destination floating-point data register is written as in the exception is disabled case. 6.6.1.
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Note that if no intervention is needed, instead of FSAVE, the handler can simply clear the appropriate FPCR and FPSR bits and then return from the exception. Because the FPCR and FPSR are written in the FSAVE frame, a context switch needs only execute FSAVE and FMOVEM for data registers. The new process needs to load data registers by using a FMOVEM/FRESTORE sequence before it can continue. FSAVE operations always write a 4-longword floating-point state frame that holds a 64-bit exception operand.
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Instructions Normally, an exception handler executes FSAVE, processes the exception, clears the exception bit in the FSAVE state frame status word, and executes FRESTORE. If appropriate exception bits set in the status word are not cleared, the same exception is taken again. If multiple exception bits are set in the status word, each should be processed, cleared, and restored by their respective handlers. In this way, all exceptions are processed in priority order.
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Table 6-23.
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Instructions Table 6-24. Instruction Format Terminology (Continued) Term Definition OPMODE Defines the exact operation to be performed by the FPU. SZ Defines the length of the PC-relative displacement for the FPU conditional branch instruction. If SZ = 0, the displacement is 16 bits, otherwise a 32-bit displacement is used. dr Specifies direction of the MOVE transfer. As a 0, it moves from memory to the FP; as 1, it moves from the FP to memory.
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Table 6-25.
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Instructions Table 6-26. Key Programming Model Differences (Continued) Feature M68000 ColdFire Support for fpGEN xxx.{w,l},FPx Yes No Support for fpGEN d8(PC,Xi),FPx Yes No Support for fpGEN #xxx,FPx Yes No Support for fmovem (Ay)+,#list Yes No Support for fmovem #list,-(Ax) Yes No Support for fmovem FP Control Registers Yes No Some differences affect function activation and return.
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values be moved into a table of constants that can be referenced using PC-relative addressing or as an offset from another address pointer. See Table 6-29. Table 6-29. M68000/ColdFire Operation Sequence 3 M68000 ColdFire Equivalent fadd.l #imm1,fp3 fadd.l (imm1_label,pc),fp3 fsub.s #imm2,fp4 fsub.s (imm2_label,pc),fp3 fdiv.d #imm3,fp5 fdiv.
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Chapter 7 Local Memory This chapter describes the MCF548x implementation of the ColdFire Version 4e local memory specification. It consists of two major sections. • Section 7.2, “SRAM Overview,” describes the MCF548x core’s local static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. • Section 7.
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• • • • 7.3 Physical location on the processor’s high-speed local bus with a user-programmed connection to the internal instruction or data bus Memory location programmable on any 0-modulo-4K address boundary Byte, word, and longword address capabilities The RAM base address registers (RAMBAR0 and RAMBAR1) define the logical base address, attributes, and access types for the two SRAM modules.
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SRAM Register Definition 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 BA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 WP D/I 0 C/I SC SD UC UD V 0 0 0 0 0 0 0 0 0 0 0 0 R BA W Reset 0 0 0 Reg Addr 0 CPU space + 0xC04 (RAMBAR0), 0xC05 (RAMBAR1) Figure 7-1. SRAM Base Address Registers (RAMBARn) RAMBARn fields are described in detail in Table 7-1. Table 7-1.
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Table 7-1. RAMBARn Field Description (Continued) Bits Name Description 5 C/I 4 SC 3 SD 2 UC 1 UD Address space masks (ASn). These fields allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as described in Section 7.6, “Power Management.” In particular, C/I is typically set. The address space mask bits are follows: C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
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SRAM Initialization 3. After the data is loaded into the SRAM, it may be appropriate to revise the RAMBAR attribute bits, including the write-protect and address-space mask fields. If the SRAM contains instructions, RAMBAR[D/I] must be set to logically connect the memory to the processor’s internal instruction bus. Remember that the SRAM cannot be accessed by the on-chip DMAs.
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; +20 ; +24 loop: 7.6 destinationOffset bytesToMove move.l movec.l RAMBASE+RAMFLAGS,a0 ;define RAMBAR0 contents a0,rambar0;load it move.l 16(a7),a0;load argument defining *src lea.l add.l RAMBASE,a1;memory pointer to SRAM base 20(a7),a1;include destinationOffset move.l asr.l 24(a7),d4;load byte count #4,d4 ;divide by 16 to convert to loop count .align movem.l movem.l lea.l lea.l subq.l bne.
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Cache Organization The MCF548x processor’s Harvard memory structure includes a 32-Kbyte data cache and a 32-Kbyte instruction cache. Both are nonblocking and 4-way set-associative with a 16-byte line. The cache improves system performance by providing single-cycle access to the instruction and data pipelines. This decouples processor performance from system memory performance, increasing bus availability for on-chip DMA or external devices.
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Way 0 Way 1 Way 2 Way 3 • • • • • • Line • • • • • • Set 0 Set 1 Set 510 Set 511 Cache Line Format TAG V M Longword 0 Longword 1 Longword 2 Longword 3 Where: TAG—21-bit address tag V—Valid bit for line M—Modified bit for line (data cache only) Figure 7-3. Data Cache Organization and Line Format A set is a group of four lines (one from each level, or way), corresponding to the same index into the cache array. 7.8.
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Cache Organization Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A: Cache population at start-up Way 0Way 1Way 2Way 3 B: Cache after invalidation, C: Cache after loads in before it is enabled Way 0 Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way 3 At reset, cache contents are indeterminate; V and M may be set. The cache should be cleared explicitly by setting CACR[DCINVA] before the cache is enabled. Setting CACR[DCINVA] invalidates the entire cache.
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7.9 Cache Operation Figure 7-5 shows the general flow of a caching operation using the 32-Kbyte data cache as an example. The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that there is no support for writing to the cache; therefore, such notions of modified cache lines and write allocation do not apply.
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Cache Operation pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to the next way. Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking.
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Valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated. Such a scenario suggests that the associated cache mode for this address space was changed. To avoid this, it is generally recommended to use the CPUSHL instruction to push or invalidate the cache entry or set CACR[DCINVA] to invalidate the data cache before switching cache modes. 7.9.
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Cache Operation 7.9.1.1.2 Copyback Mode (Data Cache Only) Copyback regions are typically used for local data structures or stacks to minimize external bus use and reduce write-access latency. Write accesses to regions specified as copyback that hit in the cache update the cache line and set the corresponding M bit without an external bus access. The cache should be flushed using the CPUSHL instruction before invalidating the cache in copyback mode using the CINV bit.
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an exception aborts the instruction and the data may be accessed again when the instruction is restarted. These guarantees apply only when ACRn[CM] indicates precise mode and aligned accesses. CPU space-register accesses using the MOVEC instruction are treated as cache-inhibited and precise. 7.9.2 Cache Protocol The following sections describe the cache protocol for processor accesses and assumes that the data is cacheable (that is, write-through or copyback).
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Cache Operation 7.9.2.3 Read Hit On a read hit, the cache provides the data to the processor core and the cache line state remains unchanged. If the cache mode changes for a specific region of address space, lines in the cache corresponding to that region that contain modified data are not pushed out to memory when a read hit occurs within that line. First execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching the cache mode. 7.9.2.
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7.9.4.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. After the bus transfer for the new line completes, the modified cache line is written back to memory and the push buffer is invalidated. 7.9.4.2.
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Cache Operation 7.9.5 Cache Locking Ways 0 and 1 of the data cache can be locked by setting CACR[DHLCK]; likewise, ways 0 and 1 of the instruction cache can be locked by setting CACR[IHLCK]. If a cache is locked, cache lines in ways 0 and 1 are not subject to being deallocated by normal cache operations. As Figure 7-7 (B and C) shows, the algorithm for updating the cache and for identifying cache lines to be deallocated is otherwise unchanged.
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Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A: Ways 0 and 1 are filled. Ways 2 and 3 are invalid. B: CACR[DHLCK] is set, locking ways 0 and 1. C: When a set in Way 2 is D: Write hits to ways 0 occupied, the set in way 3 and 1 update cache is used for a cacheable lines. access. Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way 3 Way 0Way 1Way 2Way 3 After CACR[DHLCK] is set, subsequent cache accesses go to ways 2 and 3.
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Cache Register Definition 7.10 Cache Register Definition This section describes the MCF548x implementation of the Version 4e cache registers. 7.10.1 Cache Control Register (CACR) The CACR in Figure 7-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache; however, reset does not affect the tags, state information, or data in the cache.
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Table 7-4. CACR Field Descriptions (Continued) Bits Name Description 28 DDPI Disable CPUSHL invalidation. 0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified, then invalidated. 1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then left valid. 27 DHLCK Half-data cache lock mode 0 Normal operation. The cache allocates the lowest invalid way.
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Cache Register Definition Table 7-4. CACR Field Descriptions (Continued) Bits Name Description 13 DNFB Default cache-inhibited fill buffer 0 Fill buffer does not store cache-inhibited instruction accesses (16 or 32 bits). 1 Fill buffer can store cache-inhibited accesses. The buffer is used only for normal (TT = 0) instruction reads of a cache-inhibited region. Instructions are loaded into the buffer by a burst access (line fill).
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7.10.2 Access Control Registers (ACR0–ACR3) The ACRs, Figure 7-9, assign control attributes, such as cache mode and write protection, to specified memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3 control instruction attributes. Registers are accessed with the MOVEC instruction with the Rc encodings in Figure 7-9. For overlapping data regions, ACR0 takes priority; ACR2 takes priority for overlapping instruction regions. Data transfers to and from these registers are longword transfers.
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Cache Management Table 7-5. ACRn Field Descriptions (Continued) Bits Name Description 14–13 S Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address range or if the type of access is a don’t care. 00 Match addresses only in user mode 01 Match addresses only in supervisor mode 1x Execute cache matching on all accesses 12–11 — Reserved, should be cleared. 10 AMM 9–7 — Reserved; should be cleared. 6–5 CM Cache mode.
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The contents of An used with CPUSHL specify cache row and line indexes. This differs from the 68K family where a physical address is specified. Figure 7-11 shows the An format for the data cache. The contents of An used with CPUSHL specify cache row and line indexes. Figure 7-10 shows the An format for the data cache. 31 13 12 0 4 3 0 Set Index Way Index Figure 7-10. An Format (Data Cache) Figure 7-11 shows the An format for the instruction cache.
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Cache Management dataCacheLoadAndLock: move.l movec #0xa3080800,d0; enable and invalidate data cache ... d0,cacr ; ... in the CACR The following code preloads half of the data cache (16 Kbytes). It assumes a contiguous block of data is to be mapped into the data cache, starting at a 0-modulo-16K address. move.l lea dataCacheLoop: tst.b lea subq.l bne.
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7.12 Cache Operation Summary This section gives operational details for the cache and presents instruction and data cache-line state diagrams. 7.12.1 Instruction Cache State Transitions Because the instruction cache does not support writes, it supports fewer operations than the data cache. As Figure 7-12 shows, an instruction cache line can be in one of two states, valid or invalid. Modified state is not supported.
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Cache Operation Summary 7.12.2 Data Cache State Transitions Using the V and M bits, the data cache supports a line-based protocol allowing individual cache lines to be invalid, valid, or modified. To maintain memory coherency, the data cache supports both write-through and copyback modes, specified by the corresponding ACR[CM], or CACR[DDCM] if no ACR matches. Read or write misses to copyback regions cause the cache controller to read a cache line from memory into the cache.
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Table 7-7. Data Cache Line State Transitions Current State Access Invalid (V = 0) Valid (V = 1, M = 0) Modified (V = 1, M = 1) Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. (C,W)V1 Read new line from memory and update cache; supply data to processor; stay in valid state. CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state.
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Cache Operation Summary Table 7-8. Data Cache Line State Transitions (Current State Invalid) Access Response Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. Read hit (C,W)I2 Not possible Write miss (copyback) CI3 Read line from memory and update cache; write data to cache; go to modified state. Write miss (write-through) WI3 Write data to memory; stay in invalid state.
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In Table 7-10 the current state is modified. Table 7-10. Data Cache Line State Transitions (Current State Modified) Access Response Read miss CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. Read hit CD2 Supply data to processor; stay in modified state.
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Chapter 8 Debug Support 8.1 Introduction This chapter describes the Revision D enhanced hardware debug support in the ColdFire Version 4. This revision of the ColdFire debug architecture encompasses earlier revisions. An expanded set of debug functionality is defined as Revision B (or Rev. B). The further enhanced debug architecture implemented in the Version 4 ColdFire is known as Revision C (or Rev. C).
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generations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configuration/Status Register (CSR).” The Version 3 core implements Revision B of the debug architecture, offering more flexibility for configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while hardware breakpoint registers are active. For Revision B, CSR[HRL] is 1.
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Signal Descriptions Table 8-1. Debug Module Signals Signal Description DSCLK Development Serial Clock-Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
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output for the processor’s sequential execution of single-cycle instructions (A, B, C, D...). Cycle counts are shown relative to processor frequency. These outputs indicate the current processor pipeline status and are not related to the current bus transfer. Table 8-2.
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Real-Time Trace Support NOTE A PST marker and its data display are sent contiguously. Except for this transmission, the IDLE status (0x0) can appear anytime. Again, given that real-time trace information appears as a sequence of 4-bit values, there are no alignment restrictions. That is, PST values and operands may appear on either nibble of PSTDDATA. 8.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path, is a fundamental debug function.
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Table 8-4. Processor Status Encoding (Continued) PST[3:0] Definition Hex Binary 0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the PSTDDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer on the PSTDDATA port.
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Real-Time Trace Support The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the V4 microarchitecture uses the debug pins to output the following sequence of information on two successive processor clock cycles: 1.
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Table 8-5. 0xE Status Posting PSTDDATA Stream Includes 8.3.3 Result {0xE, 0x2} Breakpoint state changed to waiting for level-1 trigger {0xE, 0x4} Breakpoint state changed to level-1 breakpoint triggered {0xE, 0xA} Breakpoint state changed to waiting for level-2 trigger {0xE, 0xC} Breakpoint state changed to level-2 breakpoint triggered {0xE, 0xE} Stopped mode. Processor Halted (PST = 0xF) PST is 0xF when the processor is halted (see Section 8.5.1, “CPU Halt”).
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Memory Map/Register Definition 8.4 Memory Map/Register Definition In addition to the existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains 19 registers to support the required functionality. These registers are also accessible from the processor’s supervisor programming model by executing the WDEBUG instruction (write only).
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The registers in Table 8-7 are accessed through the BDM port by BDM commands, WDMREG and RDMREG, described in Section 8.5.3.3, “Command Set Descriptions.” These commands contain a 5-bit field, DRc, that specifies the register, as shown in Table 8-6. Table 8-6. BDM/Breakpoint Registers DRc[4–0] 0x00 0x01–0x05 Register Name Configuration/status register1 Reserved Initial State Section/ Page CSR 0x0020_0000 8.4.2/8-11 — — — 0x04 PC breakpoint ASID control PBAC — 8.4.
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Memory Map/Register Definition to guarantee that all accesses to these resources are serialized and logically consistent. The hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting IPW = 1). BDM commands must not be issued if the ColdFire processor is accessing debug module registers with the WDEBUG instruction or the resulting behavior is undefined.
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31 R 30 29 28 BSTAT 27 26 25 24 FOF TRG HALT 23 22 BKPT 21 20 HRL 19 0 18 17 16 BKD0 PCD0 IPW0 W Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NPL 0 0 0 0 0 0 0 0 0 0 R MAP TRC EMU DDC UHE BTB SSM OTE W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 0 CPU + 0x00 Figure 8-6. Configuration/Status Register (CSR) Table 8-8 describes CSR fields. Table 8-8.
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Memory Map/Register Definition Table 8-8. CSR Field Descriptions (Continued) Bits Name Description 18 BKD Breakpoint disable. Used to disable the normal BKPT input functionality and to allow the assertion of BKPT to generate a debug interrupt. 0 Normal operation 1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor. The processor makes this interrupt request pending until the next sample point, when the exception is initiated.
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Table 8-8. CSR Field Descriptions (Continued) Bits Name Description 6 NPL Non-pipelined mode. Determines whether the core operates in pipelined or mode. 0 Pipelined mode 1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Superscalar instruction dispatch is disabled when operating in this mode. Given an average execution latency of 1.6, throughput in non-pipeline mode would be 6.
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Memory Map/Register Definition qualification. Reset clears these fields, disabling qualifications and defaulting to the Revision C debug module functionality. Table 8-9. PBAC Field Descriptions Bits Name 31-16 — 15–12 PBR3AC 11–8 PBR2AC 7–4 PBR1AC 3–0 PBRAC 8.4.4 Description Reserved, should be cleared. PBRn ASID control. Corresponds to the ASID control associated with PBRn.
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Table 8-10. BAAR Field Descriptions Bits Name 6–5 SZ Size 00 Longword 01 Byte 10 Word 11 Reserved 4–3 TT Transfer type. See the TT definition in Table 8-11. 2–0 TM Transfer modifier. See the TM definition in Table 8-11. 8.4.5 Description Address Attribute Trigger Registers (AATR, AATR1) The AATR and AATR1, Figure 8-9, define address attributes and a mask to be matched in the trigger.
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Memory Map/Register Definition Table 8-11. AATR and AATR1 Field Descriptions (Continued) Bits 23–16 Name Description ATTRASID ABLR/ABHR/ATTR ASID. Corresponds to the ASID to be included in the address breakpoint specified by ABLR, ABHR, and ATTR. 15 RM Read/write mask. Setting RM masks R in address comparisons. 14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12–11 TTM Transfer type mask.
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taken under the defined conditions. Breakpoint logic may be configured as one- or two-level triggers. TDR[31–16] or XTDR[31–16] define second-level triggers, and bits 15–0 define first-level triggers. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command.
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Memory Map/Register Definition Table 8-12. TDR Field Descriptions (Continued) Bits Name Description 28 EDLW2 Data enable bit: Data longword. Entire processor’s local data bus. 27 EDWL2 Data enable bit: Lower data word. 26 EDWU2 Data enable bit: Upper data word. 25 EDLL2 Data enable bit: Lower lower data byte. Low-order byte of the low-order word. 24 EDLM2 Data enable bit: Lower middle data byte. High-order byte of the low-order word. 23 EDUM2 Data enable bit: Upper middle data byte.
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Table 8-12. TDR Field Descriptions (Continued) Bits Name Description 2 EAL1 Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the ABLR. Trigger address = ABLR 1 EPC1 Enable PC breakpoint. If set, this bit enables the PC breakpoint for the first level trigger. 0 PCI1 Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger.
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Memory Map/Register Definition Table 8-13. PBR, PBR1, PBR2, PBR3 Field Descriptions Bits Name Description 31–1 CNTRAD PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger. 0 V Valid. 0 Breakpoint registers are not compared with the processor’s program counter register 1 Breakpoint registers are compared with the processor’s program counter register when the appropriate valid bit is set and TDR or XTDR are configured appropriately.
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31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 AD W1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 R AD W1 Reset 0 0 0 Reg Addr 0 0 0 0 0 CPU + 0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1) 1 ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and 0x1C, using the WDEBUG instruction and via the BDM port using the RDMREG and WDMREG commands. Figure 8-13.
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Memory Map/Register Definition 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 DATA (DBR/DBR1) W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R DATA (DBR/DBR1) W Reset 0 0 0 0 0 0 Reg Addr 0 0 0 CPU + 0x0E (DBR), 0x1E (DBR1) Figure 8-14. Data Breakpoint Registers (DBR/DBR1) Table 8-17 describes DBRn fields. Table 8-17.
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DBRs support both aligned and misaligned references. Table 8-19 shows relationships between processor address, access size, and location within the 32-bit data bus. Table 8-19. Access Size and Operand Data Location 8.4.
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Memory Map/Register Definition Table 8-20. PBASID Field Descriptions (Continued) Bits Name 15–8 PBA1SID PBR1ASID. Corresponds to the ASID associated with PBR1. 7–0 PBASID PBRASID. Corresponds to the ASID associated with PBR. 8.4.
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Table 8-21 describes XTDR fields. Table 8-21. XTDR Field Descriptions Bits Name Description 31–30 — 29 EBL2 28 EDLW2 Data enable bit: Data longword. Entire processor’s local data bus. 27 EDWL2 Data enable bit: Lower data word. 26 EDWU2 Data enable bit: Upper data word. 25 EDLL2 Data enable bit: Lower lower data byte. Low-order byte of the low-order word. 24 EDLM2 Data enable bit: Lower middle data byte. High-order byte of the low-order word.
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Memory Map/Register Definition Table 8-21. XTDR Field Descriptions (Continued) Bits Name 3 EAR1 Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR1 and ABHR1. Trigger if address Š ABHR or if address ð ABLR. 2 EAL1 Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the ABLR1. Trigger address = ABLR 1–0 — 8.4.11.1 Description Reserved, should be cleared.
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then if || if (PC_breakpoint Address1_breakpoint{&& Data1_breakpoint}) (Address1_breakpoint {&& Data1_breakpoint}) then if (PC_breakpoint || Address_breakpoint{&& Data_breakpoint}) In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2, and PBR3 breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is a function of DBR and DBMR; Address1_breakpoint is a function of ABHR1, ABLR1, and AATR1; and Data1_breakpoint is a function of DBR1 an
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Background Debug Mode (BDM) 4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, asserting BKPT creates a pending halt, which is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction; if a pending halt is detected then, the processor suspends execution and enters the halted state.
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8.5.2 BDM Serial Interface When the CPU is halted and PSTDDATA reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See Table 8-1. The development system serves as the serial communication channel master and must generate DSCLK.
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Background Debug Mode (BDM) . 16 15 0 S Data Field [15:0] Figure 8-19. Receive BDM Packet Table 8-22 describes receive BDM packet fields. Table 8-22. Receive BDM Packet Field Description Bits Name Description 16 S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. S 0 0 1 1 1 15–0 Data 8.5.2.
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Table 8-24. BDM Command Summary Description CPU State1 Command (Hex) Command Mnemonic Read A/D register rareg/ rdreg Read the selected address or data register and return the results through the serial interface. Halted 8.5.3.3.1 0x218 {A/D, Reg[2:0]} Write A/D register wareg/ wdreg Write the data operand to the specified address or data register. Halted 8.5.3.3.2 0x208 {A/D, Reg[2:0]} Read memory location read Read the data at the memory location specified by the longword address.
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Background Debug Mode (BDM) 8.5.3.1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in Figure 8-21. 15 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 0 Register Extension Word(s) Figure 8-21. BDM Command Format Table 8-25 describes BDM fields. Table 8-25.
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sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.
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Background Debug Mode (BDM) 8.5.3.3 Command Set Descriptions The following sections describe the commands summarized in Table 8-24. NOTE The BDM status bit (S) is 0 for normally completed commands. S = 1 for illegal commands, not-ready responses, and transfers with bus-errors. Section 8.5.2, “BDM Serial Interface,” describes the receive packet format. Freescale reserves unassigned command opcodes for future expansion.
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Command Format: 15 12 11 0x2 8 7 0x0 4 0x8 3 2 A/D 0 Register D[31:16] D[15:0] Figure 8-25. WAREG/WDREG Command Format Command Sequence WAREG/WDREG ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX BERR NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ Figure 8-26. WAREG/WDREG Command Sequence Operand Data Result Data 8.5.3.3.3 Longword data is written into the specified address or data register. The data is supplied most-significant word first.
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Background Debug Mode (BDM) 15 12 Byte 11 8 0x1 7 0x9 4 3 0x0 Command 0 0x0 A[31:16] A[15:0] Result Word Command X X X X X X 0x1 X X 0x9 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] Result Longword Command D[15:0] 0x1 0x9 A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 8-27.
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Result Data 8.5.3.3.4 Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result, the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM].
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Background Debug Mode (BDM) Command Sequence: WRITE (B/W) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ WRITE (LONG) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 8-30. WRITE Command Sequence Operand Data Result Data 8.5.3.3.
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NOTE DUMP does not check for a valid address; it is a valid command only when preceded by NOP, READ, or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a dynamically altered.
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Background Debug Mode (BDM) Result Data: 8.5.3.3.6 Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs. Fill Memory Block (FILL) A FILL command is used with the WRITE command to access large blocks of memory.
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Command Sequence: FILL (LONG) ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR FILL (B/W) ??? DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ NEXT CMD ’NOT READY’ XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ NEXT CMD ’NOT READY’ XXX BERR Figure 8-34. FILL Command Sequence Operand Data: Result Data: 8.5.3.3.
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Background Debug Mode (BDM) Result Data: 8.5.3.3.8 NOP The command-complete response (0xFFFF) is returned during the next shift operation. No Operation (NOP) performs no operation and may be used as a null command where required. Command Formats: 15 12 0x0 11 8 0x0 7 4 0x0 3 0 0x0 Figure 8-37. NOP Command Format Command Sequence: NOP ??? NEXT CMD ’CMD COMPLETE’ Figure 8-38. NOP Command Sequence Operand Data: Result Data: 8.5.3.3.
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15 12 11 0x0 8 7 4 0x0 3 0x0 0 0x1 Figure 8-39. SYNC_PC Command Format Command Sequence: SYNC_PC NEXT CMD ??? “CMD COMPLETE” Figure 8-40. SYNC_PC Command Sequence Operand Data: Result Data: 8.5.3.3.10 None Command complete status (0xFFFF) is returned when the register write is complete. Force Transfer Acknowledge (FORCE_TA) DEBUG_D logic implements the new FORCE_TA serial BDM command to resolve a hung bus condition.
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Background Debug Mode (BDM) FORCE_TA NEXT CMD ??? “CMD COMPLETE” Figure 8-42. FORCE_TA Command Sequence Operand Data: Result Data: 8.5.3.3.11 None The command complete response, 0xFFFF (with the status bit cleared), is returned during the next shift operation. This response indicates the FORCE_TA command was processed correctly and does not necessarily reflect the status of any internal bus. Read Control Register (RCREG) Read the selected control register and return the 32-bit result.
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Table 8-26.
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Background Debug Mode (BDM) Table 8-26.
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Likewise, to write an accumulator register, the following BDM sequence is needed: BdmWriteACCx ( rcreg wcreg wcreg wcreg ) macsr; #0,macsr; #data,ACCx; #saved_data,macsr; // // // // read current macsr contents & save disable all rounding modes write the desired accumulator restore the original macsr Additionally, writes to the accumulator extension registers must be performed after the corresponding accumulators are updated because a write to any accumulator alters the corresponding extension register
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Background Debug Mode (BDM) 15 12 Command 11 8 7 4 3 0 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D[31:16] D[15:0] Figure 8-45. WCREG Command/Result Formats Command Sequence: WCREG ??? MS ADDR ’NOT READY’ MS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE CONTROL REGISTER XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 8-46. WCREG Command Sequence Operand Data: Result Data: 8.5.3.3.
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15 Command 12 11 0x2 8 7 5 0xD 4 0 100 Result DRc D[31:16] D[15:0] Figure 8-47. RDMREG BDM Command/Result Formats Table 8-27 shows the definition of DRc encoding. Table 8-27. Definition of DRc Encoding—Read DRc[4:0] Debug Register Definition Mnemonic Initial State Page 0x00 Configuration/Status CSR 0x0 p. 8-11 0x01–0x1F Reserved — — — Command Sequence: RDMREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ Figure 8-48.
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Real-Time Debug Support WDMREG ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ Figure 8-50. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Command complete status (0xFFFF) is returned when register write is complete. Result Data: 8.6 Real-Time Debug Support The ColdFire Family provides support debugging real-time applications.
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BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR. PC breakpoints are treated in a precise manner: exception recognition and processing are initiated before the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local bus, but are made pending to the processor and sampled like other interrupt conditions.
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Real-Time Debug Support 4. It executes an RTE instruction when the exception handler finishes. During the processing of the RTE, FS1 is reloaded from the system stack. If this bit is set, the processor sets the emulator mode state and resumes execution of the original debug interrupt service routine. This is signaled externally by the generation of the PST value that originally identified the debug interrupt exception, that is, PST = 0xD. Fault status encodings are listed in Table 5-2.
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• Read/write control registers For BDM commands that access memory, the debug module requests the processor’s local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus. NOTE Breakpoint registers must be carefully configured in a development system if the processor is executing.
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Debug C Definition of PSTDDATA Outputs Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax PSTDDATA andi.l #,Dx PSTDDATA = 0x1 asl.l {Dy,#},Dx PSTDDATA = 0x1 asr.l {Dy,#},Dx PSTDDATA = 0x1 bcc.{b,w,l} if taken, then PSTDDATA = 0x5, else PSTDDATA = 0x1 bchg.{b,l} #,x PSTDDATA = 0x1,{0x8, source},{0x8, destination} bchg.{b,l} Dy,x PSTDDATA = 0x1,{0x8, source},{0x8, destination} bclr.
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Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction extb.l Operand Syntax Dx PSTDDATA PSTDDATA = 0x1 PSTDDATA = 0x11 illegal jmp y PSTDDATA = 0x5, {[0x9AB], target address} 2 jsr y PSTDDATA = 0x5, {[0x9AB], target address},{0xB , destination operand}2 lea.l y,Ax PSTDDATA = 0x1 link.w Ay,# PSTDDATA = 0x1,{0xB, destination operand} lsl.l {Dy,#},Dx PSTDDATA = 0x1 lsr.l {Dy,#},Dx PSTDDATA = 0x1 mov3q.
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Debug C Definition of PSTDDATA Outputs Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax PSTDDATA ori.l #,Dx PSTDDATA = 0x1 pea.l y PSTDDATA = 0x1,{0xB, destination operand} pulse PSTDDATA = 0x4 rems.l y,Dw:Dx PSTDDATA = 0x1,{0xB, source operand} remu.l y,Dw:Dx PSTDDATA = 0x1,{0xB, source operand} rts PSTDDATA = 0x1, PSTDDATA = 0x5, {[0x9AB], target address} sats.l Dx PSTDDATA = 0x1 scc.b Dx PSTDDATA = 0x1 sub.
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1 During normal exception processing, the PSTDDATA output is driven to a 0xC indicating the exception processing state. The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
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Debug C Definition of PSTDDATA Outputs Table 8-31. PSTDDATA Values for User-Mode Multiply-Accumulate Instructions (Continued) Instruction Operand Syntax PSTDDATA move.l ACCy,Rx PSTDDATA = 0x1 move.l MACSR,CCR PSTDDATA = 0x1 move.l MACSR,Rx PSTDDATA = 0x1 move.l MASK,Rx PSTDDATA = 0x1 msac.l Ry,Rx PSTDDATA = 0x1 msac.l Ry,Rx,y,Rw,ACCx PSTDDATA = 0x1,{0xB, source operand} msac.l Ry,Rx,ACCx PSTDDATA = 0x1 msac.
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Table 8-32. PSTDDATA Values for User-Mode Floating-Point Instructions (Continued) Instruction 1 fneg.sz Operand Syntax PSTDDATA y,FPx PSTDDATA = 0x1, [89B], source} fnop PSTDDATA = 0x1 fsqrt.sz y,FPx PSTDDATA = 0x1, [89B], source} fsub.sz y,FPx PSTDDATA = 0x1, [89B], source} ftst.sz y PSTDDATA = 0x1, [89B], source} 1 The FP*R notation refers to the floating-point control registers: FPCR, FPSR, and FPIAR.
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ColdFire Debug History Table 8-34. PSTDDATA Specification for Supervisor-Mode Instructions (Continued) Instruction movec.l Operand Syntax Ry,Rc rte PSTDDATA PSTDDATA = 0x1, {8, ASID} PSTDDATA = 0x7, {0xB, source operand}, {3},{0xB, source operand}, {DD}, PSTDDATA = 0x5, {[0x9AB], target address} stop # PSTDDATA = 0x1, PSTDDATA = 0xE wdebug.
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The data_breakpoint can be included as an optional part of an address breakpoint. The ColdFire debug architecture was created to provide this set of functionality without requiring the traditional connection to the external system bus. Rather, the functionality is provided using only a connection to a Freescale-defined 26-pin debug connector. By providing the required debug signals in customer-specific designs, standard third-party emulators can be used for debug of these designs.
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Freescale-Recommended BDM Pinout Additionally, the execution of the debug interrupt service routine is forced to be interrupt-inhibited by the processor hardware. While in this service routine, there is an optional capability to map all instruction and operand references into a separate address space, so that an emulator could define the routine dynamically. The current processor implementations actually include a program-invisible state bit that defines this emulator mode of operation.
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Developer reserved 1 1 2 BKPT GND 3 4 DSCLK GND 5 6 Developer reserved1 RESET 7 8 DSI VDD_IO 2 9 10 DSO GND 11 12 PSTDDATA7 PSTDDATA6 13 14 PSTDDATA5 PSTDDATA4 15 16 PSTDDATA3 PSTDDATA2 17 18 PSTDDATA1 PSTDDATA0 19 20 GND Freescale reserved 21 22 Freescale reserved GND 23 24 PSTCLK VDD_CPU 25 26 TA 1 Pins 2 reserved for BDM developer use. Supplied by target. Figure 8-51. Recommended BDM Connector MCF548x Reference Manual, Rev.
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Part II System Integration Unit Part II describes the system integration unit, which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices. It includes a general description of the SIU and individual chapters that describe components of the SIU, such as the interrupt controller, general purpose timers, slice timers, and GPIOs.
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MCF548x Reference Manual, Rev.
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Chapter 9 System Integration Unit (SIU) 9.1 Introduction The system integration unit (SIU) of the MCF548x family integrates several timer functions required by most embedded systems. The SIU contains the following components: • Slice timers • Watchdog timer • General purpose timers • General purpose I/O ports • Interrupt controller Two internal 32-bit slice timers are provided to create short cycle periodic interrupts, typically utilized for RTOS scheduling and alarm functionality.
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Table 9-1.
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Memory Map/Register Definition 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 BA 17 16 0 0 W Reset R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr CPU + 0xC0F Figure 9-1. Module Base Address Register (MBAR) 9.3.1.
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Table 9-2. SBCR Field Descriptions (Continued) Bit Name Description 29 CPU2DMA ColdFire V4e control of the multichannel DMA breakpoint. This bit controls whether a ColdFire V4e halt condition causes the assertion of the DMA breakpoint. 0 A ColdFire V4e halt condition will not halt the DMA. 1 A ColdFire V4e halt condition will halt the DMA. 28 DMA2CPU DMA control of the ColdFire V4e breakpoint. This bit controls whether a DMA halt condition causes the assertion of the ColdFire V4e breakpoint.
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Memory Map/Register Definition 9.3.1.3 Reset Status Register (RSR) RSR allows the software, particularly the reset exception service routine, to know what type of reset has been asserted. When a reset signal is asserted, the associated status bit is set, and it maintains its value until the software explicitly clears the bit.
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Table 9-5. JTAGID Field Descriptions Bits Name Description 31–0 JTAGID The JTAG Identification Number Register is a read only register which contains the JTAG ID number for the MCF548x. Its value is hard coded and cannot be modified. Values for the MCF548x are the following: MCF5485 0x0800c01d MCF5484 0x0800d01d MCF5483 0x0800e01d MCF5482 0x0800f01d MCF5481 0x0801001d MCF5480 0x0801101d MCF548x Reference Manual, Rev.
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Chapter 10 Internal Clocks and Bus Architecture 10.1 Introduction This chapter describes the clocking and internal buses of the MCF548x and discusses the main functional blocks controlling the XL bus and the XL bus arbiter. 10.1.1 Block Diagram Figure 10-1 shows a top-level block diagram of the MCF548x products.
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10.1.2 Clocking Overview The MCF548x requires a clock generated externally to be input to the CLKIN signal. The MCF548x uses this clock as the reference clock for the internal PLL. The internal PLL then generates the clocks needed by the CPU core and integrated peripherals. The external PCI and FlexBus signals are always clocked at the same frequency as the CLKIN signal. A programmable clock multiplier (determined by the AD[12:8] signals at reset) is used to determine the XL bus frequency.
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Introduction • CommBus — The data transfer interface between the multichannel DMA and each peripheral function. 10.1.4 XL Bus Features Features of the XL bus and its integration modules include the following: • 32-bit physical address • 64-bit data bus width • Split-transaction bus; address and data tenures occur independently. • One-level address pipeline; supports up to two complete address tenures before the first data tenure completes. • Strict, in-order, address and data tenures are enforced.
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Address Tenure Arbitration Transfer Termination Data Tenure Arbitration Transfer Termination Figure 10-3. Address and Data Tenures The following outlines the basic functions of each of the phases: • Address tenure: — Arbitration: During arbitration, address bus arbitration signals are used to gain mastership of the address bus. — Transfer: After mastership is obtained, the address bus master transfers the address and transfer attributes on the address bus.
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PLL 10.2 PLL 10.2.1 PLL Memory Map/Register Descriptions Table 10-2. System PLL Memory Map 10.2.2 MBAR Offset Name 0x300 System PLL Control Register Byte0 Byte1 Byte2 Byte3 SPCR Access R/W System PLL Control Register (SPCR) The system PLL control register (SPCR) defines the clock enables used to control clocks to a set of peripherals. Unused peripherals can have their clock stopped, reducing power consumption. In addition, the SPCR contains a read-only bit for the system PLL lock status.
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Table 10-3. SPCR Field Descriptions (Continued) Bits Name 9 PSCEN 8 — 7 USBEN USB Clock Enable 6 FEC1EN FEC1 Clock Enable 5 FEC0EN FEC0 Clock Enable 4 DMAEN Multi-channel DMA Clock Enable 3 CAN0EN CAN0 Clock Enable 2 FBEN FlexBus Clock Enable 1 PCIEN PCI Bus Clock Enable 0 MEMEN 10.3 Description PSC Clock Enable - Controls clock for all PSC modules. Reserved, should be cleared.
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XL Bus Arbiter algorithm (LRU). Once a requesting master is identified as having priority and is granted the bus, that master will be continue to be granted the bus if: 1. It is requesting the bus. The request must occur immediately after the required 1 clock de-assertion after a qualified bus grant. and 2. It is the highest priority device. and 3. There is no address retry.
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10.3.2.3 Watchdog Functions 10.3.2.3.1 Timer Functions There are three watchdog timers: address tenure time out, data tenure time out, and bus activity time out. Each has a programmable timer count and can be disabled. A timer time-out will set a status bit and trigger an interrupt if that interrupt is enabled. • The address tenure watchdog is a 32-bit timer.
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XL Bus Arbiter Table 10-4. XL Bus Arbiter Memory Map (Continued) MBAR Offset Name 0x258 Arbiter Address Timeout XARB_ADRTO R/W 0x25C Arbiter Data Timeout XARB_DATTO R/W 0x260 Arbiter Bus Timeout XARB_BUSTO R/W 0x264 Arbiter Master Priority Enable XARB_PRIEN R/W 0x268 Arbiter Master Priority XARB_PRI R/W 10.3.3.
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Table 10-5. XARB_CFG Bit Descriptions (Continued) Bit Name 4 — Reserved, should be cleared. 3 BA Bus Activity Time-out Enable. If enabled, the arbiter will set the Bus Activity Time-out Status bit (XARB_SR[BA]) when the Bus Activity Time-out is reached. Bus Activity Time-out is derived from the arbiter bus activity time out count register. 0 Disable bus activity time-out 1 Enable bus activity time-out 2 DT Data Tenure Time-out Enable.
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XL Bus Arbiter 10.3.3.3 Arbiter Status Register (XARB_SR) The arbiter status register indicates the state of watchdog functions. When a monitored condition occurs, the respective bit is set to 1. The bit will stay set until the bit is cleared by writing a 1 into that bit. Even if the causal condition is removed, the bit will remain set until cleared.
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to determine the state of the arbiter. It is possible that multiple conditions exist that would cause an interrupt. Disabling an interrupt by writing a 0 to a bit in this register will not clear the status bit in the arbiter status register.
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XL Bus Arbiter Table 10-8. XARB_IMR Field Descriptions (Continued) Bits Name 1 DTE Data Tenure Time-out interrupt enable. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is enabled. 0 ATE Address Tenure Time-out interrupt enable. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is enabled. 10.3.3.
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 — TBST 0 0 0 0 0 0 0 0 0 0 W Reset R TSIZ[0:2] TT[0:4] W Reset 0 Reg Addr 0 0 0 0 0 MBAR + 0x0254 Figure 10-10. Arbiter Bus Signal Capture Register (XARB_SIGCAP) Table 10-10.
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XL Bus Arbiter Table 10-11. XARB_ADRTO Field Descriptions Bits Name 31–28 — 27–0 ADRTO 10.3.3.8 R Description Reserved, should be cleared. Upper 28-bits of the Address time-out counter value. This field is prepended to 0xF to generate the full 32-bit time-out counter value.
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10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO) 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 BUSTO W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 R BUSTO W Reset 1 1 1 1 1 1 1 1 Reg Addr 1 MBAR + 0x0260 Figure 10-13. Arbiter Bus Activity Time Out Register (XARB_BUSTO) Table 10-13.
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XL Bus Arbiter Table 10-14. XARB_PRIEN Field Descriptions Bits Name Description 31–4 — Reserved, should be cleared. 3 M3 Master 3 Priority Register Enable 2 M2 Master 2 Priority Register Enable 1 — Reserved, should be cleared. 0 M0 Master 0 Priority Register Enable When enabled, the software programmable value in the arbiter master priority register (XARB_PRI) is used as the priority for the master. When disabled, the master’s priority is determined as follows: Table 10-15.
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Table 10-16. XARB_PRI Field Descriptions Bits Name 31–15 — 14–12 M3P 11 — 10–8 M2P 7–3 — 2–0 M0P Description Reserved, should be cleared. Master 3 Priority Reserved, should be cleared. Master 2 Priority Reserved, should be cleared. Master 0 Priority MCF548x Reference Manual, Rev.
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Chapter 11 General Purpose Timers (GPT) 11.1 Introduction This chapter describes the operation of the MCF548x general purpose timers. 11.1.1 Overview The MCF548x has four general-purpose timers (GPT[0:3]) that are configurable for the following functions: • Input capture • Output capture • Pulse width modulation (PWM) output • Simple GPIO • Internal CPU timer • Watchdog timer (on GPT0 only) Timer modules run off the internal peripheral bus clock. Each timer is associated to a single I/O signal.
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6. Watchdog Timer—This is a special CPU timer mode, available only on GPT0. The user must enable the watchdog timer mode, which is not active upon reset. The terminal count value is programmable. If the counter is allowed to expire, a full reset occurs. To prevent the watchdog timer from expiring, software must periodically write 0xA5 to the GMS0[OCPW] field. This causes the counter to reset. 11.
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Memory Map/Register Definition 11.3.1 GPT Enable and Mode Select Register (GMSn) 31 30 29 R 28 27 26 25 24 OCPW 23 22 0 0 21 20 19 18 0 0 OCT 17 16 ICT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 CE 0 SC OD IEN 0 0 0 0 0 0 0 0 0 0 0 R WDE N W Reset 0 Reg Addr GPIO 0 0 0 0 TMS 0 0 0 MBAR + 0x800 (GMS0), 0x810 (GMS1), 0x820 (GMS2), 0x830 (GSM3) Figure 11-1.
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Table 11-2. GMSn Field Descriptions (Continued) Bits Name Description 15 WDEN Watchdog enable. Enables watchdog operation. A timer expiration causes an internal MCF548x reset. Watchdog operation requires the TMS field be set for internal timer mode and the CE bit to be set. In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW field resets the watchdog timer, preventing it from expiring. As long as the timer is properly configured, the watchdog operation continues.
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Memory Map/Register Definition Table 11-2. GMSn Field Descriptions (Continued) Bits Name Description 8 IEN Interrupt enable. Enables interrupt generation to the CPU for all modes (IC, OC, PWM, and Internal Timer). IEN is not required for watchdog expiration to create a reset. 0 Interrupt disabled 1 Interrupt enabled 7–6 — 5–4 GPIO 3 — 2–0 TMS 11.3.2 Reserved, should be cleared. GPIO mode type. Simple GPIO functionality that can be used simultaneously with the internal timer mode.
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Table 11-3. GCIRn Field Descriptions Bits Name Description 31–16 PRE Prescaler. Prescale amount applied to internal counter (in clocks). Note that in addition to other enable bits and field settings, the PRE field must be written as non-zero to enable counter operation for all modes except the simple GPIO mode. A prescale of 0x0001 means one clock per count increment. 15–0 CNT Count value.
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Memory Map/Register Definition Table 11-4. GPWMn Field Descriptions (Continued) Bits Name 7–1 — 0 LOAD 11.3.4 Description Reserved. Should be cleared. Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with the current count and width settings. If LOAD = 0, new count or width settings are not updated until end of current period. Prescale setting is not part of this process.
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Table 11-5. GSRn Field Descriptions (Continued) Bits Name 2 PWMP PWM end of period occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000 (i.e., timer not enabled). 1 COMP OC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000 (i.e., timer not enabled). 0 CAPT IC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000 (i.e., timer not enabled). 11.4 11.4.
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Chapter 12 Slice Timers (SLT) 12.1 Introduction This chapter explains the operation of the MCF548x slice timers. 12.1.1 Overview Two slice timers are included to provide shorter term periodic interrupts—SLT0 and SLT1. Each timer consists of a 32-bit counter with no prescale. The counters count down from a prescribed value and expire/interrupt when they reach zero.
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12.2.1 SLT Terminal Count Register (STCNTn) 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 TC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R TC W Reset 0 0 0 0 0 Reg Addr 0 0 0 MBAR + 0x900 (STCNT0), + 0x910 (STCNT1) Figure 12-1. SLT Terminal Count Register (STCNTn) Table 12-2. STCNTn Field Descriptions Bits Name Description 31–0 TC Terminal count. GPIO output bit set.
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Memory Map/Register Definition Table 12-3. SCRn Field Descriptions Bits Name 31–27 — 26 RUN Run or wait mode 0 Timer counter expires, but then waits until the timer is cleared (either by writing 1 to the status bit or by disabling and re-enabling the timer), before resuming operation. 1 Timer is enabled, and runs continuously. When the timer counter expires the terminal count value immediately is reloaded and resumes counting down. 25 IEN Interrupt enable.
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12.2.4 R SLT Status Register (SSRn) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 BE ST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MBAR + 0x90C (SSR0), + 0x91C (SSR1) Figure 12-4. SLT Status Register (SSRn) Table 12-5.
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Chapter 13 Interrupt Controller 13.1 Introduction This section details the functionality for the MCF548x interrupt controller.
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and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see Section 3.8.1, “Exception Stack Frame Definition,” for more information on the stack frame format). After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine.
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Introduction 8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt source is hardwired to the given level and represents the mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in the 8-bit interrupt control register (ICRn).
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explicitly cleared in the interrupt service routine. This design provides unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device. Vector number 64 is unused. 13.2 Memory Map/Register Descriptions The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits in size.
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Memory Map/Register Descriptions Table 13-2.
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The IPR is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero. 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 INT[63:48] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R INT[47:32] W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0x700 Figure 13-1. Interrupt Pending Register High (IPRH) Table 13-3.
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Memory Map/Register Descriptions Table 13-4. IPRL Field Descriptions Bits Name Description 31–1 INT[31:1] Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRL bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRL samples the signal generated by the interrupting source. The corresponding IPRL bit reflects the state of the interrupt signal even if the corresponding IMRL bit is set.
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Table 13-5. IMRH Field Descriptions Bits 31–0 31 Name Description INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRH bit reflects the state of the interrupt signal even if the corresponding IMRH bit is set.
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Memory Map/Register Descriptions 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 INTFRC[63:48] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R INTFRC[47:32] W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0x710 Figure 13-5. Interrupt Force Register High (INTFRCH) Table 13-7. INTFRCH Field Descriptions Bits Name Description 31–0 INTFRC Interrupt force.
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13.2.1.4 Interrupt Request Level Register (IRLR) This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. 7 6 5 R 4 3 2 1 0 IRQ 0 W Reset 0 0 0 Reg Addr 0 0 0 0 0 MBAR + 0x718 Figure 13-7. Interrupt Request Level Register (IRLR) Table 13-9. IRQn Field Descriptions Bits Name 7–1 IRQ 0 — 13.2.1.5 Description Interrupt requests.
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Memory Map/Register Descriptions Table 13-10. IACKLPR Field Descriptions (Continued) Bits Name 6–4 LEVEL 3–0 PRI 13.2.1.6 Description Interrupt level. Represents the interrupt level currently being acknowledged. Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged.
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13.2.1.6.1 Interrupt Sources Table 13-12 lists the interrupt sources for each interrupt request line Table 13-12.
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Memory Map/Register Descriptions Table 13-12.
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determines the highest priority within the level, and then responds with the unique vector number corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level and priority number for the level into the IACKLPR, where it may be retrieved later. This interrupt controller design also supports the concept of a software IACK.
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Chapter 14 Edge Port Module (EPORT) 14.1 Introduction The edge port module (EPORT) has seven external interrupt pins, IRQ[7:1]. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 14-1.
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NOTE The GPIO functionality of the external interrupt pins is controlled by the EPORT module. However, some external interrupt signals are muxed with other functions. In this case, the pin’s IRQ functionality must be enabled in the GPIO module’s pin assignment register in order to use the pin’s GPIO function via the EPORT registers. For more information, refer to Chapter 15, “GPIO.” 14.3 Memory Map/Register Definition This subsection describes the memory map and register structure. 14.3.
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Memory Map/Register Definition 14.3.2.1 15 R EPORT Pin Assignment Register (EPPAR) 14 13 EPPA7 12 11 EPPA6 10 9 EPPA5 8 EPPA4 7 6 5 EPPA3 4 3 EPPA2 2 EPPA1 1 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Reg Addr 0 0 0 0 0 0 MBAR + 0xF00 Figure 14-2. EPORT Pin Assignment Register (EPPAR) Table 14-2. EPPAR Field Descriptions Bits Name Description 15–2 EPPAn EPORT pin assignment select fields.
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Table 14-3. EPDDR Field Descriptions Bits Name Description 7–1 EPDDn Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears EPDD7–EPDD1. To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.
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Memory Map/Register Definition Table 14-5. EPDR Field Descriptions Bits Name Description 7–1 EPDx Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD7-EPD1. 0 — 14.3.2.5 Reserved, should be cleared.
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Table 14-7. EPFR Field Descriptions Bits Name 7–1 EPFn 0 — Description Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF7–EPF1. Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect.
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Chapter 15 GPIO 15.1 Introduction Many of the MCF548x pins whose primary function is to serve as the external interface to off-chip resources may also be used for general-purpose digital I/O (GPIO) access and for one or two secondary functions. When used for GPIO purposes, the port x pins (PXXX) indicate which port is being accessed. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
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PORT FBCTL PORT FBCS PORT DMA PORT FEC0H PORT FEC0L PORT FEC1H PORT FEC1L PORT FECI2C BWE[3:0] / PFBCTL[7:4] OE / PFBCTL3 R/W / PFBCTL2 TA / PFBCTL1 ALE / PFBCTL0 PORT PCIBG PCIBG[4:0] / PPCIBG[4:0] PORT PCIBR PCIBR[4:0] / PPCIBR[4:0] FBCS[5:1] / PFBCS[5:1] DACK[1:0] / PDMA[3:2] DREQ[1:0] / PDMA[1:0] PORT PSC3PSC2 FEC0TXCLK / PFEC0H7 FEC0TXEN / PFEC0H6 FEC0TXD0 / PFEC0H5 FEC0COL / PFEC0H4 FEC0RXCLK / PFEC0H3 FEC0RXDV / PFEC0H2 FEC0RXD0 / PFEC0H1 FEC0CRS / PFEC0H0 PORT PSC1PSC0 FEC0TXD3 / PF
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External Pin Description • • • • • • External DMA request and acknowledge (DMA) PCI bus access (PCIGNT, PCIREQ) Ethernet data and control (FEC0H, FEC0L, FEC1H, FEC1L, FECI2C) I2C serial control (FECI2C) DMA serial peripheral interface (DSPI) Programmable serial control (PSC1PSC0 and PSC3PSC2) 15.1.2 Features The MCF548x GPIO module includes these distinctive features: • Control of primary function use of the supported GPIO ports indicated in Section 15.1.
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Table 15-1.
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External Pin Description Table 15-1.
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Table 15-1.
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Memory Map/Register Definition It should be noted from Table 15-1 that there are several cases where a function is mapped to more than one pin. While it is possible to enable the function on more than one pin simultaneously, this type of programming should be avoided for input functions to prevent unexpected behavior. All multiple-pin functions are listed in Table 15-2. Table 15-2.
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Table 15-3.
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Memory Map/Register Definition Most PODR_x registers have full 8-bit implementations, as shown in Figure 15-2. The remaining PODR_x registers use fewer than eight bits. These registers are shown in Figure 15-3, Figure 15-4, Figure 15-5, and Figure 15-6. The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are set. Unimplemented bits always remain cleared. Reading a PODR_x register returns the current values in the register, not the port x pin values.
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7 R 0 6 5 4 3 2 1 0 PODRDSPI6 PODRDSPI5 PODRDSPI4 PODRDSPI3 PODRDSPI2 PODRDSPI1 PODRDSPI0 W Reset 0 1 1 Reg Addr 1 1 1 1 1 MBAR + 0xA0E (PODR_DSPI) Figure 15-3. 7-Bit PODR_DSPI Register (PODR_x) Table 15-5. 7-Bit PODR_DSPI Field Descriptions Bits Name 7 — 6–0 PODRDSPIn 15.3.2.1.
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Memory Map/Register Definition R 7 6 5 4 3 2 1 0 0 0 0 0 PODRx3 PODRx2 PODRx1 PODRx0 0 0 0 0 1 1 1 1 W Reset Reg Addr MBAR + 0xA02 (PORT_DMA), 0xA08 (PORT_FECI2C) Figure 15-5. 4-Bit PODR_DMA and PODR_FECI2C Registers Table 15-7. 4-Bit PODR_DMA and PODR_FECI2C Field Descriptions Bits Name 7–4 — 3–0 PODRxn 15.3.2.1.
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Most PDDR_x registers have a full 8-bit implementation, as shown in Figure 15-7. The remaining PDDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-8, Figure 15-9, Figure 15-10, and Figure 15-11. The PDDR_x registers are read/write. At reset, all bits in the PDDR_x registers are cleared. Setting any bit in a PDDR_x register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x register configures the corresponding pin as an input. 15.3.2.2.
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Memory Map/Register Definition R 7 6 5 4 3 2 1 0 0 DDDSP 6 DDDSP5 DDDSP4 DDDSPI3 DDDSPI2 DDDSP1 DDDSP0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xA1E (PDDR_DSPI) Figure 15-8. 7-Bit PDDR_DSPI Data Direction Register Table 15-10. 7-Bit PDDR_DSPI Field Descriptions Bits Name 7 — 6–0 DDDSPn 15.3.2.2.
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R 7 6 5 4 3 2 1 0 0 0 0 0 DDx3 DDx2 DDx1 DDx0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xA12 (PDDR_DMA), 0xA18 (PDDR_FECI2C) Figure 15-10. 4-Bit PDDR_DMA and PDDR_FECI2C Registers Table 15-12. 4-Bit PDDR_DMA and PDDR_FECI2C Field Descriptions Bits Name 7–4 — 3–0 DDxn 15.3.2.2.
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Memory Map/Register Definition Most PPDSDR_x registers have a full 8-bit implementation, as shown in Figure 15-12. The remaining PPDSDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-13, Figure 15-14, Figure 15-15, and Figure 15-16. The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current pin states. Reading a PPDSDR_x register returns the current state of the port x pins.
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R 7 6 5 4 3 2 1 0 0 PPDx6 PPDx5 PPDx4 PPDx3 PPDx2 PPDx1 PPDx0 PSDx6 PSDx5 PSDx4 PSDx3 PSDx2 PSDx1 PSDx0 W Reset 1 0 1 P 1 P Reg Addr 1 P P 1 1 P P P1 MBAR + 0xA2E (PPDSDR_DSPI) 1 P = the current pin state. Figure 15-13. 7-Bit Port Pin Data / Set Data Registers Table 15-15. 7-Bit PPDSDR_DSPI Field Descriptions Bits Name 7 — 6–0 PPDxn PPDSDR_DSPI pin data. This is Read-only. 0 PDSPIn pin state is low 1 PDSPIn pin state is high PSDxn PPDSDR_DSPI set data.
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Memory Map/Register Definition Table 15-16. 5-Bit PPDSDR_PCIBG and PPDSDR_PCIBR Field Descriptions (Continued) Bits Name 4–0 PPDxn PPDSDR_PCIBG and PPDSDR_PCIBR pin data. This is Read-only. 0 PPCIBGn or PPCIBRn pin state is low 1 PPCIBGn or PPCIBRn pin state is high PSDxn PPDSDR_PCIBG and PPDSDR_PCIBR set data. 0 No effect 1 Corresponding PODR_PCIBGn or PODR_PCIBRn bit is set 15.3.2.3.
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R 7 6 5 4 3 2 1 0 0 0 PPDx5 PPDx4 PPDx3 PPDx2 PPDx1 0 PSDx5 PSDx4 PSDx3 PSDx2 PSDx1 W Reset 0 1 0 P Reg Addr 1 P 1 P 1 P P1 0 MBAR + 0xA21 (PDDSDR_FBCS) 1 P = the current pin state. Figure 15-16. 5-Bit PDDSDR_FBCS Register Table 15-18. 5-Bit PDDSDR_FBCS Field Descriptions Bits Name 7–6 — 5–1 PPDxn PDDSDR_FBCS pin data. This is Read-only. 0 PFBCSn pin state is low 1 PFBCSn pin state is high PSDxn PDDSDR_FBCS set data.
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Memory Map/Register Definition 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W CLRx7 CLRx6 CLRx5 CLRx4 CLRx3 CLRx2 CLRx1 CLRx0 0 0 0 0 0 0 0 0 Reset Reg MBAR + 0xA30 (PCLRR_FBCTL), 0xA34 (PCLRR_FEC0H), 0xA35 (PCLRR_FEC0L), 0xA36 (PCLRR_FEC1H), Addr 0xA37 (PCLRR_FEC1L), 0xA3C (PCLRR_PSC3PSC2), 0xA3D (PCLRR_PSC1PSC0) Figure 15-17. 8-Bit Port Clear Output Data Registers Table 15-19. 8-Bit PCLRR_x Field Descriptions Bits Name 7–0 CLRxn 15.3.2.4.
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R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PCLRRx4 PCLRRx3 PCLRRx2 PCLRRx1 PCLRRx0 0 0 0 0 0 W Reset 0 0 Reg Addr 0 MBAR + 0xA39 (PCLRR_PCIBG) and 0xA3A (PCLRR_PCIBR) Figure 15-19. 5-Bit PCIBG and PCIBR Clear Output Data Register Table 15-21. 5-Bit PCLRR_PCIBG and PCLRR_PCIBR Field Descriptions Bits Name 7–5 — 4–0 PCLRRxn 15.3.2.4.
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Memory Map/Register Definition R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 CLRFB5 CLRFB4 CLRFB3 CLRFB2 CLRFB1 0 0 0 0 0 W Reset 0 0 Reg Addr 0 MBAR + 0xA31 (PCLRR_FBCS) Figure 15-21. 5-Bit FlexBus Clear Output Data Register Table 15-23. 5-Bit PCLRR_FBCS Field Descriptions Bits Name 7–6 — 5–1 CLRFBn 0 — 15.3.2.
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Table 15-24. PAR_FBCTL Field Descriptions (Continued) Bits Name 12 Description PAR_BWE2 The PAR_BWE bit configures the BE2/BWE2 pin for its primary function or general purpose I/O. 0 BE2/BWE2 pin configured for general purpose I/O (PFBCTL6) 1 BE2/BWE2 pin configured for FlexBus BE2/BWE2 or TSIZ0 function. The function chosen depends on the reset configuration. 11 — Reserved, should be cleared.
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Memory Map/Register Definition Table 15-25. PAR_FBCS Field Descriptions Bits Name 7–6 — 5–1 PAR_CSn 0 — 15.3.2.7 Description Reserved, should be cleared. The PAR_CSn bit configures the FBCSn pin for its primary function or general purpose I/O. 0 FBCSn pin configured for general purpose I/O (PFBCS[5:1]) 1 FBCSn pin configured for FlexBus FBCSn function Reserved, should be cleared. DMA Pin Assignment Register (PAR_DMA) The PAR_DMA register controls the function of the four MCF548x DMA pins.
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15 14 13 12 11 10 9 8 7 6 R PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_E1MDIO PAR_E1MDC E07 E0MII E0MDIO E0MDC E17 E1MII W Reset 0 0 0 Reg Addr 0 0 0 1 1 1 1 5 4 0 0 0 0 3 2 1 PAR_ PAR_ PAR_ PAR_ SDA SCL IRQ6 IRQ5 0 0 1 MBAR + 0xA44 (PAR_FECI2CIRQ) Figure 15-25. FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) Table 15-27. PAR_FEC/I2C/IRQ Field Descriptions Bits Name Description 15 PAR_E07 FEC0 7-wire mode pin assignment.
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Memory Map/Register Definition Table 15-27. PAR_FEC/I2C/IRQ Field Descriptions (Continued) Bits Name 3 PAR_SDA SDA Pin Assignment. Configures the SDA pin for its primary function or general purpose I/O. 0 SDA pin configured for general purpose input (PFECI2C1) 1 SDA pin configured for SDA function 2 PAR_SCL SCL Pin Assignment. Configures the SCL pin for its primary function or general purpose I/O.
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Table 15-28. PAR_PCIBG Field Descriptions (Continued) Bits Name Description 5–4 PAR_ PCIBG2 PCIBG2 pin assignment. Configures the PCIBG2 pin for one of its primary functions or GPIO. 0X PCIBG2 pin configured for general purpose I/O (PPCIGNT2) 10 PCIBG2 pin configured for GP timer TOUT2 function 11 PCIBG2 pin configured for PCIBG2 function 3–2 PAR_ PCIBG1 PCIBG1 pin assignment. Configures the PCIBG1 pin for one of its primary functions or GPIO.
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Memory Map/Register Definition Table 15-29. PAR_PCIBR Field Descriptions (Continued) Bits Description Name 3–2 PAR_PCIBR1 PCIBR1 Pin Assignment. Configures the PCIBR1 pin for one of its primary functions or GPIO. 0X PCIBR1 pin configured for general purpose I/O (PPCIREQ1) 10 PCIBR1 pin configured for GP timer TIN1 function 11 PCIBR1 pin configured for PCIBR1 function 1–0 PAR_PCIBR0 PCIBR0 Pin Assignment. Configures the PCIBR0 pin for one of its primary functions or GPIO.
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15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2) The PAR_PSC2 register controls the functions of the PSC2 pins. The PAR_PSC2 register is read/write. 7 R 6 5 PAR_CTS2 4 PAR_RTS2 3 2 1 0 PAR_RXD2 PAR_TXD2 0 0 0 0 0 0 W Reset 0 0 Reg Addr 0 0 MBAR + 0xA4D (PAR_PSC2) Figure 15-29. PSC2 Pin Assignment Register (PAR_PSC2) Table 15-31. PAR_PSC2 Descriptions Bits Name Description 7–6 PAR_CTS2 PSC2CTS pin assignment.
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Memory Map/Register Definition 7 R 6 5 PAR_CTS1 4 PAR_RTS1 3 2 PAR_RXD1 PAR_TXD1 1 0 0 0 0 0 W Reset 0 0 0 Reg Addr 0 0 0 MBAR + 0xA4E (PAR_PSC1) Figure 15-30. PSC1 Pin Assignment Register (PAR_PSC1) Table 15-32. PAR_PCS1 Descriptions Bits Name Description 7–6 PAR_CTS1 PSC1CTS pin assignment. Configures the PSC1CTS pin for one of its primary functions or general purpose I/O.
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Table 15-33. PAR_PCS0 Descriptions Bits Name Description 7–6 PAR_CTS0 PSC0CTS pin assignment. Configures the PSC0CTS pin for one of its primary functions or general purpose I/O. 0X PSC0CTS pin configured for general purpose I/O (PPSC1PSC03) 10 PSC0CTS pin configured for PSC0BCLK function 11 PSC0CTS pin configured for PSC0CTS function 5–4 PAR_RTS0 PSC0RTS pin assignment. Configures the PSC0RTS pin for one of its primary functions or general purpose I/O.
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Memory Map/Register Definition Table 15-34. PAR_DSPI Descriptions (Continued) Bits Name Description 11–10 PAR_CS3 DSPICS3 pin assignment. Configures the DSPICS3 pin for its primary function or general purpose I/O. 00 DSPICS3 pin configured for general purpose I/O (PDSPI5) 01 DSPICS3 pin configured for FlexCAN CANTX1 10 DSPICS3 pin configured for GP timer TOUT3 function 11 DSPICS3 pin configured for DSPICS3 function 9–8 PAR_CS2 DSPICS2 pin assignment.
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Table 15-35. PAR_TIMER Descriptions Bits Name 7–6 — 5–4 PAR_TIN3 3 2–1 0 Description Reserved, should be cleared. TIN3 pin assignment.
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Functional Description (PPDSDR_x) to monitor and control the state of its pins. Data written to a PODR_x register is stored and then driven to the corresponding port x pins configured as outputs. Reading a PODR_x register returns the current state of the register regardless of the state of the corresponding pins. Reading a PPDSDR_x register returns the current state of the corresponding pins when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.
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MCF548x Reference Manual, Rev.
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Part III On-Chip Integration Part III describes on-chip integration for the MCF548x device. It includes descriptions of the system SRAM, SDRAM controller, PCI, FlexBus interface, FlexCAN, SEC cryptography accelerator, and JTAG. Contents Part III contains the following chapters: • Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM implementation. It covers general operations, configuration, and initialization.
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MCF548x Reference Manual, Rev.
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Chapter 16 32-Kbyte System SRAM 16.1 Introduction This chapter explains the operation of the MCF548x 32-Kbyte system SRAM. 16.1.1 Block Diagram The system SRAM is organized as four 8-Kbyte banks, each organized as 2048 × 32-bits. The four banks occupy a contiguous block of memory but can be optionally interleaved on long-word boundaries. When configured for interleaved access, each bank contains the data for long word address modulo {bank #} (e.g.
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The system SRAM contents always reside at MBAR + 0x0001 0000; therefore, it can be relocated by changing the MBAR contents. 16.1.2 Features The 32-Kbyte system SRAM is intended primarily as a fast scratch memory and data buffer for DMA and SEC processing, and as memory accessed through the shared bus by all system masters.
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Memory Map/Register Definition Table 16-1. System SRAM Memory Map (Continued) Address (MBAR + ) Name Byte 0 Byte 1 Byte 2 Byte 3 Access 0x1_0000– 0x1_7FFC SRAM Contents 0x1_FFCC Transfer Count Configuration Register - DMA Write Channel TCCRDW R/W 0x1_FFD0 Transfer Count Configuration Register - SEC TCCRSEC R/W 16.2.1 R/W System SRAM Configuration Register (SSCR) This register is used to define the base address of the system SRAM and whether to interleave the banks.
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16.2.2 Transfer Count Configuration Register (TCCR) This register is used to configure the allocated maximum transfer count for each bank for the following masters: the ColdFire core, DMA, SEC, or PCI. This occurs as they access memory through the shared system bus. The DMA and the SEC can access the system SRAM either via the system bus or via their dedicated ports. Refer to sections 16.2.3 through 16.2.5.
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Memory Map/Register Definition 16.2.3 Transfer Count Configuration Register—DMA Read Channel (TCCRDR) This register is used to configure the allocated maximum transfer count for each bank for the DMA read channel as it accesses SRAM directly, without going through the system bus.
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16.2.4 Transfer Count Configuration Register—DMA Write Channel (TCCRDW) This register is used to configure the allocated maximum transfer count for each bank of the DMA write channel as it accesses SRAM directly, without going through the system bus.
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Memory Map/Register Definition 16.2.5 Transfer Count Configuration Register—SEC (TCCRSEC) This register is used to configure the allocated maximum transfer count for each bank for the SEC as it accesses SRAM directly, without going through the system bus.
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16.3 Functional Description The system SRAM decodes the addresses for all four banks to determine which master is trying to access which bank. The system SRAM module provides a bus arbitration mechanism for granting access of each bank to each master. All masters simply request a data transfer and the SRAM grants a specified cycle count to the appropriate master. The arbitration is overlapped with the address phase of SRAM transfers and therefore imposes no performance penalty or overhead.
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Chapter 17 FlexBus 17.1 Introduction This chapter describes data transfer operations, error conditions, and reset operations. It describes transfers initiated by the MCF548x and includes detailed timing diagrams showing the interaction of signals in supported bus operations. NOTE Unless otherwise noted, in this chapter the term ‘clock’ refers to the CLKIN used for the bus. 17.1.
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17.2 Byte Lanes Figure 17-1 shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to AD[31:24] (BE/BWE0). A longword transfer takes four transfers on AD[31:24], starting with the MSB and going to the LSB.
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External Signals External Device / Peripheral DATA[31:Y] AD[31:0] FlexBus Address ADDR[X:0] Latch Logic ALE Interface ALE Controller R/W R/W TSIZ[1:0] SIZ[1:0] TBST BURST BE/BWE[3:0] BE/BWE[3:0] OE OE TA TA FBCSx CS Figure 17-2. Multiplexed FlexBus Implementation 17.4 External Signals This section describes the external signals that are involved in data transfer operations. Table 17-1 summarizes the MCF548x FlexBus signals. Table 17-1.
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17.4.1 Chip-Select (FBCS[5:0]) The chip-select signal indicates which device is being selected. A particular chip-select asserts when the transfer address is within the device’s address space as defined in the base and mask address registers, see Section 17.5.2, “Chip-Select Registers.” 17.4.2 Address/Data Bus (AD[31:0]) The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a bus cycle (address phase).
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External Signals For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows: • If bursting is used, TSIZ[1:0] is driven to the size of transfer. • If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port size. Table 17-2.
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17.5 Chip-Select Operation Each chip-select has a dedicated set of the following registers for configuration and control: • Chip-select address registers (CSARn) control the base address space of the chip-select. See Section 17.5.2.1, “Chip-Select Address Registers (CSAR0–CSAR5).” • Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 17.5.2.2, “Chip-Select Mask Registers (CSMR0–CSMR5).
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Chip-Select Operation Table 17-4. AD[2]/AA Automatic Acknowledge of Boot FBCS0 AD[2]/AA Boot FBCS0 AA Configuration at Reset 0 Disabled 1 Enabled with 63 wait states Table 17-5. AD[1:0]/PS[1:0], Port Size of Boot FBCS0 17.5.2 AD[1:0]/PS[1:0] Boot FBCS0 Port Size at Reset 00 32-bit port 01 8-bit port 1x 16-bit port Chip-Select Registers The following tables describe in detail the registers and bit meanings for configuring chip-select operation.
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Table 17-6.
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Chip-Select Operation 17.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5) CSMRn, Figure 17-4, are used to specify the address mask and allowable access types for the respective chip-selects.
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17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5) Each CSCRn, Figure 17-5, controls the auto acknowledge, address setup and hold times, port size, burst capability, and activation of each chip-select. Note that to support the global chip-select, FBCS0, the CSCR0 reset values differ from the other CSCRs. FBCS0 allows address decoding for boot ROM before system initialization.
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Chip-Select Operation Table 17-9. CSCRn Field Descriptions (Continued) Bits Name Description 19–18 RDAH Read Address Hold or (Deselect). This field controls the address and attribute hold time after the termination during a read cycle that hits in the chip-select address space. The hold time only applies at the end of a transfer. Therefore, a burst transfer only has a hold time added after the last bus cycle. RDAH = 00; Hold address and attributes one cycle after FBCSn negates on reads.
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Table 17-9. CSCRn Field Descriptions (Continued) Bits Name Description 3 BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each FBCSn. 0 Break data larger than the specified port size into individual port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports and word writes to 8-bit ports. 2–0 — 17.6 17.
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Functional Description Byte Select BE/BWE0 BE/BWE1 BE/BWE2 BE/BWE3 Processor External Data Bus AD[31:24] AD[23:16] AD[15:8] AD[7:0] 32-Bit Port Memory Byte 0 Byte 1 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 8-Bit Port Memory Byte 2 Byte 3 Driven with address values Byte 0 Byte 1 Driven with address values Byte 2 Byte 3 Figure 17-6. Connections for External Memory Port Sizes 17.6.
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4. FBCSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. 17.6.4.1 Data Transfer Cycle States The data transfer operation in the MCF548x is controlled by an on-chip state machine. The state transition diagram for basic read and write cycles is shown in Figure 17-7. Next Cycle S0 Wait States S3 S1 S2 Figure 17-7.
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Functional Description 17.6.5 17.6.5.1 FlexBus Timing Examples Basic Read Bus Cycle During a read cycle, the MCF548x receives data from memory or from a peripheral device. Figure 17-8 is a read cycle flowchart. NOTE Throughout this chapter AD[X:0] is used to indicate an address bus that can be 32-, 24-, or 16-bits in width. AD[31:Y] is a data bus that can be 32-, 16-, or 8-bits wide. MCF548X System 1. Set R/W to read. 2. Place address on AD[31:0]. 3. Assert ALE. 1. Decode address. 1. Negate ALE. 2.
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S0 S1 S2 S3 CLK ADDR[X:0] AD[X:0] A[31:Y] AD[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-9. Basic Read Bus Cycle 17.6.5.2 Basic Write Bus Cycle During a write cycle, the MCF548x sends data to memory or to a peripheral device. The write cycle flowchart is shown in Figure 17-10. NOTE Throughout this chapter AD[X:0] is used to indicate an address bus that can be 32-, 24-, or 16-bits in width. AD[31:Y] is a data bus that can be 32-, 16-, or 8-bits wide. MCF548X System 1.
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Functional Description The write cycle timing diagram is shown in Figure 17-11. S0 S1 S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-11. Basic Write Bus Cycle 17.6.5.3 Bus Cycle Multiplexing This section shows timing diagrams for various port size scenarios. Figure 17-12 illustrates the basic word read transfer to a 16-bit device with no wait states. The address is driven on the full AD[31:0] bus in the first clock.
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S0 S1 S2 S3 CLK AD[31:24] A[31:24] D[15:8] AD[23:16] A[23:16] D[7:0] AD[15:8] ADDR[15:8] AD[7:0] ADDR[7:0] R/W ALE 10 TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-12. Single Word Read Transfer with Muxed 32-A / 16-D or Non-Muxed 16-A / 16-D Figure 17-13 shows the similar configuration for a write transfer. The data is driven from the second clock on AD[31:16].
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Functional Description Figure 17-14 illustrates the basic byte read transfer to an 8-bit device with no wait states. The address is driven on the full AD[31:0] bus in the first clock. The MCF548x tristates AD[31:24] on the second clock and continues to drive address on AD[23:0] throughout the bus cycle. The external device returns the read data on AD[31:24], and may tristate the data line or continue to drive the data one clock after TA is sampled asserted.
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S0 S1 S2 S3 CLK AD[31:24] A[31:24] DATA[7:0] AD[23:16] ADDR[23:16] AD[15:8] ADDR[15:8] AD[7:0] ADDR[7:0] R/W ALE 01 TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-15. Single Byte Write Transfer with Muxed 32-A / 8-D or Non-Muxed 24-A / 8-D Figure 17-16 depicts a longword read through a 32-bit device. Notice that when the device port size is 32 bits, the only mode the bus supports is multiplexing address and data lines.
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Functional Description Figure 17-17 illustrates the longword write to a 32-bit device. S0 S1 S2 S3 CLK AD[31:24] A[31:24] DATA[31:24] AD[23:16] A[23:16] DATA[23:16] AD[15:8] A[15:8] DATA[15:8] AD[7:0] A[7:0] DATA[7:0] R/W ALE TSIZ[1:0] 00 FBCSn, BE/BWEn OE TA Figure 17-17. Longword Write Transfer with Muxed 32-A / 32-D 17.6.5.
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S0 S1 S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-18. Basic Read Bus Cycle (No Wait States) S0 S1 S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-19.
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Functional Description S0 S1 WS S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-20. Read Bus Cycle (One Wait State) S0 S1 WS S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-21. Write Bus Cycle (One Wait State) 17.6.5.4.
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S0 AS S1 S2 S3 CLK ADDR[X:0] AD[X:0] A[31:Y] AD[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-22. Read Bus Cycle with Two Clock Address Setup (No Wait States) S0 AS S1 S2 S3 CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-23. Write Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, there is also a programmable address hold option for each chip select.
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Functional Description S0 S1 S2 S3 AH CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-24. Read Cycle with Two Clock Address Hold (No Wait States) S0 S1 S2 S3 AH CLK ADDR[X:0] AD[X:0] AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-25. Write Cycle with Two Clock Address Hold (No Wait States) Figure 17-26 shows a bus cycle that uses address setup, wait states, and address hold.
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S0 AS S1 WS S2 S3 AH CLK ADDR[X:0] AD[X:0] A[31:Y] AD[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn OE TA Figure 17-26. Write Cycle with Two Clock Address Setup and Two Clock Hold (One Wait State) 17.6.6 Burst Cycles The MCF548x can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. The initiation of a burst cycle is encoded on the size pins.
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Functional Description NOTE Line-sized transfers requested by the core or cache are broken up into four individual longword transfers, but the DMA can request line-sized transfers when the read line or combine write flags are set. See Section 24.4.9, “Line Buffers,” for more information. CSCRs are used to enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW].
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S0 S1 S2 S2 S2 S2 S3 CLK ADDR[23:0] AD[23:0] AD[31:24] A[31:24] DATA DATA DATA DATA R/W ALE 00 TSIZ[1:0] FBCSn, BE/BWEn TBST OE TA Figure 17-28. Longword Write Burst to 8-Bit Port 3-1-1-1 (No Wait States) Figure 17-29 shows a longword read through an 8-bit device with burst inhibited. The transfer results in four individual transfers. Notice that the transfer size is driven at longword (2’b00) during the first transfer and at byte (2’b01) during the next three transfers.
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Functional Description Figure 17-30 shows a longword write through an 8-bit device with burst inhibited. The transfer results in four individual transfers. Notice that the transfer size is driven at longword (2’b00) during the first transfer and at byte (2’b01) during the next three transfers.
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Figure 17-31 illustrates a write burst transfer with one wait state. S0 S1 WS S2 WS/SWS S2 WS/SWS S2 WS/SWS S2 S3 CLK ADDR[23:0] AD[23:0] A[31:24] AD[31:24] DATA DATA DATA DATA R/W ALE 00 TSIZ[1:0] FBCSn, BE/BWEn TBST OE TA Figure 17-32. Longword Write Burst to 8-Bit Port 4-2-2-2 (One Wait State) If address setup and hold are used, only the first and last beat of the burst cycle will be affected as shown in Figure 17-33.
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Functional Description S0 AS S1 S2 S2 S2 S2 S3 AH CLK AD[23:0] AD[31:24] ADDR[23:0] A[31:24] DATA DATA DATA DATA R/W ALE 11 TSIZ[1:0] FBCSn, BE/BWEn OE TBST TA Figure 17-34. Longword Write Burst to 8-Bit Port 4-1-1-1 (Address Setup and Hold) 17.6.7 Misaligned Operands Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned.
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31 24 23 16 15 8 7 0 A[2:0] Transfer 1 –– –– –– Byte 0 001 Transfer 2 Byte 0 –– –– — 100 Figure 17-36. Example of a Misaligned Word Transfer (32-Bit Port) 17.6.8 Bus Errors The MCF548x has no bus monitor. If the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can be terminated by asserting TA or by using the software watchdog timer.
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Chapter 18 SDRAM Controller (SDRAMC) 18.1 Introduction This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general overview and includes a description of signals involved in SDRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous DRAM operations.
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18.2.3 Block Diagram Column addr[29:4] Address Input MUX Bank Row Column Address Pipeline Latches Bank Row Address Output MUX SDADDR[12:0] SDBA[1:0] Select SDCS[3:0] RAS addr[1:3] SDRAM Controller State Machine CAS SDWE SDDQS SDCLK[1:0] SDCLK[1:0] SDCKE SDDM tsiz[1:0], tbst datain[63:0] dataout[63:0] Write Data Buffer SDDATA[31:0] Read Data Buffer SDDATA[31:0] Figure 18-1. SDRAM Controller Block Diagram 18.3 18.3.
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External Signal Description 18.3.4 SDRAM Row Address Strobe (RAS) This output is the SDRAM synchronous row address strobe. 18.3.5 SDRAM Column Address Strobe (CAS) This output is the SDRAM synchronous column address strobe. 18.3.6 SDRAM Chip Selects (SDCS[3:0]) These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one SDCS line for each memory block (the MCF548x supports up to four SDRAM memory blocks). 18.3.
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18.3.12 SDRAM Clock Enable (SDCKE) This output is the SDRAM clock enable. SDCKE negates to put the SDRAM into low-power, self-refresh mode. 18.3.13 SDR SDRAM Data Strobe (SDRDQS) This is connected to SDDQS inputs. It is used in SDR mode only. 18.3.14 SDRAM Memory Supply (SDVDD) These pins supply positive power to the SDRAM module. SDVDD should be connected to +2.5V for DDR operation and +3.3V for SDR. 18.3.
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Interface Recommendations Table 18-2.
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18.4.2 SDRAM SDR Connections Figure 18-2 shows a block diagram of the connections between the MCF548x and SDR SDRAM components. SDR design requires special timing consideration for the SDDQS[3:0] signals. For reads from DDR SDRAMs, the memory will drive the DQS pins so that the data lines and DQS signals have concurrent edges. The MCF548x SDRAMC is designed to latch data 1/4 clock after the SDDQS[3:0] edge. For DDR SDRAM, this ensures that the latch time is in the middle of the data valid window.
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Interface Recommendations DDR SDRAM MCF548X SDADDR[12:0] A[12:0] SDBA[1:0] BA[1:0] SDDATA[31:0] DQ[31:0] SDCSn CS RAS CAS SDWE RAS CAS WE SD_CLK[1:0] SD_CLK[1:0] SD_CKE CLK CLK CKE SDDM[3:0] SDDQS[3:0] DM[3:0] DQS[3:0] Figure 18-3. MCF548x Connections to DDR SDRAM 18.4.4 SDRAM DDR DIMM Connections There is a JEDEC standard for a 100-pin DDR DIMM with a 32-bit wide data bus. This DIMM standard was designed specifically to support 32-bit processors.
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DDR SDRAM MCF548X SDADDR[12:0] A[12:0] SDBA[1:0] BA[1:0] SDDATA[31:0] DQ[31:0] SDCS[1:0] S[1:0] RAS CAS SDWE RAS CAS WE SDCLK[1:0] SDCLK[1:0] SDCKE CLK[1:0] CLK[1:0] CKE SDDM[3:0] DM[3:0] SDDQS[3:0] DQS[3:0] SCL SCL SDA SDA SDVDD SA0 Figure 18-4. MCF548x Connections to 100-pin DDR SDRAM DIMM 18.4.
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SDRAM Overview 18.4.5.1 Termination Example Figure 18-5 shows the recommended termination circuitry for DDR SDRAM signals. VREF 50 Ω DDR SDRAM MCF548X 25 Ω Figure 18-5. MCF548x DDR SDRAM Termination Circuit 18.5 18.5.1 SDRAM Overview SDRAM Commands When an internal bus master accesses SDRAM address space, the memory controller generates the corresponding SDRAM command. Table 18-3 lists SDRAM commands supported by the memory controller. Table 18-3.
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Table 18-3. SDRAM Commands (Continued) Function Symbol CKE CS RAS CAS WE BA[1:0] AP/C MD Other A Self-Refresh SREF H→L L L L H X X X Power-Down PDWN H→L H X X X X X X H = High L = Low V = Valid X = Don’t care Many commands require a delay before the next command may be issued; sometimes the delay depends on the type of the next command. These delay requirements are managed by the values programmed in the memory controller configuration registers (SDCFG1, SDCFG2). 18.5.1.
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SDRAM Overview issue a PALL command to close the active row. Then the SDRAMC issues ACTV to activate the necessary row and bank for the new access, followed finally by the WRITE command. The PALL and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going data movement. With both SDR and DDR memory, a read command can be issued overlapping the masked beats at the end of a previous single write of the same SDCS; the read command aborts the remaining (unnecessary) write beats.
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18.5.1.5.1 Mode Register Definition Figure 18-6 shows the mode register definition. Note that this is the SDRAM’s mode register not the SDRAMC’s mode/extended mode register (SDMR) defined in Section 18.7.3, “SDRAM Mode/Extended Mode Register (SDMR).” Field BA1 BA0 0 0 A11 A10 A9 A8 A7 A6 OP_MODE A5 A4 CASL A3 A2 BT A1 A0 BLEN Figure 18-6. Mode Register Table 18-4. Mode Register Field Descriptions Address Line Description BA[1:0] Bank Address.
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SDRAM Overview Table 18-5. Extended Mode Register Field Descriptions Address Line Description BA[1:0] Bank Address. 00 Does not select the extended mode register 01 Selects the extended mode register 1x Reserved A11–A1 Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can use these bits to implement optional features. Check with SDRAM manufacturer to determine if any optional features have been implemented. For normal operation all bits should be cleared.
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18.5.2.1 SDR Initialization SDR initialization requires the following steps: 1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification. Usually 100µs or 200µs. 2. Initialize the SDRAM drive strength (SDRAMDS) and SDRAM chip select configuration (CSnCFG) registers. 3. Program the SDRAM configuration registers (SDCFG1 and SDCFG2) with the correct delay and timing values. 4. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set.
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Functional Overview 8. Issue a second PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set. The SDCR[REF, and IREF] bits should remain cleared for this step. 9. Refresh the SDRAM. The SDRAM spec should indicate a number of refresh cycles to be performed before issuing an LMR command. Write to the SDCR with the IREF bit set (SDCR[MODE_EN, REF, and IPALL] should be cleared). This will force a refresh of the SDRAM each time the IREF bit is set.
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The SDRAM controller supports all possible XLB transfer sizes. SDRAMs are “burst only” devices; unnecessary beats on the memory bus are masked (write) or discarded (read). The SDRAMC will perform line bursts (32 byte) for all SDRAM access. This requires two beats of 16 bytes on the XLB, or eight beats of 4 bytes (one longword) on the memory bus. The SDRAM controller transfers the critical longword first, followed by the next three sequential longwords.
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Memory Map/Register Definition 18.7.1 R SDRAM Drive Strength Register (SDRAMDS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R SB_E SB_C SB_A 1 1 SB_S SB_D W Reset Reg Addr 1 1 1 1 1 1 1 1 MBAR + 0x04 Figure 18-8. SDRAM Drive Strength Register (SDRAMDS) Table 18-7.
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18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG) 31 30 29 28 27 R 26 25 24 23 22 21 20 CSBA 19 18 17 16 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R CSSZ W Reset Reg Addr 0 0 0 MBAR + 0x20 (CS0CFG), 0x24 (CS1CFG), 0x28 (CS2CFG), 0x2C (CS3CFG) Figure 18-9. SRAM Chip Select Configuration Register (CSnCFG) Table 18-9.
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Memory Map/Register Definition CS3CFG = 94000019 = 64M @ 0x9400 0000-0x97FF FFFF CS4CFG = 8000001b = 256M @ 0x8000 0000-0x8FFF FFFF CS5CFG = 00000000 = disable This gives 400 Mbyte total memory, at 0x8000 0000-0x98FF FFFF 18.7.3 SDRAM Mode/Extended Mode Register (SDMR) The SDMR, shown in Figure 18-10, is used to write to the mode and extended mode registers that physically reside within in the SDRAM chips. These registers must be programmed during SDRAM initialization. See Section 18.5.
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18.7.4 SDRAM Control Register (SDCR) The SDCR, shown in Figure 18-11, controls SDRAMC operating modes including the refresh count and address line muxing. 31 30 R MODE CKE _EN W 29 28 27 26 DDR REF 0 0 25 24 MUX Reset 23 22 AP DRIV E 21 20 19 18 17 16 RCNT Uninitialized R 15 14 13 12 0 0 0 0 11 10 9 8 DQS_OE 7 6 5 4 3 2 1 0 0 0 0 BUFF 0 IREF IPALL 0 W Reset Uninitialized Reg Addr MBAR + 0x0104 Figure 18-11.
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Memory Map/Register Definition Table 18-11. SDCR Field Descriptions (Continued) Bits Name Description 22 DRIVE Drive rule selection. 0 Tri-state except to write. SDDATA and SDDQS are only driven when necessary to perform a write. 1 Drive except to read. SDDATA and SDDQS are only tristated when necessary to perform a read. When not being driven for a write cycle, SDDATA hold the most recent value and SDDQS are driven low.
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The minimum values of certain fields can be different for SDR and DDR SDRAM, even if the data sheet timing is the same, because: • In SDR mode, the memory controller counts the delay in SDCLK • In DDR mode, the memory controller counts the delay in SDCLK × 2 SDCLK—memory controller clock—is the speed of the SDRAM interface and is equal to the internal bus clock.
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Memory Map/Register Definition Table 18-12. SDCFG1 Field Descriptions (Continued) Bits Name 19 — 18–16 ACT2RW Description Reserved. Should be cleared. Active to Read/Write delay. Active command to any following read or write delay counter. Suggested value = tRCD/SDCLK - 1 (Round up to nearest integer) EXAMPLE: If tRCD = 20ns and SDCLK = 99 MHz 20ns / 10.1 ns = 1.98; round to 2; write 0x1. Note: Count value is in SDCLK periods for both SDR and DDR mode. 15 — 14–12 PRE2ACT Reserved.
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31 30 R 29 28 27 BRD2PRE 26 25 24 23 BWT2RW 22 21 20 19 18 17 16 BL BRD2WT W Reset R Uninitialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x010C Figure 18-13. SDRAM Configuration Register 2 (SDCFG2) Table 18-13. SDCFG2 Field Descriptions Bits 18.8 Name Description 31–28 BRD2PRE Burst Read to Read/Precharge delay. Limiting case is Read to Read.
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SDRAM Example Table 18-14. SDRAM Example Specifications (Continued) Parameter 18.8.1 Specification Write recovery timer (tWR) 15 ns Precharge command to ACTV command (tRP) 15 ns (min) 18ns (max) Auto refresh command period (tRFC) 72ns (min) 75ns (max) Average periodic refresh interval (tREFI) 7.8 µs SDRAM Signal Drive Strength Settings The SDRAMDS should be programmed as shown in Figure 18-14. The settings assume the normal drive strength for 2.5V drive, 7.
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31 30 29 28 27 26 Field 25 24 23 22 21 20 19 18 16 1 0 — BA Setting 17 0000_0000_0000_0000 (hex) 0 15 14 0 13 12 11 Field 10 0 9 8 7 6 0 5 4 3 — 2 CSSZ Setting 0000_0000_0001_1001 (hex) 0 0 1 9 Figure 18-15. SDRAM Example Chip Select 0 Configuration Settings (CS0CFG) This configuration results in a value of SDRAMDS = 0x0000_0019, as described in Table 18-16. Table 18-16.
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SDRAM Example Table 18-17. SDCFG1 Field Descriptions (Continued) Bits Name Setting 23–20 RDLAT 0110 19 — 0 18–16 ACT2RW 010 15 — 0 14–12 PRE2ACT 010 PRE2ACT = tRP/SDCLK - 1 = 18ns/8.3ns - 1 = 2.16 - 1 = 1.16, rounded up to 2 11–8 REF2ACT 1000 REF2ACT = tRFC/SDCLK - 1 = 75ns/8.3ns - 1 = 9 - 1 = 8 7 — 0 6–4 WTLAT 011 0x3 is the recommended value for DDR 3–0 CSSZ 1101 Total size is 64 Mbytes. 2 x 256Mbit = 64Mbytes 18.8.
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31 30 Field MODE CKE _EN 29 28 DDR REF 27 26 25 — 24 MUX Setting 23 22 21 AP DRIVE 20 19 18 17 16 RCNT 1110_0001_0000_1101 (hex) E 15 14 Field 1 13 12 — 11 10 0 9 8 DQS_OE Setting 7 6 D 5 — 4 3 BUFF — 2 1 IREF IPALL 0 — 0000_0000_0000_0010 (hex) 0 0 0 2 Figure 18-18. SDRAM Control Register Settings + MODE_EN and IPALL This configuration results in a value of SDCR = 0xE10D_0002, as described in Table 18-19. Table 18-19.
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SDRAM Example 18.8.6 Set the Extended Mode Register The SDMR should be programmed as shown in Figure 18-19. This step enables the DDR memory’s DLL. 31 Field 30 29 28 27 26 25 BNKAD 24 23 22 21 20 19 OPTION Setting 18 17 16 DLL — CMD 1 0 0100_0000_0000_0001 (hex) 4 15 14 0 13 12 11 10 0 9 8 Field 7 6 1 5 4 3 2 — Setting 0000_0000_0000_0000 (hex) 0 0 0 0 Figure 18-19.
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Table 18-21. SDMR Field Descriptions Bits Name Setting 31–30 BNKAD 00 29–25 OP_MODE 0010 Selects normal operating mode and resets the DLL. 24–22 CASL 010 CAS latency of two clocks. 21 BT 0 20–18 BLEN 011 17 — 0 Reserved. Should be cleared. 16 CMD 1 Initiate the LMR command. 15–0 — 0 Reserved. Should be cleared. 18.8.8 Description 00 selects the mode register. Sequential burst type.
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SDRAM Example Table 18-22. SDCR + MODE_EN and IPALL Field Descriptions (Continued) Bits Name Setting 22 DRIVE 0 21–16 RCNT 001101 15–12 — 0000 Reserved. Should be cleared. 11–8 DQS_OE 0000 0x0 disables drive for all SDDQS pins for now. 7–5 — 000 Reserved. Should be cleared. 4 BUFF 0 0 indicates that a buffered memory module is not being used. 3 — 0 Reserved. Should be cleared. 2 IREF 0 Do not initiate a REF command. 1 IPALL 1 Initiate a PALL command. 0 — 0 Reserved.
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Table 18-23. SDCR + MODE_EN and IREF Field Descriptions (Continued) Bits Name Setting Description 27–26 — 00 Reserved. Should be cleared. 25–24 MUX 01 01 is the MUX setting for a 13 x 9 x 4 memory. See Table 18-2. 23 AP 0 0 sets the auto precharge control bit to A10. 22 DRIVE 0 Data and DQS lines are only driven for a write cycle. 21–16 RCNT 001101 15–12 — 0000 Reserved. Should be cleared. 11–8 DQS_OE 0000 0x0 disables drive for all SDDQS pins for now. 7–5 — 000 Reserved.
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SDRAM Example Table 18-24. SDMR Field Descriptions (Continued) Bits Name Setting Description 21 BT 0 Sequential burst type. 20–18 BLEN 011 Burst length of eight. 17 — 0 Reserved. Should be cleared. 16 CMD 1 Initiate the LMR command. 15–0 — 0 Reserved. Should be cleared. 18.8.11 Enable Automatic Refresh and Lock Mode Register The SDCR should be programmed as shown in Figure 18-24.
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Table 18-25. SDCR + REF Field Descriptions (Continued) Bits Name Setting Description 15–12 — 0000 Reserved. Should be cleared. 11–8 DQS_OE 1111 0xF enables drive for all SDDQS pins. 7–5 — 000 Reserved. Should be cleared. 4 BUFF 0 0 indicates that a buffered memory module is not being used. 3 — 0 Reserved. Should be cleared. 2 IREF 0 Initiate a REF command. 1 IPALL 0 Do not initiate a PALL command. 0 — 0 Reserved. Should be cleared. 18.8.
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SDRAM Example move.l move.l #0x008D0000, d0//Write LMR and clear reset DLL d0, SDMR Enable Auto Refresh and Lock SDMR: move.l move.l #0x710D0F00, d0//Enable auto refresh and clear MODE_EN d0, SDCR MCF548x Reference Manual, Rev.
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MCF548x Reference Manual, Rev.
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Chapter 19 PCI Bus Controller 19.1 Introduction This chapter details the operation of the PCI bus controller for the MCF548x device. The PCI Bus Arbiter is detailed in Chapter 20, “PCI Bus Arbiter Module.” 19.1.1 Block Diagram PCI Arbiter External REQ/GNT Comm Bus Req/Gnt PCI Controller Block XL Bus Slave Bus (IP Bus) Configuration PCI Controller Configuration Interface Master Bus Target Target Interface Master Bus/ Comm Bus Initiator Initiator Interface External PCI Bus Figure 19-1.
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• • • • • • • • • • • • Compatible with PCI 2.2 specification PCI initiator and target operation Fully synchronous design 32-bit PCI address bus PCI 2.2 Type 0 configuration space header Supports the PCI 16/8 clock rule PCI master multichannel DMA or CPU access to PCI bus Ideal transfer rates up to 266 Mbytes/sec. (66 MHz clock, 128 byte buffer) PCI to system bus address translation Target response is medium DEVSEL generation Initiator latency time-outs Automatic retry of target disconnects 19.
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External Signal Description 19.2.3 Device Select (PCIDEVSEL) The PCIDEVSEL signal is asserted active low when the PCI controller decodes that it is the target of a PCI transaction from the address presented on the PCI bus during the address phase. 19.2.4 Frame (PCIFRAME) The PCIFRAME signal is asserted active low by a PCI initiator to indicate the beginning of a transaction. It is deasserted when the initiator is ready to complete the final data phase. 19.2.
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19.2.13 Target Ready (PCITRDY) The PCITRDY signal is asserted active low by the currently addressed target to indicate that it is ready to complete the current data phase. 19.3 Memory Map/Register Definition The MCF548x has several sets of registers that control and report status for the different interfaces to the PCI controller: PCI Type 0 configuration space registers, general status/control registers, and communication subsystem interface registers.
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Memory Map/Register Definition Table 19-2.
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Table 19-2.
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Memory Map/Register Definition 19.3.1.1 Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 Device ID W Reset 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 1 1 R Vendor ID W Reset 0 0 0 1 0 0 0 Reg Addr 0 0 MBAR + 0xB00 Figure 19-2. Device ID/Vendor ID Register (PCIIDR) Table 19-3.
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Table 19-4. PCISCR Field Descriptions Bits Name Description 31 PE Parity error detected. This bit is set when a parity error is detected, even if the PCISCR[PER] is cleared. This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect. 30 SE System error signalled. This bit is set whenever the PCI controller generates a PCI system error on the PCISERR line. This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect.
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Memory Map/Register Definition Table 19-4. PCISCR Field Descriptions (Continued) Bits Name Description 6 PER Parity error response. This bit controls the device’s response to parity errors. 0 The device sets its Parity Error status bit (bit 31) in the event of a parity error, but does not assert PERR. 1 When a parity error is detected, the PCI controller asserts PERR 5 V VGA palette snoop enable. Fixed to 0. This bit indicates that the PCI controller is not VGA compatible.
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Table 19-5. PCICCRIR Field Descriptions Bits Name Description 31–8 Class Code This field is read-only and represents the PCI Class Code assigned to processor. Its value is: 0x06 8000. (Other bridge device). 7–0 Revision ID This field is read-only and represents the PCI Revision ID for this version of the processor. Its value is: 0x00. 19.3.1.
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Memory Map/Register Definition 19.3.1.5 Base Address Register 0 (PCIBAR0)—PCI Dword 4 31 30 29 28 27 26 R 25 24 23 22 21 20 19 18 BAR 0 17 16 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF 0 0 0 0 0 0 0 0 0 0 0 0 0 R RANGE IO/M# W Reset Reg Addr 0 0 0 MBAR + 0xB10 Figure 19-6. Base Address Register 0 (PCIBAR0) Table 19-7.
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19.3.1.6 Base Address Register 1 (PCIBAR1)—PCI Dword 5 31 R 30 BAR1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF 0 0 0 0 0 0 0 0 0 0 0 0 1 R RANGE IO/M# W Reset Reg Addr 0 0 0 MBAR + 0xB14 Figure 19-7. Base Address Register 1 (PCIBAR1) Table 19-8.
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Memory Map/Register Definition All 32 bits of the register are programmable by the slave bus. From the PCI bus, this register can only be read, not written. The reset value is 0x0000_0000 and is accessible at address MBAR + 0xB2C. 19.3.1.9 Expansion ROM Base Address PCIERBAR—PCI Dword C Not implemented. Fixed to 0x0000_0000 at address MBAR + 0xB30. 19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D Not implemented. Fixed to 0x00 at address MBAR + 0xB34. 19.3.1.
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registers are accessed primarily internally as offsets of MBAR, but can also be accessed by an external PCI master if PCI base and target base address registers are configured to access the space. See Section 19.5.2, “Address Maps,” on configuring address windows. 19.3.2.
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Memory Map/Register Definition Table 19-10. PCIGSCR Field Descriptions (Continued) Bits Name Description 13 PEE Parity error interrupt enable. This bit enables CPU Interrupt generation when the PCI Parity Error signal, PCIPERR, is sampled asserted. When enabled and PCIPERR asserts, software must clear the PE status bit to clear the interrupt condition. 12 SEE System error interrupt enable. This bit enables CPU Interrupt generation when a PCI system error is detected on the PCISERR line.
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19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1) 31 30 R Base Address Translation 1 W Reset R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xB68 Figure 19-11.
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Memory Map/Register Definition Table 19-13. PCITCR Field Descriptions Bits Name 31–25 — Reserved, should be cleared. 24 LD Latency rule disable. This control bit applies only when MCF548 is Target. When set, it prevents the PCI Controller from automatically issuing a retry disconnect due to the PCI 16/8 clock rule. This bit should only be set when the XL<->PCI path is not in use. The only transactions that are retried on the XL bus by the PCI are reads.
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Table 19-14. PCIIW0BTAR Field Descriptions Bits Name Description 31–24 Window 0 Base Address One of three base address registers to determine an XL bus hit on PCI. At most, the upper byte of the address is decoded. The Window 0 Address Mask register determines what bits of this register to compare the XL bus address against to generate the hit. The smallest possible Window is a 16-Mbyte block.
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Memory Map/Register Definition 19.3.2.7 31 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) 30 R 29 28 27 26 25 24 23 22 Window 2 Base Address 21 20 19 18 17 16 Window 2 Address Mask W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R Window 2 Translation Address W Reset 0 0 0 0 0 0 0 Reg Addr 0 MBAR + 0xB78 Figure 19-15.
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Table 19-15. PCIIWCR Field Descriptions Bits Name 31–28 — 27–24 Description Reserved, should be cleared. Window 0 Bit[3]—IO/M#. Control[3:0] 0 Window is mapped to PCI memory. 1 Window is mapped to PCI I/O. Bit[2:1]—PCI read command (PRC). If bit[3] is programmed memory, “0”, then these bits are used to determine the type of PCI memory command to issue. See Table 19-57. If bit[3] is set to “1”, the value of these bits is meaningless. 00 PCI Memory Read. 01 PCI Memory Read Line.
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Memory Map/Register Definition Table 19-16. PCIICR Field Descriptions Bits Name Description 31–27 — 26 REE Retry error enable. This bit enables CPU Interrupt generation in the case of Retry Error termination of a transaction. It may be desirable to mask CPU interrupts, but in such a case, software should poll the status bits to prevent a possible lock-up condition. 25 IAE Initiator abort enable. This bit enables CPU Interrupt generation in the case of Initiator Abort termination of a transaction.
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Table 19-17. PCIISR Field Descriptions Bits Name Description 31–27 — Reserved, should be cleared. 26 RE Retry error. This flag is set when the controller ARTRY’s a read on XL bus when retry-terminated by the PCI target or when the Max_Retries limit is reached for a single XL bus write transaction. A CPU interrupt will be generated if PCIICR[RE] bit is set. It is up to application software to clear this bit by writing ‘1’ to it. 25 IA Initiator abort.
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Memory Map/Register Definition Table 19-18. PCICAR Field Descriptions (Continued) Bits Name Description 23–16 Bus Number This register field is an encoded value used to select the target bus of the configuration access. For target devices on the PCI bus connected to MCF548, this field should be set to 0x00. 15–11 Device Number This field is used to select a specific device on the target bus.Section 19.4.4.2, “Configuration Mechanism,” for more information.
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Table 19-19. PCITPSR Field Descriptions Bits Name 31–18 Description Packet_Size Packet_Size [15:2]. The Packet_Size field indicates the number of bytes for the transmit controller to send over PCI. Only bits [15:2] are writable. Only 32-bit data transfers to the FIFO are allowed. Writing to this register also completes a Restart Sequence as long as the Master Enable bit, PCITER[ME], is high and Reset Controller bit, PCITER[RC], is low. 17–16 Packet_Size [1:0] The two low bits are hardwired low.
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Memory Map/Register Definition 19.3.3.1.3 R Tx Transaction Control Register (PCITTCR) 31 30 29 28 27 26 25 24 23 22 21 18 17 16 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W 0 0 0 DI 0 0 0 0 0 0 0 0 0 0 0 0 0 PCI_cmd 20 19 Max_Retries W Reset R Max_Beats W Reset 0 0 Reg Addr 0 MBAR + 0x8408 Figure 19-22. Tx Transaction Control Register (PCITTCR) Table 19-21.
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19.3.3.1.4 R Tx Enables Register (PCITER) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RC RF 0 CM BE 0 0 ME 0 0 FEE SE RE TAE IAE NE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MBAR + 0x840C Figure 19-23. Tx Enables Register (PCITER) Table 19-22.
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Memory Map/Register Definition Table 19-22. PCITER Field Descriptions (Continued) Bits Name Description 21 FEE FIFO error enable. User writes this bit high to enable CPU Interrupt generation in the case of FIFO error termination of a packet transmission. It may be desirable to mask CPU interrupts in the case that multichannel DMA is controlling operation, but in such a case software should poll the status bits to prevent a possible lock-up condition. 20 SE System error enable.
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Table 19-23. PCITNAR Field Descriptions Bits 31–0 19.3.3.1.6 31 Name Description Next_Address This status register contains the next (unwritten) PCI address and is updated at the successful completion of each PCI data beat. It represents a byte address and is updated with the user-written Start_Add value whenever the Start_Add is reloaded. It is intended to be accurate even in the case of abnormal terminations on the PCI bus.
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Memory Map/Register Definition Table 19-25. PCITDCR Field Descriptions Bits Name Description 31–16 Bytes_Done This status register indicates the number of bytes transmitted since the start of a packet. It is updated at the end of each successful PCI data beat. For normally terminated packets the Bytes_Done value and the Packet_Size values will be equal. If Continuous Mode is active, the Bytes_Done value operates the same way.
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Table 19-26. PCITSR Field Descriptions (Continued) Bits Name Description 23 BE3 Bus error type 3. This bit is set whenever a slave bus transaction attempts to write to a Read-Only register. This flag bit is set regardless of the bus error enable bit (BE). If software is polling and wishes to disregard this error it must mask this bit out. No register bit corruption occurs for this (or any other) bus error case. This bit is cleared by writing ‘1’ to it. 22 BE2 Bus error type 2.
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Memory Map/Register Definition 19.3.3.1.9 31 Tx FIFO Data Register (PCITFDR) 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 FIFO_Data_Word W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R FIFO_Data_Word W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0x8440 Figure 19-28. Tx FIFO Data Register (PCITFDR) + Table 19-27.
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Table 19-28. PCITFSR Field Descriptions Bits Name Description 31 IP Illegal Pointer. An address outside the FIFO controller’s memory range has been written to one of the user visible pointers. This bit will cause the FIFO error output to assert unless the IP_MASK bit in the FIFO Controller register is set. Resetting the FIFO will clear this condition and the bit is cleared by writing a one to it. 30 TXW Transmit Wait Condition.
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Memory Map/Register Definition Table 19-29. PCITFCR Field Descriptions Bits Name Description 31–30 — 29 WFR 28-27 — 26–24 GR[2:0] Granularity. Control high “watermark” point at which FIFO negates Alarm condition (i.e., request for data). It represents the number of free bytes times 4. A granularity setting of zero should be avoided because it means the Alarm bit (and the Requestor signal) will not negate until the FIFO is completely full.
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Table 19-30. PCITFAR Field Descriptions Bits Name 31–12 — 11–7 Alarm Description Reserved, should be cleared. Bits 11-7 are hardwired low. 6–0 Bits 6-0 are programmable to control a 128-byte FIFO. User writes these bits to set low level “watermark”, which is the point where FIFO asserts request for multichannel DMA controller data filling. Value is in bytes. For example, with Alarm = 32 (0x20), an alarm condition occurs when the FIFO contains less than 32bytes.
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Memory Map/Register Definition 19.3.3.1.14 Tx FIFO Write Pointer Register (PCITFWPR) R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R WritePtr W Reset Reg Addr 0 0 0 0 MBAR + 0x8454 Figure 19-33. Tx FIFO Write Pointer Register (PCITFWPR) Table 19-32.
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19.3.3.2.1 31 Rx Packet Size Register (PCIRPSR) 30 29 28 27 26 R 25 24 23 22 21 20 19 18 Packet_Size[15:2] 17 16 Packet_Size [1:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset Reg Addr MBAR + 0x8480 Figure 19-34. Rx Packet Size Register (PCIRPSR) Table 19-33.
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Memory Map/Register Definition Table 19-34. PCIRSAR Field Descriptions Bits Name Description 31–0 Start_Add The user writes this register with the desired starting address for the current packet. This is the address which will be first presented on the external PCI bus and then auto-incremented as necessary. Addressing is assumed to be sequential from the start address unless the PCIRTCR[DI] bit is set. This register will not increment as the PCI packet proceeds. 19.3.3.2.
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Table 19-35. PCIRTCR Field Descriptions (Continued) Bits Name 12 FB Description Full burst. This is the full burst bit and it supersedes the Max_Beats setting. Since Max_Beats provides support for up to 8-beat bursts, the Full burst bit should not be set for packets sizes of 8-beats or less. In Full burst mode, the user must program Packets_Size to at least 40 bytes.
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Memory Map/Register Definition Table 19-36. PCIRER Field Descriptions Bits Name Description 31 RC Reset controller. User writes this bit high to put Receive Controller in a reset state. Note that other register bits are not affected. This Reset is intended for recovery from an error condition or to reload the Start Address when Continuous mode is selected.
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Table 19-36. PCIRER Field Descriptions (Continued) Bits Name Description 17 IAE Initiator abort enable. User writes this bit high to enable CPU Interrupt generation in the case of initiator abort error termination of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel DMA is controlling operation, but in such a case software should poll the status bits to prevent a possible lock-up condition. 16 NE Normal termination enable.
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Memory Map/Register Definition 19.3.3.2.6 31 Rx Done Counts Register (PCIRDCR) 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 Bytes_Done W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R Packets_Done W Reset 0 0 0 Reg Addr 0 0 0 0 0 0 MBAR + 0x8498 Figure 19-39. Rx Done Counts Register (PCIRDCR) Table 19-38.
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19.3.3.2.7 R Rx Status Register (PCIRSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 NT BE3 BE2 BE1 FE SE RE TA IA rwc1 rwc1 rwc1 rwc1 rwc1 rwc1 rwc1 rwc1 rwc1 W Reset R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x849C 1 Bits 24-16 are read-write-clear (rwc).
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Memory Map/Register Definition Table 19-39. PCIRSR Field Descriptions (Continued) Bits Name Description 18 RE Retry Error.This bit is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction has performed retries in excess of the setting. An interrupt will be generated by this condition if the PCITER[RE] bit is set. This retry counter is reset at the beginning of each packet, not at the beginning of each transaction.This bit is cleared by writing ‘1’ to it.
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19.3.3.2.9 R Rx FIFO Status Register (PCIRFSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 IP TXW 0 0 0 0 0 0 FAE RXW UF OF FR Full rwc1 rwc1 rwc1 rwc1 W rwc1 Reset R rwc1 17 16 Alarm Empty 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x84C4 1 Bits 31, 30 and 23-20 are read-write-clear (rwc).
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Memory Map/Register Definition Table 19-41. PCIRFSR Field Descriptions (Continued) Bits Name Description 17 Alarm The FIFO is at or above the Alarm “watermark”, as set by the user according to the Alarm and Control registers settings. This is not a sticky bit or error indication. 16 Empty The FIFO is empty. This is not a sticky bit or error condition. 15–0 — Reserved, should be cleared. 19.3.3.2.
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Table 19-42. PCIRFCR Field Descriptions (Continued) Bits Name Description 19 OF_MASK Overflow mask. When this bit is set, the FIFO controller masks the Status Register’s OF bit from generating an error. 18 TXW_MASK Transmit wait condition mask. When this bit is set, the FIFO controller masks the Status Register’s TXW bit from generating an error. (To help with backward compatibility, this bit is asserted at reset.) 17–0 — Reserved, should be cleared. 19.3.3.2.
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Memory Map/Register Definition 19.3.3.2.12 Rx FIFO Read Pointer Register (PCIRFRPR) R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R ReadPtr W Reset Reg Addr 0 0 0 0 MBAR + 0x84D0 Figure 19-45. Rx FIFO Read Pointer Register (PCIRFRPR) Table 19-44.
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Table 19-45. PCIRFWPR Field Descriptions Bits Name 31–7 — 6–0 WritePtr 19.4 Description Reserverd, should be cleared. This value is maintained by the FIFO hardware and is not normally written by the user. It can be adjusted in special cases but will of course disrupt the integrity of the data flow. This value represents the Write address being presented to the FIFO RAM. Functional Description The MCF548x PCI module provides both master and target PCI bus interfaces as shown in Figure 19-1.
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Functional Description Table 19-46. PCI Command Encodings (Continued) 19.4.1.2 PCICXBE[3:0] Command Type 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Basic Transfer Control The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one or more data phases.
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command driven on the PCICXBE bus. In cycle 2, the AD bus is in a turnaround cycle because of the read on a muxed bus. The byte enables, which are active low, are driven onto the PCICXBE bus in this clock. Any combination of byte enables can be asserted (none may be asserted). A target will respond to an address phase by driving the DEVSEL signal. The specification allows for four types of decode operations.
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Functional Description 0 1 2 3 4 5 6 7 8 9 PCI_CLK FRAME PCIAD PCICXBE A1 D1 D2 CMD BYTE ENABLES BYTE ENABLES PCIIRDY PCITRDY (Wait) DEVSEL PCISTOP Address Phase Data Phase 1 Data Phase 2 Figure 19-48. PCI Write Terminated by Target 19.4.1.4 PCI Bus Commands PCI supports a number of different commands. These commands are presented by the initiator on the PCICXBE[3:0] lines during the address phase of a PCI transaction. Table 19-47.
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Table 19-47. PCI Bus Commands (Continued) PCICXBE[3:0] PCI Bus Command MCF548x Supports as Initiator MCF548x Supports as Target Definition 1001 Reserved No No — 1010 Configuration read Yes Yes The configuration read command accesses the 256 byte configuration space of a PCI agent. 1011 Configuration write Yes Yes The configuration read command accesses the 256 byte configuration space of a PCI agent.
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Functional Description As an initiator, the MCF548x supports both linear incrementing and cache wrap mode. For memory transactions, when an XL bus burst transaction is wrapped, the cache wrap mode is automatically generated. For zero-word-aligned bursts and single-beat transactions, the MCF548x drives AD[1:0] to 0b00. As a target, the MCF548x treats cache wrap mode as a reserved memory mode when the cache line size register is programmed zero.
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tells the community of devices on the PCI bus that the bridge that “owns” the PCI bus has already performed the bus number comparison and verified that the request targets a device on its bus. Figure 19-49 shows the contents of the AD bus during the address phase of the Type 0 configuration access. Target Configuration Doubleword Number 31 11 10 Reserved 8 7 Function Number 2 Dword Number 1 0 0 0 Figure 19-49.
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Functional Description its secondary bus as a Type 0 configuration access, decoding the device number to select one of the IDSEL lines. If the bus number is not equal to its secondary bus, but is within the range of buses that are subordinate to the bridge, the bridge claims and passes that access through as a Type 1 access. Responds to Type 0 Device 0.0 MCF548x Primary Bus . Device 0.1 Secondary Bus PCI Bridge . PCI Bridge Device 0.2 Subordinate Bus Device 1.2 Device 2.2 Device 1.0 Device 1.
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PCI Request/Grant (to PCI Arbiter) XL Bus Arbiter Multichannel DMA Controller XL Bus Initiator Comm Bus Initiator PCI Controller tx_req tx_gnt rx_req rx_gnt PCI Initiator Arbiter External PCI Bus Initiator Interface Figure 19-52. Initiator Arbitration Block Diagram 19.4.2.1 Priority Scheme The PCI initiator arbiter uses the following fixed priority scheme: 1. XL bus initiator 2. Comm bus transmit (Tx) 3. Comm bus receive (Rx) (lowest) 19.4.
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Functional Description The particular type of PCI transaction generated is determined by the PCI configuration bits associated with the address window (PCIIWCR). For example, the user might set one window to do PCI memory read multiple accesses, one window for PCI I/O accesses, and the other window to do non-prefetchable (memory-mapped I/O) PCI memory accesses. See Table 19-57 for command translations.
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request to the PCI bus comes in, the data transfer is delayed until all previous writes to the PCI bus are completed. Only when the write buffer is empty can burst data from the XL bus be posted. 19.4.4.1 Endian Translation The PCI bus is inherently little endian in its byte ordering. The internal XL bus, however, is big endian. XL bus transactions are limited to 1, 2, 3, 4, 5, 6, 7, 8, or 32 byte (burst) transactions within the data bus byte lanes on any 32-bit address boundary for burst transfers.
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Functional Description Table 19-49.
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19.4.4.2 Configuration Mechanism In order to support both Type 0 and Type 1 configuration transactions, the MCF548x provides the 32 bit configuration address register (PCICAR). The register specifies the target PCI bus, device, function, and configuration register to be accessed.
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Functional Description Table 19-50.
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19.4.4.2.2 Type 1 Configuration Translation For Type 1 translations, the 30 high-order bits of the configuration address register are copied without modification onto the AD[31:2] signals during the address phase. The AD[1:0] signals are driven to 0b01 during the address phase to indicate a Type 1 configuration cycle. 19.4.4.3 Interrupt Acknowledge Transactions When the MCF548x detects a read from an I/O defined window (Section 19.3.2.
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Functional Description assigned by the PCI SIG Steering Committee. The current list of defined encodings are provided in Table 19-51. Table 19-51. Special Cycle Message Encodings 19.4.4.5 PCIAD[15:0] Message 0x0000 SHUTDOWN 0x0001 HALT 0x0002 x86 architecture-specific 0x0003–0xFFFF — Transaction Termination If the PCI cycle Master Aborts, the interface will return 0xFFFF FFFF as read data, but complete without error. It will issue an interrupt to the internal interrupt controller if enabled.
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Upon detection of a PCI address phase, the PCI controller decodes the address and bus command to determine if the transaction is for local memory (BAR0 or BAR1 hit). If the transaction falls within MCF548x PCI space (memory only), the PCI Controller target interface asserts DEVSEL, latches the address, decodes the PCI bus command, and forwards them to the internal control unit. On writes, data is forwarded along with the byte enables to the internal gasket.
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Functional Description Table 19-53.
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Table 19-54. Non-Contiguous PCI to XL Bus Transfers (Requires Two XL Bus Accesses) (Continued) PCI Bus BE[3: 0] 0110 XL Bus Data Bus Byte Lanes AD[2:0] 31:24 23:16 15:8 7:0 A[29:31] 0 000 OP3 OP2 000 1 2 100 OP3 OP2 4 5 6 OP3 100 OP2 111 0101 000 OP3 OP2 OP3 001 OP2 011 0101 100 OP3 OP2 OP3 101 OP2 111 0010 000 OP3 OP2 OP1 000 OP3 OP1 010 0010 100 OP3 OP2 OP1 OP2 OP3 100 OP1 110 0100 000 OP3 OP2 OP1 000 OP2 OP1 100 OP3 OP2 OP1 OP3 100 111 19.4.
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Functional Description on the XL bus will have 100% bandwidth available to them during PCI multichannel DMA activities. In general, this block will be used by functions in the multichannel DMA API. The communication subsystem initiator interface consists of Receive and Transmit FIFOs, integrated as separate multichannel DMA peripherals. Therefore, it is generally controlled by the multichannel DMA controller through a pre-described program loop.
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19.4.6.3 Data Translation The PCI bus is inherently little endian in its byte ordering. The comm bus however is big endian. Table 19-55 shows the byte lane mapping between the two buses. Because this interface only allows 32-bit accesses, there is only one entry. Table 19-55. Comm Bus to PCI Byte Lanes for Memory Transactions Comm Bus Transfer long 19.4.6.
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Functional Description If Continuous mode is active, basic operation is still straight forward. A Restart is achieved by writing the Packet_Size register to a non-zero value (just as before). When a Restart occurs, the Bytes_Done counter is cleared to begin counting for the current packet and the Packets_Done counter increments. The Packets_Done counter indicates the total number of previously completed packets. However, the Master Enable and Reset bits must not toggle in this case.
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19.4.6.9 Bus Errors Because bus errors are particular to the module register set and that register set includes both transmit and receive controller and FIFO settings, the bus error status bits and Bus error Enable bit(s) are duplicated in the Transmit and Receive register groupings. Clearing or setting one will clear or set the other. From a software point of view, then, they can be treated separately or together, as desired. 19.4.
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Application Information read and write requests from an XL bus master and decodes them to different address ranges resulting in the generation of memory, I/O, configuration, interrupt acknowledge and special cycles on the PCI bus. The window registers are defined in Section 19.3.2.6, “Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR),” through Section 19.3.2.8, “Initiator Window Configuration Register (PCIIWCR).” Table 19-57.
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19.5.2.1 19.5.2.1.1 Address Translation Inbound Address Translation The MCF548x-as-target occupies two memory target address windows on the PCI bus. The location is determined by the values programmed to BAR0 and BAR1 of the PCI Type 00h configuration space. These inbound memory window sizes are fixed to one 256-Kbyte window (BAR0) and one 1-Gbyte window (BAR1). PCI inbound address translation allows address translation to any space in MCF548x space (4 Gbytes of address space).
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Application Information MCF548x Space PCI Space (Memory View) 0 Inbound Translation Base Address 0 0 Register Space TBATR0 Address Translation 1G Initiator Windows 1G PCI Space Not Recommended TBATR1 Address Translation 2G Inbound Translation Base Address 1 System Memory MCF548x Memory MCF548X BAR1 MCF548x Memory MCF548X BAR0 2G SDRAM Space 3G 3G 4G 4G Figure 19-54. Inbound Address Map 19.5.2.1.
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PCI Space (Memory View) MCF548x Space 0 PCI Space (I/O View) 0 (Configuration View) 0 0 1G 1G Window 0 MBAR Register Space Window 0 Translation 1G 1G Window 0 XLB Initiator Windows 2G Window 1 Not Recommended Window 1 Translation 2G Not Recommended Window 2 Window 2 Translation 3G MCF548X Memory 2G Window 1 2G MCF548X Memory 3G 3G 3G 4G 4G Window 2 4G 4G Window 0 Base Address = 0x40 Window 0 Address Mask = 0x1F Window 0 Translation Address = 0x00 Associated with PCI Prefetchabl
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XL Bus Arbitration Priority Table 19-58. Address Register Accessibility (Continued) Base Address Register 19.
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MCF548x Reference Manual, Rev.
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Chapter 20 PCI Bus Arbiter Module 20.1 Introduction This chapter describes the MCF548x PCI bus arbiter module, including timing for request and grant handshaking, the arbitration process, and the registers in the PCI bus arbiter programing model. It also provides arbitration examples. For information on the PCI Controller, see Chapter 19, “PCI Bus Controller.” 20.1.
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20.1.3 • • • • • • Features Direct support for up to five external PCI bus masters Fair arbitration scheme Hidden bus arbitration Bus parking Master time-out Interface with 33 MHz and 66 MHz PCI 20.2 External Signal Description This section defines the PCI arbiter and corresponding external I/O signals. Table 20-1 summarizes this information. Table 20-1. PCI Arbiter External Signals Name 20.2.
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Register Definition 20.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the MCF548x needs to initiate a PCI transaction. 20.2.6 External Bus Request (PCIBR[4:1]) The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus. 20.2.
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Table 20-2. PACR Field Descriptions Bits Name Description 31 DS Disable bit for the internal PCI arbiter. 0 Enable the PCI arbiter. 1 Disable the on-chip arbiter and use GNT0 for the MCF548x PCI request output and REQ0 for its grant input. 30–22 — Reserved, should be cleared. 21–17 EXTMINTEN External master broken interrupt enables. If an external master time-out occurs and the corresponding interrupt enable bit is set, a CPU interrupt will be generated.
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Functional Description 20.3.2 PCI Arbiter Status Register (PASR) R 31 30 29 28 27 26 25 24 23 22 0 0 0 0 0 0 0 0 0 0 21 20 19 18 17 EXTMBK ITLMBK 1 W rwc1 rwc Reset R 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xC04 1 Bits 21-16 are read-write-clear (rwc).
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20.4.2 20.4.2.1 Arbitration Hidden Bus Arbitration PCI bus arbitration can take place while the currently granted device is performing a bus transaction if another master is requesting access to the bus. As long as the bus is active, the arbiter can deassert GNT to one master and assert GNT to the next in the same cycle and no PCI bus cycles are consumed due to arbitration. The newly granted device must wait until the bus is relinquished by the current master before initiating a transaction. 20.4.2.
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Functional Description High-Priority Group Device 1 (1/3) 1a MCF548X (1/3) Low-Priority Group 1b 2a 3a Low-Priority Group Slot (1/3) Device 2 (1/12) 2b Device 0 (1/12) 4b 3b Device 3 (1/12) Device 4 (1/12) PCI Arbiter Control Register PACR[26:31] = 000101b Figure 20-4. PCI Arbitration Initial State 20.4.2.3 Arbitration Latency Worst case arbitration latency: arbitration latency is the number of clock cycles from a master’s REQ assertion to PCI bus idle state AND its GNT assertion.
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0 1 2 3 4 5 6 7 8 9 10 11 12 PCI_CLK REQ[0] REQ[1] REQ[2] GNT[0] GNT[1] GNT[2] (Parked) PCIFRAME PCIIRDY PCIAD DRIVEN LOW ADDR DATA Access 0 STATE IDLE TURN GRANT ADDR DATA Access 1 ACTIVE GRANT ADDR DATA Access 0 ACTIVE GRANT ACTIVE Figure 20-5. Alternating Priority Device 0 and device 1 assert REQ while the bus is parked with device 2. Because the PCI bus is idle, the arbiter deasserts GNT to the parked master (device 2) and a cycle later, grants access to device 0.
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Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 12 PCI_CLK REQ[0] REQ[1] REQ[2] GNT[0] GNT[1] GNT[2] (Parked) PCIFRAME PCIIRDY PCIAD LOW ADDR DATA ADDR Access 2 STATE IDLE TURN DATA Access 0 ACTIVE GRANT ADDR DATA Access 1 ACTIVE GRANT ADDR DATA Access 2 ACTIVE GRANT ACTIVE Figure 20-6. Higher Priority Override The arbiter again deasserts device 2’s GNT on clock 2, but device 2 initiates a transaction in the same cycle.
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considered “broken” and subsequent requests are acknowledged. This “never-mind” scenario is detrimental to system performance, however, and is not a recommended implementation. 20.5 Reset Reset capability is provided by the MCF548x system reset. This signal resets both hardware and software registers in the internal PCI arbiter. An MCF548x software bit external to the arbiter controls the external PCIRESET signal (See Section 19.3.2.1, “Global Status/Control Register (PCIGSCR)”).
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Chapter 21 FlexCAN 21.1 Introduction The FlexCAN module is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbps), short distance, priority-based protocol that can communicate using a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires).
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Control IRQ or DMA Request Serial Buffers Tx Rx Tx Shifter Data Rx Shifter Transparent to User • 16 Transmit/Receive • Message Buffers • • • • Buffer 0 • Data Buffer 13 Data Buffer 14 ID Data Length Data Buffer 15 Time Stamp Data Length Data ID Time Stamp Data Length ID Time Stamp Mask 14 Mask 15 •• • • • • • ID Global Mask Figure 21-2. FlexCAN Message Buffer Architecture 21.1.2 The CAN System A typical CAN system is shown below in Figure 21-3.
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Introduction bus. It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or defective stations. 21.1.3 Features Following are the main features of the FlexCAN module: • Full implementation of the CAN protocol specification version 2.
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• • • • The prescaler is disabled, thus halting all CAN bus communication. The FlexCAN ignores its Rx pins and drives its Tx pins as recessive. The FlexCAN loses synchronization with the CAN bus, and the NOTRDY and FRZACK bits in CANMCR are set. The CPU is allowed to read and write the error counter registers (in other modes they are read-only).
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External Signals 21.2 External Signals The FlexCAN module has two I/O signals connected to the external MPU pins: CANTX and CANRX. Note that the general purpose I/O (GPIO) must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 15, “GPIO”) prior to configuring a FlexCAN channel. 21.2.1 CANTX[1:0] CANTXn transmits serial data to the CAN bus transceiver. 21.2.2 CANRX[1:0] CANRXn receives serial data from the CAN bus transceiver. 21.3 21.3.
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Table 21-1. FlexCAN Memory Map (Continued) MBAR Offset Name Byte0 Byte1 Byte2 Byte3 Access FlexCAN0 FlexCAN1 0xA034– 0xA07F 0xA834– 0xA87F 0xA080– 0xA17F 0xA880– 0xA97F 21.3.2 Reserved — Message buffers 0–15 MB S/U Register Descriptions This section describes the registers in the FlexCAN module. NOTE The FlexCAN has no hard-wired protection against invalid bit/field programming within its registers.
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Memory Map/Register Definition Table 21-2. CANMCR Field Descriptions Bits Name Description 31 MDIS Module disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the FlexCAN clocks. This is the only bit in CANMCR not affected by soft reset. See Section 21.1.4.3, “Module Disabled Mode” for more information. 0 Enable the FlexCAN module, clocks enabled 1 Disable the FlexCAN module, clocks disabled 30 FRZ FREEZE assertion response.
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Table 21-2. CANMCR Field Descriptions (Continued) Bits Name Description 22–4 — 3–0 MAXMB Reserved, should be cleared. Maximum number of message buffers. This 6-bit field defines the maximum number of message buffers that will take part in the matching and arbitration process. The reset value (0xF) is equivalent to 16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode. Maximum MBs in Use = MAXMB + 1 21.3.2.
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Memory Map/Register Definition Table 21-3. CANCTRL Field Descriptions Bits Name Description 31–24 PRESDIV Prescaler division factor. This 8-bit field defines the ratio between the system clock frequency and the serial clock (S clock) frequency. The S clock period defines the time quantum of the CAN protocol. For the reset value, the S clock frequency is equal to the system clock frequency.
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Table 21-3. CANCTRL Field Descriptions (Continued) Bits 6 Name Description BOFFREC Bus off recovery mode. This bit defines how FlexCAN recovers from bus off state. If this bit is cleared, automatic recovering from bus off state occurs according to the CAN Specification 2.0B. If the bit is set, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is cleared by the user.
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Memory Map/Register Definition The timer value is captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message. Writing to the timer is an indirect operation. The data is first written to an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed.
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Table 21-4. Mask Examples for Normal/Extended Messages (Continued) 1 2 3 4 5 6 7 Base ID ID28.................ID18 IDE Extended ID ID17......................................
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Memory Map/Register Definition Table 21-5. RXGMASK Field Descriptions (Continued) Bits Name Description 28–18 MI28–MI18 Standard ID mask bits. These bits are the same mask bits for the Standard and Extended Formats. 17–0 MI17–MI0 21.3.2.4.2 Extended ID mask bits. These bits are used to mask comparison only in Extended Format. FlexCAN Rx 14 Mask Register (RX14MASK) The RX14MASK register has the same structure as the Rx global mask register and is used to mask message buffer 14.
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31 30 29 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 1 1 1 1 1 1 1 1 1 1 R 28 27 26 25 24 23 22 21 20 19 18 17 16 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 W Reset R MI15 MI14 MI13 MI12 MI11 MI10 W Reset 1 1 1 Reg Addr 1 1 1 MBAR + 0xA018 (RX15MASK0); 0xA818 (RX15MASK1) Figure 21-9. FlexCAN Rx15 Mask Register (RX15MASK) Table 21-7.
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Memory Map/Register Definition to zero and counts in a manner where the internal counter counts 11 such bits, then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the FLTCONF field in the error and status register is updated to be error-active, and both error counters are reset to zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the TXECTR value.
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACK ERR CRC ERR FRM ERR 0 0 0 W Reset R BITERR STF TX RX IDLE TXRX ERR WRN WRN FLT CONF 0 BOFF ERR INT INT 0 W Reset 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 0 0 MBAR + 0xA020 (ERRSTAT0); 0xA820 (ERRSTAT1) Figure 21-11.
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Memory Map/Register Definition Table 21-8. ERRSTAT Field Descriptions (Continued) Bits Name Description 8 RXWRN Receiver error status flag. The RXWARN status flag reflects the status of the FlexCAN receive error counter. 0 Receive error counter < 96 1 RxErrCounter ≥ 96 7 IDLE Idle status. The IDLE bit indicates when there is activity on the CAN bus. 0 The CAN bus is not idle. 1 The CAN bus is idle. 6 TXRX Transmit/receive status.
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15 14 13 12 11 10 9 8 7 6 5 4 IMASK_H R BUF 15M W Reset 0 2 1 0 IMASK_L BUF 14M BUF 13M BUF 12M BUF 11M BUF 10M BUF 9M 0 0 0 0 0 0 Reg Addr 3 BUF BUF7 BUF 8M M 6M 0 0 BUF 5M BUF 4M BUF 3M BUF 2M BUF 1M BUF 0M 0 0 0 0 0 0 0 MBAR + 0xA02A (IMASK0); 0xA82A (IMASK1) Table 21-9. FlexCAN Interrupt Mask Register (IMASK) Table 21-10 describes the IMASK fields. Table 21-10.
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Functional Overview Table 21-12. IFLAG Field Descriptions Bits Name Description 15–0 BUFnI IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be generated. To clear an interrupt flag, first read the flag as a one, and then write it as a one.
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31 30 29 28 27 26 25 24 23 0x0 CODE 0x4 22 21 20 SRR IDE RTR 19 18 17 16 15 14 13 12 11 10 LENGTH 9 8 7 6 5 4 3 2 1 0 TIME STAMP Standard ID [28:18] Extended ID [17:0] 0x8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 0xC Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 21-12. Message Buffer Structure for Both Extended and Standard Frames Table 21-13.
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Functional Overview Table 21-13. Message Buffer Field Descriptions (Continued) Bits Name Description 28–0 ID [28:18] Standard frame identifier: In standard frame format, only the 11 most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored.
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Table 21-15. Message Buffer Code for Tx Buffers RTR Initial Tx Code Code After Successful Transmission X 1000 — 0 1100 1000 Data frame to be transmitted once, unconditionally. After transmission, the MB automatically returns to the INACTIVE state. 1 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. 0 1010 1010 Transmit a data frame whenever a remote request frame with the same ID is received.
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Functional Overview Message Buffers FlexCAN Base Address Offset 0x80 0x84 0x88 Control/Status Identifier Message Buffer 0 8 byte Data fields 0x8F 0x90 Message Buffer 1 0x9F 0xA0 Message Buffer 2 0xAF Message Buffer 3 0xB0 through 0x16F Message Buffer 14 0x170 Message Buffer 15 0x17F Figure 21-13. FlexCAN Message Buffer Memory Map 21.4.3 Transmit Process The CPU prepares or changes an MB for transmission by executing the following steps: 1.
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Once the arbitration process is complete and there is a “winner” MB for transmission, the frame is transferred to the serial message buffer (SMB) for transmission (move out). While transmitting, the FlexCAN transmits up to 8 data bytes, even if the DLC is bigger in value.
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Functional Overview was captured at the beginning of the ID field on the CAN bus) is written into the TIMESTAMP field in the MB, the ID field, data field (8 bytes at most) and the LENGTH field are stored, the CODE field is updated and a status flag is set in the IFLAG register. The CPU should read a receive frame from its MB in the following way: 1. Read the control/status word (mandatory—activates internal lock for this buffer). 2. Read the ID (optional—needed only if a mask was used). 3.
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lost. Two or more receive MBs that hold a matching ID to a received frame do not assure reception in the FlexCAN if the user has deactivated the matching MB after FlexCAN has scanned the second. 21.4.6.1 Serial Message Buffers (SMBs) To allow double buffering of messages, the FlexCAN has two shadow buffers called serial message buffers. These two buffers are used by the FlexCAN for buffering both received messages and messages to be transmitted.
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Functional Overview • There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued and the CODE field is not updated. 21.4.6.4 Locking and Releasing Message Buffers Besides message buffer deactivation, the lock/release/busy mechanism is designed to guarantee data coherency during the receive process.
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When transmitting a remote frame, the user initializes a message buffer as a transmit message buffer with the RTR bit set to one. Once this remote frame is transmitted successfully, the transmit message buffer automatically becomes a receive message buffer, with the same ID as the remote frame that was transmitted. When a remote frame is received by the FlexCAN, the remote frame ID is compared to the IDs of all transmit message buffers programmed with a CODE of 1010.
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Functional Overview • • • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CANCTRL register so that their sum (plus 2) is in the range of 4 to 16 time quanta. Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard.
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• • If PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the scheduled sync segment.
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FlexCAN Initialization Sequence • If the RXECTR increases to a value greater than 127, it is no longer incremented, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127, in order to return to error active state. 21.
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MCF548x Reference Manual, Rev.
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Chapter 22 Integrated Security Engine (SEC) This chapter provides an overview of the MCF548x security encryption controller (SEC). NOTE Purchasing any of the MCF548x devices with security requires government export control regulation. 22.1 Features The SEC is designed to offload computationally intensive security functions, such as authentication bulk encryption from the MCF548x core. It is optimized to process all the algorithms associated with IPSec, SSL/TLS, iSCSI, and SRTP.
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define the cryptographic function to be performed and the location of the data. The SEC’s bus-mastering capability permits the host processor to set up a crypto-channel with a few register writes, then the SEC can perform reads and writes on system memory to fetch data packet descriptors and complete the specified tasks. 22.3 Block Diagram Figure 22-1 shows a block diagram of the SEC module.
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Overview 22.4.2 SEC Controller Unit The SEC controller unit manages on-chip resources, including the individual execution units (EUs), FIFOs, the bus interface, and the internal buses that connect all the various modules. The controller receives service requests from the bus interface and various crypto-channels, and schedules the required activities.
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4. Wait for EU to complete processing. 5. Upon completion, unload results and context and write them to external memory as indicated by the data packet descriptor. 6. If multiple services requested, go back to step 2. 7. Reset the appropriate EU if it is dynamically assigned. Note that if statically assigned, an EU is reset only upon direct command written to the SEC. 8. Perform descriptor completion notification as appropriate.
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Overview 64-bit key Plaintext blocks 64-bit block n 64-bit block n-1 ... 64-bit block 2 Ciphertext blocks 64-bit block 1 64-bit block n 64-bit block n-1 ... 64-bit block 2 64-bit block 1 DES Figure 22-2. DES Encryption Process In addition, the DEU module can compute Triple-DES. Triple-DES is an extension to the DES algorithm whereby every 64-bit input block is processed three times. A diagram of Triple-DES is shown in Figure 22-3.
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n-bit key Plaintext stream byte n byte n-1 ... Ciphertext stream byte 2 byte n byte 1 byte n-1 ... byte 2 byte 1 RC4 Figure 22-4. RC4 Encryption Process 22.4.4.3 Advanced Encryption Standard Execution Unit (AESU) The AESU is used to accelerate bulk data encryption/decryption in compliance with the advanced encryption standard algorithm (AESA) Rinjdael. The AESU executes on 128 bit blocks with a choice of key sizes: 128, 192, or 256 bits.
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Overview • The MDEU also supports HMAC computations, as specified in RFC 2104. With any hash algorithm, the larger message is mapped onto a smaller output space, therefore collisions are potential, albeit not probable. The 160-bit hash value is a sufficiently large space such that collisions are extremely rare. The security of the hash function is based on the difficulty of locating collisions.
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22.4.4.5 Random Number Generator (RNG) The RNG is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS 140-1 standards for randomness and non-determinism. Because many cryptographic algorithms use random numbers as a source for generating a secret value (a nonce), it is desirable to have a private RNG for use by the SEC. The anonymity of each random number must be maintained, as well as the unpredictablility of the next random number.
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Memory Map/Register Definition Table 22-3. SEC Register Map (Continued) Register Offset Mnemonic 0x21008 SIMRH SEC Interrupt Mask Register High p. 22-14 0x2100C SIMRL SEC Interrupt Mask Register Low p. 22-14 0x21010 SISRH SEC Interrupt Status Register High p. 22-14 0x21014 SISRL SEC Interrupt Status Register Low p. 22-14 0x21018 SICRH SEC Interrupt Control Register High p. 22-14 0x2101C SICRL SEC Interrupt Control Register Low p. 22-14 0x21020 SIDR SEC ID Register p.
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Table 22-3. SEC Register Map (Continued) Register Offset Mnemonic Name Page DEU Registers 0x2A018 DRCR DEU Reset Control Register p. 22-34 0x2A028 DSR DEU Status Register p. 22-35 0x2A030 DISR DEU Interrupt Status Register p. 22-37 0x2A038 DIMR DEU Interrupt Mask Register p. 22-39 MDEU Registers 0x2C018 MDRCR MDEU Reset Control Register p. 22-41 0x2C028 MDSR MDEU Status Register p. 22-41 0x2C030 MDISR MDEU Interrupt Status Register p.
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Controller 22.6.1 EU Access Assignment of an EU function to a channel is done either statically or dynamically. In the case of static assignment, an EU is assigned to a channel via the EU Assignment Control Register (EUACR). Once an EU is statically assigned to a channel, it will remain that way until the EUACR is written and the assignment is removed.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Field — RNG — — Reset 1111 0000 1111 0000 R R/W R R R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Field — MDEU — AFEU Reset 1111 0000 1111 0000 R R/W R R/W R/W Reg Addr 16 0 MBAR + 0x21000 Figure 22-7.
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Controller Table 22-5. Channel Assignment Value (Continued) 22.6.4.2 Value Channel 0x3–0xE Reserved 0xF EU is not statically assigned to any channel and is not allowed to be dynamically assigned to a channel. EU Assignment Status Registers (EUASRH and EUASRL) The EUASR registers, shown in Figure 22-9 and Figure 22-10, are used to check the assignment status (static or dynamic) of an EU to a particular crypto-channel. When an EU is already assigned, it is inaccessible to any other crypto-channel.
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Table 22-6. EUASRH and EUASRL Field Descriptions Bits 31–0 22.6.4.3 Name Description See Figure 22-10 Channel Assignment. Each field corresponds to one of the SEC EUs. The field indicates if the EU is currently assigned to one of the two channels as shown in Table 22-5. SEC Interrupt Mask Registers (SIMRH and SIMRL) The SEC generates a single interrupt output from all possible interrupt sources. These sources can be masked by the SIMR registers.
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Controller 31 Field 30 29 CHA_1 Definition ERR DN 28 CHA_0 ERR 27 26 25 24 23 22 AERR 21 20 19 18 17 16 4 3 2 1 0 — DN Reset 0x0000 R/W W 15 14 13 12 11 10 9 8 Field 7 6 5 — Definition Reset 0x0000 R/W W Reg Addr MBAR + 0x21008 (SIMRH), 0x 21010 (SISRH), 0x21018 (SICRH) Figure 22-11. SEC Interrupt Mask, Status, and Control Registers High (SIMRH, SISRH, and SICRH) I Table 22-7.
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31 30 29 Field 28 27 26 25 — 24 23 RNG Definition ERR Reset 22 21 — 20 19 AFEU DN ERR DN 5 4 18 — 17 16 MDEU ERR DN 1 0 0x0000 R/W R/W 15 Field 14 13 — 12 AESU Definition ERR 11 10 9 — DN 8 DEU ERR Reset 7 6 — TEA 3 2 — DN 0x0000 R/W R/W Reg Addr MBAR + 0x2100C (SIMRL), 0x 21014 (SISRL), 0x2101C (SICRL) Figure 22-12. SEC Interrupt Mask, Status, and Control Registers Low (SIMRL, SISRL, and SICRL) Table 22-8.
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Controller 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 Version W Reset 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R Version W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0x 21020 Figure 22-13. ID Register (SIDR) 22.6.4.
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Table 22-9. SMCR Field Descriptions (Continued) Bits Name 7–4 CURR_CHAN Current Channel. These bits are read only. They indicate the channel number that is currently in use by the controller as a master on the XLB bus. The possible values are: 0000 - No Channel is currently in use. 0001 - Channel 0 is in use. 0010 - Channel 1 is in use. 3–0 22.6.4.
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Channels store the ciphered data the EU outputs. Through a series of requests to the controller, the crypto-channel decodes the contents of the descriptors to perform the following functions: • Request assignment of one or more of the several EUs for the exclusive use of the channel. • Request assignment of the MDEU when the descriptor header calls for multi-operation processing. The MDEU will be configured to snoop input or output data intended for the primary assigned EU. • Reset assigned EU(s).
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 BURST_SIZE 0 0 0 WE NE NT 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R CDIE RST W Reset Reg Addr 0 0 0 0 MBAR + 0x2200C (CCCR0), 0x2300C (CCCR1) Figure 22-16. Crypto-Channel Configuration Register (CCCRn) Table 22-11.
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Channels Table 22-11. CCCRn Field Descriptions (Continued) Bits Name Description 2 NT Channel DONE Notification Type. This bit controls when the crypto-channel will generate Channel DONE Notification. 0 End-of-chain: The crypto-channel will generate channel done notification (if enabled) when it completes the processing of the last descriptor in a descriptor chain.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset R STATE W Reset Reg Addr 0 0 0 0 0 MBAR + 0x22010 (CCPSRH0), 0x23010 (CCPSRH1) Figure 22-17. Crypto-Channel Pointer Status Register High (CCPSRHn) Table 22-13.
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Channels Table 22-14. CCPSRLn Field Descriptions Bits Name Description 31–27 — 26 STAT Crypto-Channel Static Mode Enable. The STAT bit is set when descriptor processing is initiated and the EUs indicated in the descriptor header register are already assigned to the channel. This bit is cleared when descriptor processing is initiated for the next descriptor and no EUs are assigned to the channel. 0 Crypto-channel is operating in dynamic mode. 1 Crypto-channel is operating in static mode.
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Table 22-14. CCPSRLn Field Descriptions (Continued) Bits Name Description 18 SRD 17 PD Primary EU done. Reflects the state of the done interrupt from the assigned primary EU. 0 The assigned primary EU done interrupt is inactive. 1 The assigned primary EU done interrupt is active indicating the EU has completed processing and is ready to provide output data. 16 SD Secondary EU done. Reflects the state of the done interrupt from the assigned secondary EU.
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Channels Table 22-14. CCPSRLn Field Descriptions (Continued) Bits Name Description 8 EUERR EU error. An EU assigned to this channel has generated an error interrupt. This error may also be reflected in the controller’s SISR. The EUERR bit can only be cleared by first clearing the error source in the assigned EU which caused it to be set. 0 No error. 1 EU error. 7–0 PAIR_PTR Descriptor buffer register length/pointer pair.
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Table 22-15.
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Channels 22.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn) The CDPR, shown in Figure 22-19, contains the address of the data packet descriptor which the crypto-channel is currently processing. This register, along with the PAIR_PTR in the CCPSR, can be used to determine if a new descriptor can be safely inserted into a chain of descriptors.
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31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 FETCH_ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R FETCH_ADDR W Reset 0 0 0 0 0 Reg Addr 0 0 0 0 MBAR + 0x2204C (FR0), 0x2304C (FR1) Figure 22-20. Fetch Register (FRn) Table 22-17 describes the FRn fields. Table 22-17. FRn Field Descriptions Bits Name Description 31–0 FETCH ADDR Fetch address.
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ARC Four Execution Unit (AFEU) hardware reset, software reset, or module initialization, which performs proper initialization of the S-Box. To determine when this is complete, observe the RD bit in the AFEU status register.
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R 31 30 29 0 0 0 0 0 15 14 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 OFR IE ID RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT IFW W Reset R W Reset Reg Addr MBAR + 0x28028 Figure 22-22. AFEU Status Register (AFSR) Table 22-19 describes AFEU status register fields. Table 22-19.
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ARC Four Execution Unit (AFEU) Table 22-19. AFSR Field Descriptions (Continued) Bits Name 25 ID Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller interrupt status register (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and SISRL)”). 0 AFEU is not signaling done 1 AFEU is signaling done 24 RD Reset done.
PAGE 634
Table 22-20. AFISR Field Descriptions (Continued) Bits Names Description 29 OFE Output FIFO error. The AFEU output FIFO was detected non-empty upon write of AFEU data size register. 0 No error detected 1 Output FIFO non-empty error 28 IFE Input FIFO error. The AFEU Input FIFO was detected non-empty upon generation of done interrupt 0 Input FIFO non-empty error enabled 1 Input FIFO non-empty error disabled 27 — Reserved, should be cleared. 26 IFO Input FIFO overflow.
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ARC Four Execution Unit (AFEU) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AE OFE IFE 0 IFO OFU 0 0 0 0 IE ERE CE KSE DSE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R ME W Reset R W Reset Reg Addr MBAR + 0x28038 Figure 22-24.
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Table 22-21. AFIMR Field Descriptions (Continued) Bits Names Description 19 ERE Early Read Error. The AFEU register was read while the AFEU was performing encryption. 0 Early read error enabled 1 Early read error disabled 18 CE Context Error. An AFEU key register, the key size register, data size register, mode register, or context memory was modified while AFEU was performing encryption. 0 Context error enabled 1 Context error disabled 17 KSE Key Size Error.
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Data Encryption Standard Execution Units (DEU) R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 RI MI SR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MBAR + 0x2A018 Figure 22-25.
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R 31 30 29 0 0 0 0 0 15 14 0 0 28 27 26 25 24 OFR IE ID RD 0 0 0 0 0 13 12 11 10 9 0 0 0 0 0 0 0 0 0 0 HALT IFW 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MBAR + 0x2A028 Figure 22-26. DEU Status Register (DSR) Table 22-23 describes the DEU status register’s bit settings. Table 22-23.
PAGE 639
Data Encryption Standard Execution Units (DEU) Table 22-23. DSR Field Descriptions (Continued) Bits Name 25 ID Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller interrupt status register (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and SISRL)”). 0 DEU is not signaling done 1 DEU is signaling done 24 RD Reset done.
PAGE 640
Table 22-24. DISR Field Descriptions (Continued) Bits Name Description 29 OFE Output FIFO error. The DEU output FIFO was detected non-empty upon write of DEU data size register. 0 No error detected 1 Output FIFO non-empty error 28 IFE Input FIFO error. The DEU input FIFO was detected non-empty upon generation of DONE interrupt. 0 No error detected 1 Input FIFO non-empty error 27 — Reserved 26 IFO Input FIFO Overflow. The DEU input FIFO has been pushed while full.
PAGE 641
Data Encryption Standard Execution Units (DEU) 22.9.5 DEU Interrupt Mask Register (DIMR) The interrupt mask register controls the result of detected errors. For a given error (as defined in Section 22.9.4, “DEU Interrupt Status Register (DISR)”), if the corresponding bit in this register is set, then the error is ignored; no error interrupt occurs and the interrupt status register is not updated to reflect the error.
PAGE 642
Table 22-25. DIMR Field Descriptions (Continued) Bits Name Description 25 OFU 24-22 — 21 KPE 20 IE 19 ERE 18 CE 17 KSE Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate for Triple DES) was written to the DEU key size register 0 Key size error enabled 1 Key size error disabled 16 DSE Data size error (DSE): A value was written to the DEU data size register that is not a multiple of 8 bytes.
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Message Digest Execution Unit (MDEU) 22.10.2 MDEU Reset Control Register (MDRCR) This register, shown in Figure 22-29, allows three levels reset of just the MDEU, as defined by the three self-clearing bits.
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R 31 30 29 0 0 0 0 0 15 14 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 0 IE ID RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT IFW W Reset R W Reset Reg Addr MBAR + 0x2C028 Figure 22-30. MDEU Status Register (MDSR) Table 22-27 describes MDEU status register fields. Table 22-27.
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Message Digest Execution Unit (MDEU) Table 22-27. MDSR Field Descriptions (Continued) Bits Name Description 24 RD Reset Done. This status bit, when high, indicates that MDEU has completed its reset sequence, as reflected in the signal sampled by the appropriate crypto-channel. 0 Reset in progress 1 Reset done 23-0 — Reserved, should be cleared. 22.10.
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Table 22-28. MDISR Field Descriptions (Continued) Bits Name Description 25-21 — Reserved, should be cleared. 20 IE Internal Error. Indicates the MDEU has been locked up and requires a reset before use. 0 No internal error detected 1 Internal error detected Note: This bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the interrupt mask register or by resetting the MDEU. 19 ERE Early Read Error.
PAGE 647
Message Digest Execution Unit (MDEU) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AE 0 0 0 IFO 0 0 0 0 0 IE ERE CE KSE DSE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R ME W Reset R W Reset Reg Addr MBAR 0x2C038 Figure 22-32.
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Table 22-29. MDIMR Field Descriptions (Continued) Bits Name 16 DSE 15-0 — Description Data Size Error. An inconsistent value was written to the MDEU data size register: 0 Data size error enabled 1 Data size error disabled Reserved, should be cleared. 22.11 RNG Execution Unit (RNG) The RNG is an execution unit capable of generating 32-bit random numbers. It is designed to comply with the FIPS-140 standard for randomness and non-determinism.
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RNG Execution Unit (RNG) Table 22-30. RNGRCR Field Descriptions Bits Name Description 31-27 — Reserved 26 RI Reset Interrupt. Writing this bit active high causes RNG interrupts signalling DONE and ERROR to be reset. It further resets the state of the RNG interrupt status register. 0 No reset 1 Reset interrupt logic 25 MI Module Initialization.
PAGE 650
Table 22-31. RNGSR Field Descriptions Bits Name Description 31-30 — 29 HALT 28 — 27 OFR Output FIFO Readable. The controller uses this signal to determine if the RNG can source the next burst size block of data. 0 RNG output FIFO not ready 1 RNG output FIFO ready 26 IE Interrupt Error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller interrupt status register (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and SISRL)”).
PAGE 651
RNG Execution Unit (RNG) Table 22-32 describes RNG interrupt status register fields. Table 22-32. RNGISR Field Descriptions Bits Name Description 31 ME Mode Error. Indicates that the host has attempted to write an illegal value to the mode register 0 Valid data 1 Invalid data error 30 AE Address Error. An illegal read or write address was detected within the RNG address space.
PAGE 652
Table 22-33. RNGIMR Field Descriptions Bits Name Description 31 ME Mode Error. An illegal value was detected in the mode register. 0 Mode error enabled 1 Mode error disabled 30 AE Address Error. An illegal read or write address was detected within the MDEU address space. 0 Address error enabled 1 Address error disabled 29–26 — Reserved 25 OFU 24–21 — Reserved 20 IE Internal Error. An internal processing error was detected while generating random numbers.
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Advanced Encryption Standard Execution Units (AESU) R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 RI MI SR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MBAR + 0x32018 Figure 22-36.
PAGE 654
R 31 30 29 0 0 0 0 0 15 14 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 OFR IE ID RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT IFW W Reset R W Reset Reg Addr MBAR + 0x32028 Figure 22-37. AESU Status Register (AESSR) Table 22-35 describes AESU status register fields. Table 22-35.
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Advanced Encryption Standard Execution Units (AESU) Table 22-35. AESSR Field Descriptions (Continued) Bits Name Description 25 ID Interrupt Done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller interrupt status register (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and SISRL)”). 0 AESU is not signaling done 1 AESU is signaling done 24 RD Reset Done.
PAGE 656
Table 22-36. AESISR Field Descriptions (Continued) Bits Name Description 29 OFE Output FIFO Error. The AESU output FIFO was detected non-empty upon write of AESU data size register. 0 No error detected 1 Output FIFO non-empty error 28 IFE Input FIFO Error. The AESU input FIFO was detected non-empty upon generation of done interrupt. 0 No error detected 1 Input FIFO non-empty error 27 — Reserved 26 IFO Input FIFO Overflow. The AESU Input FIFO has been pushed while full.
PAGE 657
Advanced Encryption Standard Execution Units (AESU) and the interrupt status register is not updated to reflect the error. If the corresponding bit is not set, then upon detection of an error, the interrupt status register is updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt processing.
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Table 22-37. AESIMR Field Descriptions (Continued) Bits Name Description 20 IE Internal Error. An internal processing error was detected while the AESU was processing. 0 Internal error enabled 1 Internal error disabled 19 ERE 18 CE 17 KSE Key Size Error. An inappropriate value (not 16, 24 or 32 bytes) was written to the AESU key size register 0 Key size error enabled 1 Key size error disabled 16 DSE Data Size Error. Indicates that the number of bits to process is out of range.
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Descriptors Descriptor Pointer Descriptor Header +0x04 Data Field Length 1 +0x08 Data Field Pointer 1 +0x0C Data Field Length 2 +0x10 Data Field Pointer 2 +0x14 Data Field Length 3 +0x18 Data Field Pointer 3 +0x1C Data Field Length 4 +0x20 Data Field Pointer 4 +0x24 Data Field Length 5 +0x28 Data Field Pointer 5 +0x2C Data Field Length 6 +0x30 Data Field Pointer 6 +0x34 Data Field Length 7 +0x38 Data Field Pointer 7 +0x3C Next Descriptor Pointer Figure 22-40.
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Table 22-38. Header Bit Definitions Bits Name Description 31–28 PEUSEL Primary execution unit select. Programs the channel to select a primary EU of a given type. A “No primary EU selected” or a reserved value in this field will generate an unrecognized header error condition during processing of the descriptor header. 0x0 No primary EU selected 0x1 AFEU 0x2 DEU 0x3 MDEU 0x4 RNG 0x5 Reserved 0x6 AESU 0x7–0xF Reserved 27–20 PMODE Primary execution unit mode.
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Descriptors Table 22-38. Header Bit Definitions (Continued) Bits Name Description 1 ST Snoop type. Selects which of the two types of available snoop modes applies to the descriptor. 0 Snoop output data mode. 1 Snoop input data mode. In snoop input data mode, while the bus transaction to write data into the input FIFO of the primary EU is in progress, the secondary EU (always MDEU) will snoop the same data into its input FIFO.
PAGE 662
22.13.1.2 Descriptor Length and Pointer Fields The length and pointer fields represent one of seven data length/pointer pairs. Each pair defines a block of data in system memory. The length field gives the length of the block in bytes. The maximum allowable number of bytes is 32 Kbytes. A value of zero loaded into the length field indicates that this length/pointer pair should be skipped and processing should continue with the next pair.
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Descriptors 22.13.1.3 Null Fields On occasion, a descriptor field may not be applicable to the requested service. With seven length/pointer pairs, it is possible that not all descriptor fields will be required to load the required keys, context, and data. (Some operations do not require context, others may only need to fetch a small, contiguous block of data.) Therefore, when processing data packet descriptors, the SEC will skip entirely any pointer that has an associated length of zero. 22.13.1.
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DPD–DES–CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KEY PTR_KEY LEN_DATAIN PTR_DATAIN LEN_DATAOUT PTR_DATAOUT LEN_CTXOUT PTR_CTXOUT null length null pointer null length null pointer PTR_NEXT DPD–DES–CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KEY PTR_KEY LEN_DATAIN PTR_DATAIN LEN_DATAOUT PTR_DATAOUT LEN_CTXOUT PTR_CTXOUT null length null pointer null length null pointer PTR_NEXT DPD–DES–CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KEY PTR_KEY LEN_DATAIN PTR_DATAIN LEN_DATAOUT PTR_DATAOUT LEN_CTXOUT PTR_CTXOUT null length null pointer n
PAGE 665
Descriptors Table 22-43.
PAGE 666
Table 22-44. Descriptor Length/Pointer Mapping (Continued) Descriptor Type L/P 1 L/P 2 L/P 3 L/P 4 L/P 5 L/P 6 L/P 7 1110 HMAC Key HMAC Data Key Data In Data Out IV Out via FIFO HMAC/Context Out 1111 HMAC Key HMAC Data IV Data In Data Out IV Out via FIFO HMAC/Context Out 22.13.4 Descriptor Classes The SEC has two general classes of descriptors: dynamic, which refers to a continually changing usage model, and static, which refers to a relatively unchanging usage of the SEC resources.
PAGE 667
Descriptors Table 22-45. Dynamic Descriptor Example (Continued) Field Name Value/Type Description PTR_6 IV Out Pointer Address where IV is to be written (optional) LEN_7 MAC Out Length NULL PTR_7 MAC Out Pointer NULL PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor 22.13.4.2 Static Descriptors Recall that the SEC has five execution units and two crypto-channels. The EUs can be statically assigned or dedicated to a particular crypto-channel.
PAGE 668
Table 22-46. First Static Descriptor Example (Continued) Field Name Value/Type Description PTR_6 IV Out Pointer NULL LEN_7 MAC Out Length NULL PTR_7 MAC Out Pointer NULL PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor The middle (and multiple subsequent) descriptors contains length/pointer pairs to the remaining data to be permuted. Table 22-47 shows the format for a TYPE 0001 data packet descriptor that encrypts or decrypts a block of data.
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EU Specific Data Packet Descriptors Table 22-48.
PAGE 670
Table 22-49. AFEU Mode Register Field Descriptions Bits Name Description 7–3 — Reserved 2 CS Context Source. If set, this causes the context to be moved from the input FIFO into the S-box prior to starting encryption/decryption. Otherwise, context should be directly written to the context registers. Context Source is only checked if the prevent permute bit is set. 0 Context not from FIFO 1 Context from input FIFO 1 DC Dump Context.
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EU Specific Data Packet Descriptors Table 22-50. Descriptor for a Dynamically Assigned AFEU Using a Key (Continued) Field Name Value/Type Description LEN_7 MD Out Length NULL PTR_7 MD Out Pointer NULL PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor Table 22-51 shows the descriptor format to load a previously generated context into the AFEU. Then the input data is ciphered and the context is unloaded. Table 22-51.
PAGE 672
Table 22-52.
PAGE 673
EU Specific Data Packet Descriptors Table 22-53. First Descriptor for a Statically Assigned AFEU Using a Context (Continued) Field Name PTR_7 Value/Type MAC Out Pointer PTR_NEXT Description NULL Next Descriptor Pointer Pointer to next data packet descriptor Table 22-54 shows the descriptor format for the middle descriptor to perform the cipher on a block of data using a context or key that was loaded into the AFEU using either the first descriptors. Table 22-54.
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Table 22-55. Final Descriptor for a Statically Assigned AFEU (Continued) Field Name Value/Type Description LEN_3 Key Length NULL PTR_3 Key Pointer NULL LEN_4 Data In Length Number of bytes of data to be ciphered.
PAGE 675
EU Specific Data Packet Descriptors 22.14.2.1 Dynamically Assigned DEU For IPSec processing, it is envisioned that the SEC will need to process small packets of data associated with many different contexts. This descriptor type is designed to optimize system throughput in a case where the DEU module is dynamically assigned by the controller to whichever crypto-channel requests it.
PAGE 676
Table 22-58. Typical Header Values for Dynamic DEU Descriptor Format (Continued) Header Value E/C S/T E/D 0x20300010 ECB Triple DES Encrypt 0x20200010 ECB Triple DES Decrypt 22.14.2.2 Statically Assigned DEU When statically assigned, it can be assumed that no other crypto-channel will access the DEU in between descriptors. Therefore, in this usage mode, the context remains within the DEU. The DEU is programmed with the particular mode of operation at the time of context-load.
PAGE 677
EU Specific Data Packet Descriptors Table 22-60.
PAGE 678
Table 22-62. Typical Header Values for Middle Static DEU Descriptor Format (Continued) Header Value E/C S/T E/D 0x20600010 CBC Triple DES Decrypt 0x20100010 ECB Single DES Encrypt 0x20000010 ECB Single DES Decrypt 0x20300010 ECB Triple DES Encrypt 0x20200010 ECB Triple DES Decrypt Table 22-63 shows the final descriptor that performs a cipher on data using the key and optional context (IV) that were loaded into the DEU by a previous descriptor, then optionally unloads the context.
PAGE 679
EU Specific Data Packet Descriptors Table 22-64. Typical Header Values Final Static DEU Descriptor Format (Continued) Header Value E/C S/T E/D 0x20600010 CBC Triple DES Decrypt 0x20100010 ECB Single DES Encrypt 0x20000010 ECB Single DES Decrypt 0x20300010 ECB Triple DES Encrypt 0x20200010 ECB Triple DES Decrypt 22.14.3 MDEU Mode Options and Data Packet Descriptors The MDEU mode options, shown in Figure 22-48, contains 8 bits which are used to program the MDEU.
PAGE 680
Table 22-65. MDEU Mode Option Field Descriptions (Continued) Bits Name 2 PD 1–0 ALG Description Pad. If set, configures the MDEU to automatically pad partial message blocks. 0 Do not autopad 1 Perform automatic message padding whenever an incomplete message block is detected. Algorithm selection. Determines the algorithm to be used for operations.
PAGE 681
EU Specific Data Packet Descriptors (outbound) or compare the hash generated by the SEC with the hash which was received with the packet (inbound). If the hashes match, the packet integrity check passes. Table 22-67.
PAGE 682
Table 22-69.
PAGE 683
EU Specific Data Packet Descriptors Table 22-71.
PAGE 684
Table 22-73.
PAGE 685
EU Specific Data Packet Descriptors Table 22-75.
PAGE 686
Table 22-76. AESU Mode Register Field Descriptions (Continued) Bits Name Description 5 FM Final MAC. Processes final message block and generates final MAC tag at end of message processing (OCB and CCM mode only) 0 Do not generate final MAC tag 1 Generate final MAC tag after CCM processing is complete. 4 IM Initialize MAC. Initializes AESU for new message (CCM mode only) 0 Do not initialize (context will be loaded by host) 1 Initialize new message with nonce 3 — Reserved, should be cleared.
PAGE 687
EU Specific Data Packet Descriptors Table 22-77. Descriptor for a Dynamically Assigned AESU (Continued) Field Name Value/Type Description PTR_6 IV Out Pointer Address where output IV is to be written (optional) LEN_7 MAC Out Length NULL PTR_7 MAC Out Pointer NULL PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor Table 22-78 lists several different descriptors that use the format shown in Table 22-77. Table 22-78.
PAGE 688
Table 22-79. First Descriptor for a Statically Assigned AESU (Continued) Field Name PTR_7 Value/Type MAC Out Pointer PTR_NEXT Description NULL Next Descriptor Pointer Pointer to next data packet descriptor Table 22-80 lists several different descriptors that use the format shown in Table 22-79. Table 22-80.
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EU Specific Data Packet Descriptors Table 22-82. Typical Header Values for Using Middle Static AESU Descriptor Format Header Value Mode E/D 0x6030010 CBC Encrypt 0x60200010 CBC Decrypt 0x6010010 ECB Encrypt 0x60000010 ECB Decrypt 0x60600010 CTR — Table 22-83 shows the final descriptor for a statically assigned AESU. Table 22-83.
PAGE 690
Table 22-84. Typical Header Values for Using Final Static AESU Descriptor Format (Continued) Header Value Mode E/D 0x60000010 ECB Decrypt 0x60600010 CTR — 22.14.5.3 AESU-CCM Mode Descriptor The SEC supports single pass, single descriptor AES-CCM processing for generic authenticate-and-encrypt block cipher. Table 22-85 shows a the descriptor format used for AES-CCM in encryption mode.
PAGE 691
EU Specific Data Packet Descriptors Table 22-86. AES-CCM Encryption Context Input Format Offset from Input Context Base Address Field Length Description 0x0 IV 16 bytes This is the session specific IV parameter 0x10 NULL 16 bytes These 16 bytes are loaded with zeroes to serve as a placeholder 0x20 Counter 16 bytes The counter is a second session specific parameter similar to the IV. 0x30 Counter modulus 8 bytes Always 8 for 802.11, but can very in other protocols.
PAGE 692
Table 22-88. Descriptor for a AES-CCM Decryption (Continued) Field Name Value/Type Description LEN_6 IV Out Length Number of bytes of output IV to be written (24 or 32 bytes) PTR_6 IV Out Pointer Address where output IV is to be written LEN_7 MAC Out Length NULL PTR_7 MAC Out Pointer NULL PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor Table 22-89 shows the format used for the context input for AES-CCM. Table 22-89.
PAGE 693
EU Specific Data Packet Descriptors such that the same data read into the DEU, AESU, or AFEU modules can be simultaneously directed to the MDEU module. 22.14.6.1 Snooping As shown in Figure 22-41, the ST bit in the descriptor header controls the type of snooping which must occur between the primary and secondary EU. The rationale of in-snooping vs. out-snooping is found in security protocols which perform both encryption and integrity checking, such as IPSec.
PAGE 694
DEU/AESU and MDEU only reading the portion that matches the starting address and byte length in the length/pointer fields corresponding to their data of interest. Ciphertext is brought into the DEU/AESU input FIFO, with the MDEU in-snooping the portion of the data it has been told to process. As the decryption continues, the plaintext fills the DEU/AEU output FIFO, and this data is written back to system memory as needed.
PAGE 695
EU Specific Data Packet Descriptors Table 22-92.
PAGE 696
copy the last 8 bytes of the ciphertext to the Security Association Database Entry for this particular session before transmitting the packet. Table 22-94.
PAGE 697
EU Specific Data Packet Descriptors Table 22-95. Typical Header Values for Dynamic Multi-Function DEU Descriptors (Continued) Header Value E/C S/T E/D Algorithm HMAC Pad 0x20731E20 CBC Triple DES Encrypt MD5 Yes Yes 0x20731C20 CBC Triple DES Encrypt SHA Yes Yes Table 22-96 lists typical AESU/HMAC multi-function descriptor header values. Table 22-96.
PAGE 698
Table 22-97.
PAGE 699
EU Specific Data Packet Descriptors Table 22-98.
PAGE 700
Table 22-100 shows the representative descriptor format for the middle descriptors in a statically assigned multi-function operation descriptor chain. The middle descriptor header encodes to select the DEU or AESU as the primary EU, and the MDEU for the secondary EU. Because all the data necessary to calculate the HMAC in a single dynamic descriptor is still not available, continue is set while initialize, HMAC, and autopad are cleared in the SMODE field.
PAGE 701
EU Specific Data Packet Descriptors Table 22-101.
PAGE 702
Table 22-102.
PAGE 703
EU Specific Data Packet Descriptors Table 22-103.
PAGE 704
Table 22-104. Typical Header Values for Final Static Multi-Function DEU Descriptors (Continued) Header Value E/C S/T E/D Algorithm HMAC Pad 0x20638E22 CBC Triple DES Decrypt MD5 Yes Yes 0x20738E20 CBC Triple DES Encrypt MD5 Yes Yes 0x20638C22 CBC Triple DES Decrypt SHA Yes Yes 0x20738C20 CBC Triple DES Encrypt SHA Yes Yes Table 22-105 lists typical AESU/HMAC multi-function descriptor header values. Table 22-105.
PAGE 705
EU Specific Data Packet Descriptors performs the HMAC function first, then attaches the HMAC (which is variable size) to the end of the payload data. The payload data, HMAC, and any padding added after the HMAC are then encrypted. Parallel encryption and authentication of TLS “records” cannot be performed using the SEC snooping mechanisms which work for IPSec. Performing TLS record layer encryption and authentication with the SEC requires two descriptors.
PAGE 706
Table 22-107 lists several different descriptor header values that can be used for the outbound TLS descriptor one shown in Table 22-106. Table 22-107. Typical Header Values for Outbound TLS Descriptor One Format Header Value Algorithm HMAC Pad 0x31D00010 SHA256 Yes Yes 0x31E00010 MD5 Yes Yes 0x31C00010 SHA Yes Yes The second descriptor, shown in Table 22-108, performs the encryption of the record, HMAC, pad length, and any padding generated to disguise the size of the TLS record.
PAGE 707
EU Specific Data Packet Descriptors The primary EU is the AFEU, with its mode bits set to cause the AFEU to load the key and initialize the AFEU S-box for data permutation. The descriptor does not designate a secondary EU, so the setting of the snoop type bit is ignored. Table 22-109.
PAGE 708
Table 22-110.
PAGE 709
Chapter 23 IEEE 1149.1 Test Access Port (JTAG) 23.1 Introduction The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing testing. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. 23.1.
PAGE 710
23.1.2 Features The basic features of the JTAG module are the following: • Performs boundary-scan operations to test circuit board electrical continuity • Bypasses instruction to reduce the shift register path to a single cell • Sets chip output pins to safety states while executing the bypass instruction • Samples the system pins during operation and transparently shift out the result • Selects between JTAG TAP controller and Background Debug Module (BDM) using the MTMOD0 pin 23.1.
PAGE 711
External Signal Description Table 23-2. Pin Function Selected MTMOD0 = 0 MTMOD0 = 1 Pin Name Module selected BDM JTAG — Pin Function — BKPT DSI DSO DSCLK TCK TMS TDI TDO TRST TCK BKPT DSI DSO DSCLK When one module is selected, the inputs into the other module are disabled or forced to a known logic level as shown in Table 23-3, in order to disable the corresponding module. Table 23-3.
PAGE 712
23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK) The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the TAP controller to the test-logic-reset state. The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled and DSO changes state. 23.2.1.
PAGE 713
Memory Map/Register Definition 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 5 4 3 2 1 0 JTAGID W Reset See Table 23-4 Reg Addr MBAR + 0x50 15 14 13 12 11 10 9 8 R 7 6 JTAGID W Reset See Table 23-4 Reg Addr MBAR + 0x50 Figure 23-2. JTAG IDCODE Register Table 23-4. JTAG IDCODE Field Descriptions Bits Name Description 31–0 JTAGID The JTAG identification number register is a read only register which contains the JTAG ID number for the MCF548x.
PAGE 714
23.3.2.6 Boundary Scan Register The boundary scan register is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins. The boundary scan register contains bits for bonded-out and non bonded-out signals excluding JTAG signals, analog signals, power supplies, compliance enable pins, and clock signals. 23.4 23.4.
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Functional Description 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT DR-SCAN SELECT IR-SCAN 1 1 CAPTURE-DR 1 CAPTURE-IR 0 0 0 SHIFT-DR 1 EXIT1-DR 1 EXIT1-IR 1 1 0 0 0 PAUSE-DR 0 PAUSE-IR 1 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 0 0 0 UPDATE-IR 1 0 Figure 23-3. TAP Controller State Machine Flow 23.4.3 JTAG Instructions Table 23-5 describes public and private instructions. F Table 23-5.
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Table 23-5. JTAG Instructions (Continued) 23.4.3.1 Instructio n IR[5:0] CLAMP 011111 Selects bypass while applying fixed values to output pins and asserting functional reset HIGHZ 111101 Selects bypass register while tri-stating all output pins and asserting functional reset ENABLE 000010 Selects TEST_CTRL register BYPASS 111111 Selects bypass register for data operations Instruction Summary External Test Instruction (EXTEST) The EXTEST instruction selects the boundary scan register.
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Initialization/Application Information 23.4.3.4 ENABLE_TEST_CTRL Instruction The ENABLE_TEST_CTRL instruction selects a 3-bit shift register (TEST_CTRL) for connection as a shift path between the TDI and TDO pin. When the user transitions the TAP controller to the UPDATE_DR state, the register transfers its value to a parallel hold register. It allows the control chip to test functions independent of the JTAG TAP controller state. 23.4.3.
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MCF548x Reference Manual, Rev.
PAGE 719
Part IV Communications Subsystem Part IV contains chapters that discuss the operation and configuration of the communications I/O subsystem including the MCF548x multichannel DMA, communications timer, PSC, FEC, DSPI, and USB2, and I2C. Contents Part IV contains the following chapters: • Chapter 24, “Multichannel DMA,” provides an overview of the multichannel DMA controller module including the operation of the external DMA request signals.
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MCF548x Reference Manual, Rev.
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Chapter 24 Multichannel DMA 24.1 Introduction The MCF548x’s direct memory access controller (DMA) module provides a flexible and efficient means to move blocks of data within the system. The multichannel DMA controller reduces the workload on the microprocessor, allowing it to continue execution of system software. The DMA microcode engine is tailored to efficiently transfer data across the internal bus architecture to memory and peripheral devices.
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24.1.2 Overview The DMA controller processes microcode tasks that are stored in memory. A task is a sequence of instructions, referred to as descriptors, that specifies a series of data movements or manipulations. The DMA controller steps through the descriptors and executes the specified function in a similar fashion to a CPU executing a program. 24.1.2.1 Master DMA Engine (MDE) The MDE is the main interpreter for the multichannel DMA.
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External Signals 24.2 External Signals 24.2.1 DREQ[1:0] These active-low inputs provide external requests from peripherals needing DMA service. When asserted, the device is requesting service. Depending on the operating mode, either the level of the signal is sampled at the rising edge of the system clock or an edge detect is used to recognize a high to low change. These inputs have no effect when the task enable control bit is cleared. 24.2.
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24.3.1.3 Variable Table Each task has a private 48-longword variable table. Typically, each variable table must be aligned to a 256-byte boundary, though some may be aligned to a 128-byte boundary if the task uses 32 or less variables. 24.3.1.4 Function Descriptor Table Function descriptor tables are 256-byte tables that hold the operation codes to be passed to the DMA execution units when data manipulation is performed. Each function descriptor table must be aligned to a 256-byte boundary.
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Memory Map/Register Definitions Programmer-Maintained, Located in Memory Task Table Pointed to by TaskBAR Task 0 Pointers, Control Task 1 Pointers, Control Task 2 Pointers, Control Task 3 Pointers, Control Start, End, Variable Table Pointer, Control Task Descriptor Table Task 0 Task 1 Task 2 Task 3 • • • Task 15 Variable Table Pointed to by Task Table Initial Value0 Initial Value1 Initial Value2 Initial Value3 0 1 2 3 Increment0 Increment1 22 23 24 25 •• • 0 1 2 3 4 5 6 7 8 9 10 11 12 13 LCD0 DRD0
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Table 24-1.
PAGE 727
Memory Map/Register Definitions 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 Task Base Address W Reset Uninitialized 15 14 13 12 11 10 9 R 8 7 6 Task Base Address W Reset Uninitialized Reg Addr MBAR + 0x8000 Figure 24-3. Task Base Address Register (TaskBAR) Table 24-2. TaskBAR Field Descriptions Bits Name 31–0 24.3.3.3 Description Task Base Address Task base address. Pointer to the base address of the DMA task table.
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24.3.3.4 End Pointer (EP) 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Descriptor Pointer W Reset Uninitialized 15 14 13 12 11 10 9 R 8 7 Descriptor Pointer W Reset Uninitialized Reg Addr MBAR + 0x8008 Figure 24-5. End Pointer Register (EP) Table 24-4. EP Field Descriptions Bits Name 31–0 Descriptor Pointer 24.3.3.5 Description Descriptor pointer. Pointer to the address of the last DMA descriptor for the currently executing task.
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Memory Map/Register Definitions 24.3.3.6 PTD Control (PTD) The priority task decode control register is used to configure different operating modes of this DMA module. The PTD is also used to enable/disable new functionality designed into the module after the first release of the design.
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24.3.3.7 R DMA Interrupt Pending (DIPR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset R TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK TASK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 MBAR +0x8014 Figure 24-8.
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Memory Map/Register Definitions Table 24-8. DIMR Field Descriptions Bits Name 31–16 — 15–0 TASKn 24.3.3.9 Description Reserved Interrupt mask. Each bit corresponds to an interrupt source defined by the task number. An interrupt is masked by setting the corresponding bit in the IMR. At system reset, all bits are initialized to logic ones.
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Table 24-9. TCRn Field Descriptions (Continued) Bits Name Description 7 ASTRT Auto start. This bit can be set or cleared by the programmer at any time. This bit is also cleared if the MDE encounters an error in the task. At system reset, this bit is cleared.Setting this bit instructs the MDE to start the task indicated by the ASTSKNUM field once the current task completes. 0 Task will not start at end of taskl 1 Task will start at end of task 6 HIPRITSKEN High-priority task enable.
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Memory Map/Register Definitions Table 24-10. PRIOR Field Descriptions Bits Name Description 7 HLD Keep current priority of initiator. This bit can be set or cleared by the programmer at any time. This bit allows the current initiator to hold priority until the initiator has negated or the task has finished. When this bit is cleared, an initiator with a higher priority will block the current initiator and force arbitration. At system reset, this bit is cleared.
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Figure 24-13.
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Memory Map/Register Definitions 31 30 29 28 27 TASK0 R 26 25 24 23 TASK1 22 21 20 19 TASK2 18 17 16 TASK3 SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset TASK4 R TASK5 TASK6 TASK7 SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ SRCSZ DSTSZ 0 0 0 0 0 0 0 0 0 0 0 20 19 18 17 16 W Reset 0 0 0 Reg Addr 0 0 MBAR + 0x8060 (TSKSZ0) Figure 24-14.
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24.3.3.13 Debug Comparator Registers (DBGCOMPn) 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 Comparator Value W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R Comparator Value W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0x8070 Figure 24-16. Debug Comparator Register (DBGCMPn) Table 24-12.
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Memory Map/Register Definitions Table 24-13. Debug Control Field Descriptions Bits 31–16 Name Description Block Tasks Specify for each of tasks 15-0, whether to block that task with detection of a breakpoint 0 Do not block task 1 Block the task 15 AA 14 B AutoArm—The bit specifies whether or not the triggered bit dbgStatusReg[16] will be automatically reset to 0 following the saving of context for a breakpoint. This bit is set to 0 at reset.
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Table 24-15 below shows the encodings for the bits. These bits are set to 101 at reset signifying an uninitialized state. Table 24-15. Comparator 2 Type Bit Encodings Encodings Comparator 2 Type 000 uninitialized 001 write address 010 read address 011 current pointer 100 task # 101 counter value 110 reserved 111 reserved 24.3.3.
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Memory Map/Register Definitions Table 24-16. Debug Status Field Descriptions (Continued) Bits Name Description 16 T Triggered.This bit indicates that a DMA breakpoint has occurred with the current settings. Status bit is sticky and requires a 1 to be written to it to clear it. The writing of a 0 to this bit has no effect. This bit is set to 0 at reset. 0 Armed or normal operation 1 Triggered or debug mode 15–0 Task Blocked Task Blocked. Each bit corresponds to one of the 16 task numbers.
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Table 24-17. PTD Debug Register Descriptions (Continued) Value Written Reg Name 4 taskEnable 5 taskRun 6 dbgTaskBlock 7 alwaysInit PTDDBG[15:0] reflects the state of the ALWINIT bit in each of the Task Control Registers (TCRs). 8 taskStart PTDDBG[15:0] reflects the state of the Auto-start (ASTRT) bit in each task’s control register (TCR). 24.3.4 Description PTDDBG[15:0] reflects the state of the EN (task enable) bit in each of the Task Control Registers (TCRs).
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Memory Map/Register Definitions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R W 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Base Address Reset 0 0 0 0 0 0 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBAR + 0x0D00 (EREQBAR0); 0x0D10 (EREQBAR1) Figure 24-20. External Request Base Address Register 24.3.4.
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Table 24-19. EREQCTRL Field Descriptions Bits Name 31–8 — Reserved, should be cleared. 7–6 MD Mode. This field set the mode of operation of the external request input. This bits are reset to zero. 00 Idle 01 Level Request 10 Edge Request 11 Piped Request 5–4 BSEL Bus Select. This field selects which of the internal buses to make the compare against. These bits are reset to zero.
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Functional Description The details of creating task code is beyond the scope of this document. An API containing pregenerated task code is provided and described in the “Multichannel DMA API User’s Guide”. 24.4.2 Descriptors The DMA controller interprets a series of descriptors that specifies a sequence of data movements and manipulations. A collection of these descriptors is much like a program. The two types of descriptors are loop control descriptors (LCDs) and data routing descriptors (DRDs).
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24.4.5 Prioritization The multichannel DMA has two basic prioritization schemes to decide which task should run when more than one is enabled and its initiator is asserted. These are initiator priority and task priority. When in initiator priority mode, the task with the highest priority active initiator is selected for execution. There are eight priority levels (0-7).
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Functional Description function descriptor table. Each data routing descriptor can use the contents of the function descriptor table to perform different operations. The LURC is programmed to perform its operations on 32-bit operands. The operations can be categorized into four types: two-operand checksum/CRC operations, two-operand boolean operations, two-operand addition and subtraction, and manipulation/shift operations.
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24.4.9 Line Buffers The multichannel DMA makes use of line buffers in its interface to the XL bus to combine writes and to prefetch reads to increase performance. Each line buffer is 32 bytes in depth. The buffer interface has two queues, one for prefetched reads, and another for collecting writes. There are two line buffers in the write queue. Each buffer keeps byte validity, and has a tag address valid on the line boundary. There are four read line buffers.
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Programming Model 24.4.10 Termination of Loop While executing an inner loop, there are two ways to terminate that loop: 1. Loop-termination conditions have been met. A loop is allowed one termination condition. For example, this could be a byte count for a number of taps in a filter application. 2. The FIFO indicates the end of a full “packet” of information. This response could come from intelligent peripherals which can recognize frame boundaries in a supported protocol, such as an Ethernet controller.
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4. Priority registers - These will typically only be set during initialization, but can be changed during operation if desired. 5. Initiator Mux Control register - This will typically be set up during configuration and will be dependent on what modules of the chip which the system is using. 6. Task Size registers - The Task Size registers may or may not need to be initialized. These registers may not be used by a task if the task has hardcoded what transfer sizes to use in its DRDs.
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Programming Model The base address for context save space is used to save variables and values being used by the MDE and ADS. For each task, an area needs to be set aside for all relevant data to be saved until the task is called again.
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Table 24-20. Behavior of Task Table Control Bits (Continued) Bit Name 3 I 2 SP Speculative Prefetch 0 Do not enable speculative prefetch 1 Enable speculive prefetch 1 CW Combined Write Enable 0 Do not enable combined writes 1 Enable combined writes 0 RL Read Line Buffer Enable 0 Do not enable line reads 1 Enable line reads 24.
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Timing Diagrams DACKto assert (clock 5). The next falling edge of DREQ occurs during clock 8, causing the internal request to assert on the rising edge of clock 9. 0 1 2 3 4 5 6 7 8 9 10 CLK DREQ Internal DMA Request Internal DMA Acknowledge DACK Figure 24-25. Edge-Triggered External Request Timing 24.6.3 Pipelined Requests Figure 24-26 shows the timing for pipelined external requests.
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MCF548x Reference Manual, Rev.
PAGE 753
Chapter 25 Comm Timer Module (CTM) 25.1 Introduction This chapter contains a detailed description of the Comm Timer Module (CTM). 25.1.1 Block Diagrams The following section presents three block diagrams showing the CTM in greater detail. Figure 25-1 is a high level block diagram of the CTM. The figure shows the signal flow through the sub-modules and the architecture on a high level.
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cAcknowledge Internal Bus clk Miscellaneous Block mode source[3:0] percent[1:0] Percent 15-bit Percent (High Time) Counter Register timerInterrupt Comparators counterReference[15:0] cInitiator 16-bit Period Counter TCRselect dataRd[23:0] Figure 25-2.
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Memory Map/Register Definition The fixed timer channel provides the user with two modes, a programmable baud clock generator mode or a fixed period task initiator mode. • In baud clock generator mode the fixed timer channel outputs a cInitiator signal that is free running. • In fixed period task initiator mode the fixed timer channel outputs a cInitiator signal in response to a cAcknowledge input from the multichannel DMA’s PTD (priority task decode).
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Table 25-2.
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Memory Map/Register Definition Table 25-3. CTCRn—Fixed Timer Channel Field Descriptions Bits Name Description 31 I Interrupt. This bit is set whenever the timerInterrupt signal asserts in the fixed timer. This indicates that the cAcknowledge signal has arrived too far into the current cycle to be completed within that period or that it was too short in duration to satisfy the request. Writing a 1 will clear the bit. 0 Indicates that no interrupt has occurred or is pending.
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NOTE The initiator mode is different from that of a fixed channel in that the period is variable . 31 30 29 28 27 0 0 0 S M 0 0 0 0 1 1 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 1 1 R 26 25 24 23 22 21 20 19 18 17 16 1 1 1 1 1 5 4 3 2 1 0 1 1 1 1 1 1 PCT CRV W Reset R CRV W Reset 1 1 1 Reg Addr 1 1 1 1 1 MBAR + 0x7F10 (CTCR4); + 0x7F14 (CTCR5); + 0x7F18 (CTCR6); + 0x7F1C (CTCR7) Figure 25-5.
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Functional Description 25.3 Functional Description 25.3.1 Variable Timer in Baud Clock Generator Mode In baud clock generator mode, the functionality is the same for both fixed and variable timer channels. The only difference is the variable timer channel has a 24-bit reference value, and the fixed channel timer only has a 16-bit reference value.
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is deasserted, and the percent counter stops counting and retains a value of 0x3. As before the cInitiator signal remains asserted because the percent counter has not timed out. At the rising edge of the clock in cycle 13 the cAcknowledge signal is asserted for the third time, and the percent counter begins to count. At the rising edge of the clock in cycle 14 the cAcknowledge signal is deasserted, and the percent counter stops counting and retains a value of 0x4.
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Functional Description At the rising edge of the clock in cycle 8, the cAcknowledge signal is asserted. At that point the percent counter begins to count. At the rising edge of clock 10, cAcknowledge is deasserted and the counter reaches the high time value. As a result of the counter reaching the high time value (2), cInitiator is deasserted. The counter does not stop counting; however, it continues to count toward the period reference value (8).
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MCF548x Reference Manual, Rev.
PAGE 763
Chapter 26 Programmable Serial Controller (PSC) 26.1 Introduction This chapter describes the MCF548x programmable serial controller (PSC). 26.1.1 Block Diagram A block diagram of the PSC/IrDA module is shown in Figure 26-1 below. Modem Control IP Bus UART SIR CODEC Mux Comm Bus Control Registers Soft Modem Bus Interface FIFOs MUX Serial Ports MIR CODEC FIR CODEC Figure 26-1. PSC/IrDA Block Diagram 26.1.2 Overview The PSC/IrDA module provides asynchronous, synchronous, and IrDA 1.
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• • • • • • • Backward compatible with the MC68681 — 5,6,7,8 bits data plus parity — Odd, even, none, or force parity — Stop bit width programmable in 1/16 bit increments — Parity, framing, and overrun error detection — Automatic PSCnCTS and PSCnRTS modem control signals IrDA 1.0 SIR mode (SIR) — Baud rate range: 2400 to 115200 bps — Selectable pulse width: either 3/16 bit duration or 1.6 us. IrDA 1.1 MIR mode (MIR) — Baud rate: 0.576 Mbps or 1.152 Mbps. IrDA 1.1 FIR mode (FIR) — Baud rate: 4.
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Memory Map/Register Definition 26.2.4 PSCnTXD PSCnTXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. The PSCnTXD signals can be programmed to be driven low (break status) by a command. Refer to Section 26.3.3.5, “Command Register (PSCCRn),” for information about how to program this signal function. 26.2.
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MBAR Offset Name PSC0 PSC1 PSC2 0x860C 0x870C 0x880C 0x890C 0x8610 0x8614 0x8618 0x8710 0x8714 0x8718 0x8810 0x8814 0x8818 Byte0 Byte1 Byte2 Byte3 PSC3 0x8910 0x8914 Access Table 26-2.
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Memory Map/Register Definition MBAR Offset Name PSC0 PSC1 PSC2 Byte0 Byte1 Byte2 Byte3 PSC3 0x868E 0x878E 0x888E 0x898E Access Table 26-2.
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Table 26-3. PSCMR1n Field Descriptions Bits Name Description 7 RXRTS Receiver request-to-send (UART and SIR modes only). Allows the PSCnRTS output to control the PSCnCTS input of the transmitting device to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for PSCnRTS control, PSCnRTS control is disabled for both. Transmitter RTS control is configured in PSCMR2n[TxRTS]. 0 The receiver has no effect on PSCnRTS.
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Memory Map/Register Definition 7 R 6 5 4 3 2 1 0 CM TXRTS TXCTS CM TXRTS TXCTS 0 0 0 0 SIR CM 0 0 0 0 0 0 All other modes 0 0 0 0 0 0 SB Mode UART W R W R W Reset 0 Reg Addr 0 MBAR + 0x8600 (PSC0); 0x8700 (PSC1); 0x8800 (PSC2); 0x8900 (PSC3) Figure 26-3. PSC Mode Register 2 (PSCMR2n) Table 26-4. PSCMR2n Field Descriptions Bits Name 7–6 CM 5 TXRTS Description Channel mode (all modes). Selects a channel mode. Section 26.4.
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Table 26-4. PSCMR2n Field Descriptions Bits Name Description 4 TXCTS Transmitter clear-to-send (UART and SIR modes). If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. 0 PSCnCTS has no effect on the transmitter. 1 Enables clear-to-send operation. The transmitter checks the state of PSCnCTS each time it is ready to send a character.
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Memory Map/Register Definition Table 26-5. PSCSRn Field Descriptions Bits Name 15 RB_NEOF Description For UART and SIR modes, this field signifies a received break. 0 No break received. 1 Break received. For modem mode, this field is reserved. In MIR and FIR mode, this bit signifies a next byte is EOF. 0 The next byte to be read from the RxFIFO is not the last one of the frame. 1 The next byte to be read from the RxFIFO is the last one of the frame. This bit is effective when RxRDY = 1.
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Table 26-5. PSCSRn Field Descriptions (Continued) Bits Name Description 9 FU For all modes, this field signifies that the RxFIFO is full. 0 The number of data in the RxFIFO is less than the threshold or the number of data is more than the granularity after exceeding the threshold. 1 The number in RxFIFO is more than the threshold. This bit becomes low after reading enough data from RxFIFO and the number in it becomes less than the granularity.
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Memory Map/Register Definition The upper 4 bits set the receiver and the lower 4 bits set the transmitter clock source. To use the system bus clock for both the transmitter and receiver, program the PSCCSR with 0xDD. It is possible to program the transmitter and the receiver with different clock sources. 7 6 5 4 3 2 1 0 0 1 R RCSEL W Reset 1 Reg Addr 1 TCSEL 0 1 1 1 MBAR + 0x8604 (PSC0); 0x8704 (PSC1); 0x8804 (PSC2); 0x8904 (PSC3) Figure 26-6.
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Table 26-7. PSCCRn Field Descriptions Bits Value 7 Command — Description Reserved, should be cleared. 6–4 MISC Field (This field selects a single command.) 000 NO COMMAND — 001 RESET MODE Causes the mode register pointer to point to PSCMR1n. REGISTER POINTER 010 RESET RECEIVER The receiver and RxFIFO are immediately reset. The receiver is disabled. The FU and RxRDY bits in the PSCSR are cleared and RxFIFO is initialized. All other registers are unaltered.
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Memory Map/Register Definition Table 26-7. PSCCRn Field Descriptions (Continued) Bits Value Command 3–2 Description TXC Field (This field selects a single command) 00 NO ACTION TAKEN The transmitter stays in its current mode. 01 TRANSMITTER This command enables operation of the transmitter. If the transmitter is already enabled, this ENABLE command has no effect. • In UART and SIR mode, the TxEMP and TxRDY bits in PSCSR are also asserted.
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Table 26-7. PSCCRn Field Descriptions (Continued) Bits Value Command 1–0 Description RXC Field (This field selects a single command) 00 NO ACTION TAKEN The receiver stays in its current mode. 01 RECEIVER ENABLE This command enables operation of the receiver. If the receiver is already enabled, this command has no effect. • In UART mode, if the parity mode is not multidrop mode, this command enables the receiver and forces the receiver to search for start bit state.
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Memory Map/Register Definition 31 30 29 28 27 26 25 24 23 22 21 20 R RB RB W TB TB Reset 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R RB RB W TB TB Reset 19 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 0 MBAR + 0x860C (PSC0); 0x870C (PSC1); 0x880C (PSC2); 0x890C (PSC3) Figure 26-9.
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31 30 29 28 27 26 25 24 23 R RB[19:4] W TB[19:4] Reset 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R RB[3:0] W TB[3:0] Reset 22 0 0 Reg Addr 0 0 MBAR + 0x860C (PSC0); 0x870C (PSC1); 0x880C (PSC2); 0x890C (PSC3) Figure 26-11.
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Memory Map/Register Definition Table 26-10. PSCRBn and PSCTBn AC 97 Mode Field Descriptions Bits Name 11 SOF 10–0 — 26.3.3.7 Description Start of frame. 1 RB/TB contains the first sample in the frame. This is also known as the TAG slot. Bits 31–16 contain the valid data 0 RB/TB contains valid data in bits 31–12. This data is not the first sample in a new frame. Reserved, should be cleared.
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26.3.3.8 Auxiliary Control Register (PSCACRn) PSCACR controls the handshake of the transmitter/receiver. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset IEC0 0 Reg Addr 0 0 0 0 0 0 0 MBAR + 0x8610 (PSC0); 0x8710 (PSC1); 0x8810 (PSC2); 0x8910 (PSC3) Figure 26-13. Auxiliary Control Register (PSCACRn) Table 26-12. PSCACRn Field Descriptions Bits Name 7–1 — 0 IEC0 26.3.3.9 Description Reserved, should be cleared. Interrupt enable control for D_CTS.
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Memory Map/Register Definition Table 26-13. PSCISRn Field Descriptions Bits Name 15 IPC 14–11 — Reserved, should be cleared. 10 DB In UART / SIR, this is a Delta break. The receiver detected the beginning or the end of a break condition. In other modes, this is reserved. 9 RXRDY FU Descriptions Input port change. This bit is set when PSCIPCRn[D_CTS] and PSCACRn[IEC0] are set. Receive data is ready. (selected if PSCMR1[6] = 0) 0 There is no data in the RxFIFO.
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15 R IPC 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Mode RXRDY_FU TXRDY DEOF ERR 0 0 0 0 0 0 MIR / FIR RXRDY_FU TXRDY 0 0 0 0 0 0 W R IPC 0 ERR Modem W R IPC 0 0 0 0 DB RXRDY_FU TXRDY 0 ERR 0 0 0 0 0 0 UART W R IPC 0 0 0 0 DB RXRDY_FU TXRDY DEOF ERR 0 0 0 0 0 0 SIR W Reset 0 0 Reg Addr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBAR + 0x8614 (PSC0); 0x8714 (PSC1); 0x8814 (PSC2); 0x8914 (PSC3) Figure 26-15.
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Memory Map/Register Definition 26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn) These registers hold the upper and lower bytes of the preload value to be used by the PSC timer in order to provide a given baud rate. 7 6 5 4 R 3 2 1 0 CT[15:8] UART / SIR W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr Mode All other modes MBAR + 0x8618 (PSC0); 0x8718 (PSC1); 0x8818 (PSC2); 0x8918 (PSC3) Figure 26-16. Counter Timer Upper Register (PSCCTURn) Table 26-15.
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Table 26-17. PSCIPn Field Descriptions (Continued) Bits Name 5–1 — 0 CTS Description Reserved, should be cleared. Current state of the PSCnCTS input 0 PSCnCTS is low 1 PSCnCTS is high 26.3.3.13 Output Port Bit Set (PSCOPSETn) Output ports are asserted by writing to this register. Table 26-18. PSCOPSETn Field Descriptions Bits Name 7–1 — 0 RTS Description Reserved, should be cleared. This field is reserved in AC97 mode.
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Memory Map/Register Definition 26.3.3.15 PSC/IrDA Control Register (PSCSICRn) This register sets the main operation mode. Table 26-20. PSCSICRn Field Descriptions Bits Name Descriptions 7 ACRB This field is reserved in UART, SIR, MIR, FIR, and modem modes. In AC97 mode, this bit signifies Cold Reset to the transceiver in PSC 0 The transceiver recovers from low power mode in AC97. 1 The transceiver stays in the current state. This bit is included for compatibility with USART.
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26.3.3.16 Infrared Control Register 1 (PSCIRCR1n) This register controls the configuration in IrDA mode. Table 26-22. PSCIRCR1n Field Descriptions Bits Name Description 7–4 — Reserved, should be cleared. 2 FD In MIR, FIR, SIR, and modem modes, this bit signifies full duplex enable. 0 The receiver in IrDA mode is disabled while the transmitter is busy. 1 The receiver in IrDA mode is not disabled while the transmitter is busy. This bit should not be set in usual operations.
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Memory Map/Register Definition Table 26-23. PSCIRCR2n Field Descriptions (Continued) Bits Name 1 ABORT Descriptions In most modes this bit is reserved. In MIR and FIR mode, this bit signifies abort output. 0 Stop sending abort sequence. 1 While the transmitter is sending data or CRC, writing 1 to this bit causes the transmitter immediately start to output abort sequence (2 or more illegal symbol “0000” in FIR mode, or 7 or more consecutive in MIR mode).
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Table 26-25. PSCIRMDRn Field Descriptions Bits Name 7 FREQ Description Applies only in MIR mode; in all other modes, this field is reserved. In MIR mode, this bit signifies 0.576 Mbps mode. 0 The baud rate is 1.152 Mbps. 1 If the baud rate is 0.576 Mbps, this bit should be set high in order to output 1.6 us SIP. 6–0 M_FDIV Applies only in MIR mode; in all other modes, this field is reserved. In MIR mode, this bit signifies clock divide ratio. The bit frequency is derived by the following equation.
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Memory Map/Register Definition Table 26-27. PSCIRFDRn Field Descriptions Bits Name Description 7–4 — 3–0 F_FDIV Reserved, should be cleared. Applies only in FIR mode; in all other modes, this field is reserved. In FIR mode, this field signifies clock divide ratio. The bit frequency is derived by the following equation. f bit_clk f bit = ----------------------------Eqn. 26-2 F_FDIV + 1 This bit frequency should be 8 MHz.
PAGE 790
Reads from the PSCRFDRn register return received data from the Rx FIFO. In addition, this register provides the possibility to fill the Rx FIFO for software development/debug purposes. Writes to the PSCTFDRn register write data into the Tx FIFO. In addition, this register provides the possibility to read data back from the Tx FIFO for software development/debug purposes. Refer to Section 26.3.3.6, “Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn)”, for more information about the data formats.
PAGE 791
Memory Map/Register Definition Table 26-30. PSCRFSRn and PSCTFSRn Field Descriptions Bits Name Description 15 IP Illegal pointer. This bit signifies an illegal pointer condition in the FIFO controller. A 1 in this bit will cause a FIFO error condition in the PSCISR. This bit will remain set until a 1 is written to this bit location. 0 No illegal pointer condition. 1 An address outside the FIFO controller’s memory range has been written to one of the user-visible pointers.
PAGE 792
Table 26-30. PSCRFSRn and PSCTFSRn Field Descriptions (Continued) Bits Name Description 2 FU FIFO full alarm. This read only bit indicates that the FIFO is full. The FIFO must be read to clear this alarm. 0 FIFO is not full. 1 FIFO has requested attention because it is full. The FIFO must be read to clear this alarm. 1 ALARM Alarm. This read-only bit indicates that the FIFO has determined an alarm condition.
PAGE 793
Memory Map/Register Definition 31 30 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 R 29 28 27 26 WFR TIMER FRMEN 25 24 GR IP_ MSK W Reset R 23 22 21 20 FAE_ RXW UF_ MSK _MSK MSK 19 18 17 16 0 0 0 0 0 3 2 1 0 0 0 0 0 OF_ TXW_ MSK MSK CNTR W Reset 0 Reg Addr 0 0 0 0 0 0 1 MBAR + 0x8668 (PSCRFCR0); 0x8768 (PSCRFCR1); 0x8868 (PSCRFCR2) ; 0x8968 (PSCRFCR3) and MBAR + 0x8688 (PSCTFCR0); 0x8788 (PSCTFCR1); 0x8888
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Table 26-31. PSCRFCRn and PSCRTFCRn Field Descriptions (Continued) Bits Name 21 Description RXW_MSK Receive wait condition mask. When this bit is set, the FIFO controller masks the status register’s RXW bit from generating an error. 20 UF_MSK FIFO underflow mask. When this bit is set, the FIFO controller masks the status register’s UF bit from generating an error. 19 OF_MSK FIFO overflow mask. When this bit is set, the FIFO controller masks the status register’s OF bit from generating an error.
PAGE 795
Memory Map/Register Definition provided through a port to the FIFO controller. The read pointer can be both read and written. This ability facilitates the debug of the FIFO controller and peripheral drivers.
PAGE 796
there are no safeguards to prevent retransmitting data which has been overwritten. When FRMEN in the PSCRFCR and PSCTFCR is cleared, then this pointer has no meaning. The last read frame pointer is reset to zero, and non-functional bits of this pointer will always remain zero.
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Functional Description Table 26-36. PSCRLWFPn / PSCTLWFPn Field Descriptions Bits Name 15–9 — 8–0 LWFP 26.4 Description Reserved, should be cleared. Last write frame pointer. FIFO-maintained pointer which indicates the start of the last frame written into the FIFO. This register can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates which point to begin retransmission of the data frame.
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PSCnTXD C1 C2 C3 Break C4 Start Break Write C4 End Break Write C5 C5 Transmitter Enabled PSCnRTS PSCnCTS Module_En_B Command from Bus Enable Assert TX RTS Write C1 Write C2 Write C3 Disable TX Figure 26-28. Modem Control and Transmitter If PSCnRTS is programmed to be RxRTS, the PSCnRTS output is automatically asserted and negated by the receiver.
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Functional Description A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of PSCMR1. PSCMR1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled.
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PSCBCLK PSCFSYNC PSCnTXD D7 D6 D5 D4 D3 D2 D1 D0 PSCnRXD D7 D6 D5 D4 D3 D2 D1 D0 DTS1 = 0 & SHDIR = 0 PSCBCLK PSCFSYNC PSCnTXD D0 D1 D2 D3 D4 D5 D6 D7 PSCnRXD D0 D1 D2 D3 D4 D5 D6 D7 DTS1 = 0 & SHDIR = 1 PSCBCLK PSCFSYNC PSCnTXD D7 D6 D5 D4 D3 D2 D1 D0 PSCnRXD D7 D6 D5 D4 D3 D2 D1 D0 DTS1 = 1 & SHDIR = 0 PSCBCLK PSCFSYNC PSCnTXD D0 D1 D2 D3 D4 D5 D6 D7 PSCnRXD D0 D1 D2 D3 D4 D5 D6 D7 DTS1 = 1 & SHDIR = 1 Figure 26-30.
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Functional Description PSCBCLK PSCFSYNC PSCnTXD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PSCnRXD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 26-31. Waveform of Modem16 Mode The function of this mode is the same as 8-bit modem mode except that the transmit/receive data length is 16 bit. 26.4.5 AC97 Mode Figure 26-32 shows the waveform in AC97 modem mode. 20.8 µs (48.0 kHz) 81.4 ns (12.
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26.4.5.1 Transmitter The transmitter starts to transmit the first bit at the one clock after the rising edge of the frame sync. The first slot, slot #0, is 16 bits wide while the other slot, from slot #1 to slot #12, is 20 bits wide. Because the transmit order is the MSB first, the SHDIR bit in the PSCSICR should be a value 0. The transmitter keeps the output low until the receiver detects the ‘CODEC ready’ condition, which is indicated by a high in the first bit of a new frame.
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Functional Description Leaving low power mode can be done via either a warm or cold reset (Figure 26-34). The CPU performs a warm reset by writing a 1 to the AWR bit of SICR register for a minimum of 1 us. The AWR bit forces a 1 on PSCnRTS, which is used as the frame sync output in AC97 mode. The pulse width of warm or cold reset should be dependent on AC97 codec chip. RESET PSCFSYNC PSCBCLK PSCBCLK Cold reset Warm reset Figure 26-34. AC97 Cold and Warm Reset 26.4.
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The STA represents the start of the frame and the STO represents the end of the frame. Both of STA and STO are defined as 01111110 in binary format. In the transmitted data and FCS, a 0 is inserted after 5 consecutive 1s. The FCS is a 16-bit CRC defined as: CRC ( x ) = x 26.4.7.2 16 +x 12 5 +x +1 Eqn. 26-3 Serial Interaction Pulse (SIP) The MIR and FIR system must emit SIP at least once per 500ms while the connection lasts, in order to inform slower systems (SIR) not to interfere with the link.
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Functional Description . Table 26-38. Chip Patterns for FIR Fields PA 1000 0000 1010 1000 (16 times repeated) STA 0000 1100 0000 1100 0110 0000 0110 0000 STO 0000 1100 0000 1100 0000 0110 0000 0110 first chip 26.4.9 last chip PSC FIFO System The receive FIFO stack consists of the FIFO and a receiver shift register connected to the RxD. Data is assembled in the receiver shift register and loaded into the FIFO at the location pointed to by the FIFO write pointer.
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are unaffected, and PSCSRn[ERR] sets when the receiver detects the start bit of the new overrunning character. To support flow control, the receiver can be programmed to automatically negate and assert RTS. In which case, the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full. The receiver asserts RTS when a FIFO position becomes available. Overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device.
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Functional Description NOTE In AC97, the number of data bytes are four times the number of time slot samples in the FIFO. Because, each 20-bit sample uses an entire 32-bit longword in the FIFO. For the Rx FIFO, the value can be between 0 and 7 bytes only. Therefore, the interrupt has hysteresis. For example, the interrupt goes active when the Rx FIFO is “almost full” (i.e., the amount of empty space is less than the alarm level).
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26.4.10 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 26-42. These modes are useful for local and remote system diagnostic functions, and can be used in modem mode and IrDA mode as well as UART mode. The modes are described in the following paragraphs. PSCnRXD RX TX disabled PSCnTXD Automatic echo disabled RX PSCnRXD PSCnTXD TX Local loop back RX TX disabled disabled PSCnRXD PSCnTXD Remote loop back Figure 26-42.
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Resets is ignored, the TxD is held marking, and the receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be enabled. 26.4.10.3 Remote Loopback Mode In this mode, the channel automatically transmits received data on the TxD output on a bit-by-bit basis. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. While in this mode, the receiver clock is used for the transmitter.
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26.6 Interrupts This section describes interrupts originated by this module. Table 26-40. Interrupt Summary Interrupt Mode Source Description Processor Interrupt UART IPC The state of the modem control input ports had changed and a certain time has passed. DB Detected delta break. The input port RXD has kept low for a certain time.
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Software Environment 26.7.2 26.7.2.1 Configuration UART Mode The following is a sample initialization sequence for UART mode. Table 26-41. Sample Initialization Sequence for UART Mode Step No. Register Value Details Meaning 1 PSCSICR 08 RxDCD=1 DCD input effects receiver SIM[2:0]=000 UART mode RCS[3:0]=1101 Receiver baud rate is made from PSC timer TCS[3:0]=1101 Transmitter baud rate is made from PSC timer CT[15:0]=108 (dec) Divide sys_clk by 108. If f(sys_clk) = 33.
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Table 26-41. Sample Initialization Sequence for UART Mode (Continued) Step No.
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Software Environment Table 26-42. Sample Initialization Sequence for Modem8 Mode (Continued) Step No. Register Value Details Meaning 5 PSCTFCR 0F WRITE TAG=00 Not EOF FRMEN=1 Enable frame mode GR[2:0]=100 Granularity is 16 byte 6 PSCRFAR 00F0 ALARM[8:0]=0F0 Request is asserted if # of data >= 240 7 PSCTFAR 00F0 ALARM[8:0]=0F0 Request is asserted if # of empty >= 240 8 PSCCR 05 TC=01 Enable transmitter RC=01 Enable receiver 26.7.2.
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Table 26-43. A Sample Initialization Sequence for AC97 Mode (Continued) Step No. Register Value Details 6 PSCRFAR 00F0 ALARM[8:0]=0F0 Request is asserted if # of data >= 240 7 PSCTFAR 00F0 ALARM[8:0]=0F0 Request is asserted if # of empty >= 240 8 PSCCR 05 TC=01 Enable transmitter RC=01 Enable receiver 26.7.2.5 Meaning SIR Mode Here is a sample configuration sequence in SIR mode. Table 26-44. A Sample Initialization Sequence for SIR Mode Step No.
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Software Environment Table 26-44. A Sample Initialization Sequence for SIR Mode (Continued) Step No. 8 Register Value PSCMR2 07 Details CM[1:0]=00 PSCIRCR1 00 Normal mode (not test mode) TxRTS=0 PSCnRTS is not controlled by transmitter TxCTS=0 PSCnCTS does not control transmitter SB[3:0]=0111 9 Meaning FD=0 SPUL=1 1 stop bit Receiver is disabled while transmitting Pulse width is 1.6 us 10 PSCIRSTR 36 IRSTIM=54 (dec) Counter value for 1.
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Table 26-45. A Sample Initialization Sequence for MIR Mode (Continued) Step No.
PAGE 817
Software Environment Table 26-46. A Sample Initialization Sequence for FIR Mode (Continued) Step No.
PAGE 818
After initialization and after enabling the receiver, the receiver is ready to receive data. While receiving serial data, the receiver will eliminate STA and STO, and these flags are not written into the FIFO. After receiving enough data, PSC asserts request/interrupt to prompt the processor to read the received data. 26.7.3.2 FIR Mode After initialization, writing data to the TB and enabling the transmitter sends data via the PSCnTXD port. The PA, STA, CRC (option), and STO are automatically added.
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Chapter 27 DMA Serial Peripheral Interface (DSPI) This chapter describes the use of the DMA serial peripheral interface (DSPI) implemented on the MCF548x processor. 27.1 Overview The DMA serial peripheral interface (DSPI) block provides a synchronous serial bus for communication between an MCU and an external peripheral device. The DSPI supports up to eight queued SPI transfers (four receive and four transmit) in the DSPI resident FIFOs eliminating CPU intervention between transfers.
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27.3 Block Diagram Figure 27-1 shows a DSPI with external queues in system RAM. CommBus DSPI DMA & Interrupt Control RX FIFO TX FIFO CMD Data 16 Data 16 Shift Register DSPISOUT DSPISIN SPI Baud Rate, Delay and Transfer Control DSPISCK 4 DSPICSn/SS/PCSS Figure 27-1. DSPI with Queues and DMA 27.4 Modes of Operation The DSPI has two modes of operation: master and slave. The two modes are entered by host software writing to a register. 27.4.
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Signal Description 27.5 Signal Description 27.5.1 Overview Table 27-1 lists the DSPI signals. Table 27-1.
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27.5.2.4 DSPI Serial Input (DSPISIN) DSPISIN is a serial data input signal. 27.5.2.5 DSPI Serial Output (DSPISOUT) DSPISOUT is a serial data output signal. 27.5.2.6 DSPI Serial Clock (DSPISCK) DSPISCK is a synchronous serial communication clock signal. In master mode, the DSPI generates the DSPISCK. In slave mode, DSPISCK is an input from an external bus master. 27.6 Memory Map and Registers Table 27-2 shows the DSPI memory map. Table 27-2.
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Memory Map and Registers 27.6.1 DSPI Module Configuration Register (DMCR) The DMCR contains bits which configure various attributes associated with DSPI operation. The HALT bit can be changed at any time but will only take effect on the next frame boundary. Only the HALT bit in the DMCR may be changed while the DSPI is in the running state.
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Table 27-3. DMCR Field Descriptions (Continued) Bits Name Description 25 PCSSE Peripheral chip select strobe enable. Selects between the DSPICS5 and PCSS functions. See Section 27.7.3.5, “Peripheral Chip Select Strobe Enable (PCSS)” for more information. 0 DSPICS5/PCSS is used as the DSPICS5 signal 1 DSPICS5/PCSS is used as PCSS peripheral strobe signal 24 ROOE Receive FIFO overflow overwrite enable.
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Memory Map and Registers Table 27-3. DMCR Field Descriptions (Continued) Bits Name 7–1 — 0 HALT 27.6.2 Description Reserved, should be cleared. Halt. Provides a mechanism for software to start and stop DSPI transfers. See Section 27.7.1, “Start and Stop of DSPI Transfers” for details on the operation of this bit. 0 Start transfers 1 Stop transfers on the next frame boundary DSPI Transfer Count Register (DTCR) The DTCR contains a counter that indicates the number of SPI transfers made.
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an SPI master, the DTFR[CTAS] field in the command portion of the Tx FIFO entry selects which of the DCTAR registers is used. In slave mode, a subset of the bitfields in only the DCTAR0 registers are used to set the slave transfer attributes. See the individual bit descriptions of this register for details on which bits are used in slave modes.
PAGE 827
Memory Map and Registers Table 27-5. DCTAR Field Descriptions (Continued) Bits Name Description 21–20 PASC After DSPISCK delay prescaler. The PASC field selects the prescaler value for the delay between the last edge of DSPISCK and the negation of DSPICS. This field is only used in master mode.
PAGE 828
Table 27-5. DCTAR Field Descriptions (Continued) Bits Name Description 7–4 DT Delay after transfer scaler. The DT field selects the delay after transfer scaler. This field is only used in master mode. The delay after transfer is the time between the negation of the DSPICS signal at the end of a frame and the assertion of DSPICS at the beginning of the next frame. Table 27-7 lists the scaler values.
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Memory Map and Registers Table 27-7. Scaler for CS to DSPISCK Delay, After DSPISCK Delay, and Delay After Transfer (Continued) CSSCK / ASC / DT Setting PCS to DSPISCK Delay Scaler Value CSSCK / ASC / DT Setting PCS to DSPISCK Delay Scaler Value 0110 128 1110 32768 0111 256 1111 65536 Table 27-8. DSPI Baud Rate Scaler 27.6.
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Table 27-9. DSR Field Descriptions Bits Name Description 31 TCF Transfer complete flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF bit is set at the end of the frame transfer. The TCF bit remains set until cleared by software. 0 Transfer not complete 1 Transfer complete 30 TXRXS Transmit and receive status. The TXRXS bit reflects the status of the DSPI. See Section 27.7.
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Memory Map and Registers Table 27-9. DSR Field Descriptions (Continued) Bits Name Description 15–12 TXCTR Transmit FIFO counter. The TXCTR field indicates the number of valid entries in the Tx FIFO. The TXCTR is incremented every time the DRFR is written. The TXCTR is decremented every time an SPI command is executed and the SPI data is transferred to the shift register. 11–8 TXPTR Transmit next pointer. The TXPTR field indicates which Tx FIFO entry will be transmitted during the next transfer.
PAGE 832
DIRSR Field Descriptions Bits Name Description 31 TCFE Transfer complete flag interrupt enable. The TCFE bit enables TCF flag in the DSR to generate an interrupt request. 0 TCF interrupts are disabled 1 TCF interrupts are enabled 30–29 — 28 EOQFE End of queue flag interrupt enable. The EOQFE bit enables the EOQF flag in the DSR to generate an interrupt request. 0 EOQ interrupts are disabled 1 EOQ interrupts are enabled 27 TFUFE Transmit FIFO underflow flag interrupt enable.
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Memory Map and Registers 27.6.6 DSPI Tx FIFO Register (DTFR) The DTFR provides a means to write to the Tx FIFO. SPI commands and data written to this register are transferred to the Tx FIFO. See Section 27.7.2.4, “Tx FIFO Buffering Mechanism” for more information. 8- or 16-bit write accesses to the DTFR will transfer 32 bits to the Tx FIFO.
PAGE 834
Table 27-10. DTFR Field Descriptions (Continued) Bits Name Description 26 CTCNT Clear SPI_TCNT. The CTCNT provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the SPI_TCNT field in the DTCR register. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. 0 Do not clear DTCR[SPI_TCNT] 1 Clear DTCR[SPI_TCNT] 25–22, 20, 17 — 21, 19, 18, 16 CSn 15–0 TXDATA 27.6.7 Reserved, should be cleared. DSPI chip select.
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Memory Map and Registers 27.6.8 DSPI Tx FIFO Debug Registers 0–3 (DTFDRn) The DTFDRn registers provide visibility into the Tx FIFO for debugging purposes. Each register is an entry in the Tx FIFO. The registers are read-only and cannot be modified. Reading the DTFDRn registers does not alter the state of the Tx FIFO .
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset R RXDATA W Reset 0 0 0 0 0 0 Reg Addr 0 0 0 MBAR + 0x8A7C–8A88 Figure 27-10. DSPI Rx FIFO Debug Register (DRFDR_x) Table 27-13. DRFDR_x Field Descriptions 27.7 Bits Name 31–16 — 15–0 RXDATA Description Reserved, should be cleared.
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Functional Description DSPI Master DSPISIN Shift Register DSPISOUT Baud Rate Generator DSPI Slave SOUT Shift Register SIN DSPISCK SCK DSPICSn SS Figure 27-11. SPI Serial Protocol Overview The DSPI has four peripheral chip select signals that are used to select which of the slaves to communicate with: DSPICS5, DSPICS3, DSPICS1, and DSPICS0. The transfer rate and delay settings are described in section Section 27.7.3, “DSPI Baud Rate and Clock Delay Generation.” 27.7.
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Table 27-14.
PAGE 839
Functional Description for successful communication with an SPI master. These SPI slave mode transfer attributes are set in the DCTAR0. 27.7.2.3 FIFO Disable Operation The FIFO disable mechanisms allow SPI transfers without using the Tx FIFO or Rx FIFO. The DSPI operates as a double-buffered simplified SPI when the FIFOs are disabled. The Tx and Rx FIFOs are disabled separately. The Tx FIFO is disabled by setting DMCR[DTXF]. The Rx FIFO is disabled by setting DMCR[DRXF].
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27.7.2.5 Rx FIFO Buffering Mechanism The Rx FIFO functions as a buffer for data received on the DSPISIN signal. The Rx FIFO holds from 1 to 16 received SPI data frames. SPI data is added to the Rx FIFO at the completion of a transfer when the received data in the shift register is transferred into the Rx FIFO. SPI data is removed (popped) from the Rx FIFO by reading the DRFR. Rx FIFO entries can only be removed from the Rx FIFO by reading the DRFR or by flushing the Rx FIFO.
PAGE 841
Functional Description 27.7.3.1 Baud Rate Generator The baud rate is the frequency of the DSPI serial communication clock (DSPISCK). The system clock fsys is divided by a prescaler (PBR) and scaler (BR) to produce DSPISCK. The PBR and BR fields in the DCTARn registers select the frequency of DSPISCK by the formula below: DSPISCK baud rate fsys = PBR × BR Table 27-15 shows an example of how to compute the baud rate. Table 27-15. Baud Rate Computation Example 27.7.3.
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1 t DT = -------- × PDT × DT f sys Eqn. 27-7 Table 27-18 shows an example of how to compute the delay after transfer. Table 27-18. Delay after Transfer Computation Example 27.7.3.5 PDT Prescaler DT Scaler Fsys Delay after Transfer 0b01 3 0b1110 32768 100 MHz 0.98 ms Peripheral Chip Select Strobe Enable (PCSS) The PCSS signal provides a delay to allow the DSPICSn signals to settle after transitioning, thereby avoiding glitches.
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Functional Description 27.7.4 Transfer Formats The SPI serial communication is controlled by the serial communications clock (DSPISCK) signal and the DSPICSn signals. The DSPISCK signal provided by the master device synchronizes shifting and sampling of the data on the DSPISIN and DSPISOUT pins. The DSPICSn signals serve as enable signals for the slave devices.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DSPISCK (CPOL = 0) DSPISCK (CPOL = 1) Master and Slave Sample Master DSPISOUT/ Slave DSPISIN Master DSPISIN/ Slave DSPISOUT DSPICSn/PCSS tCSC MSB First (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 LSB First (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 tCSC = PCS to DSPISCK delay tASC = After DSPISCK delay tDT = Delay after transfer (minimum CS idle time) tASC Bit 2 Bit 5 Bit 1 Bit 6 tDT t LSB CSC MSB Figure 27-15.
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Functional Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DSPISCK (CPOL = 0) DSPISCK (CPOL = 1) Master and Slave Sample Master DSPISOUT/ Slave DSPISIN Master DSPISIN/ Slave DSPISOUT DSPICSn/PCSS tCSC tASC tDT MSB First (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB First (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tCSC = PCSS to DSPISCK delay tASC = After DSPISCK delay tDT = Delay after transfer (minimum CS negation time) Bit 1 Bit 6 LSB MSB Figure 27-16.
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1 2 3 4 5 6 System Clock DSPISCK Slave Sample Master Sample Slave DSPISOUT Master DSPISOUT PCSS tCSC tASC System Clock System Clock tCSC = PCSS to DSPISCK delay tASC = After DSPISCK delay Figure 27-17. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4) 27.7.4.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) Figure 27-18 shows the modified transfer format for CPHA = 1. Only the condition where CPOL = 0 is described.
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Functional Description be visible on the master DSPISCK pin during the sampling of the last bit. The DSPISCK to CS delay must be greater or equal to half of the DSPISCK period. 1 2 3 4 5 6 System Clock DSPISCK Slave Sample Master Sample Master DSPISOUT Slave DSPISOUT PCSS tCSC tASC tCSC = PCSS to DSPISCK delay tASC = After DSPISCK delay Figure 27-18. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, Fsck = Fsys/4) 27.7.4.
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(tDT) is not inserted between the transfers. Figure 27-20 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1. DSPISCK (CPOL = 0) DSPISCK (CPOL = 1) Master DSPISOUT Master DSPISIN PCSS tCSC tASC tCSC = PCSS to DSPISCK delay tASC = After DSPISCK delay tCSC Figure 27-20. Example of Continuous Transfer (CPHA = 1, CONT = 1) Switching DCTARn registers between frames while using continuous selection can cause errors in the transfer.
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Functional Description DSPISCK (CPOL = 0) DSPISCK (CPOL = 1) Master DSPISOUT Master DSPISIN PCSS tDT tDT = 1 DSPISCK Figure 27-21. Continuous DSPISCK Timing Diagram (CSCK = 0) If DTFR[CONT] is set, DSPICSn remains asserted between the transfers when the DSPICSn signal for the next transfer is the same as for the current transfer. Figure 27-22 shows timing diagram for continuous DSPISCK format with continuous selection enabled.
PAGE 850
Each condition has a flag bit in the Section 27.6.4, “DSPI Status Register (DSR)” and a request enable bit in the Section 27.6.5, “DSPI DMA/Interrupt Request Select Register (DIRSR).” The Tx FIFO fill flag (TFFF) and Rx FIFO drain flag (RFDF) generate interrupt requests or DMA requests depending on the DIRSR[TFFFS] and DIRSR[RFDFS] bits. 27.7.6.1 End of Queue Interrupt Request The end of queue request indicates that the end of a transmit queue is reached.
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Initialization and Application Information 27.8 27.8.1 Initialization and Application Information How to Change Queues This section presents an example of how to change queues for the DSPI. The queues are not part of the DSPI, but the DSPI includes features in support of queue management. 1. The last command word from a queue is executed. The EOQ bit in the command word is set to indicate to the DSPI that this is the last entry in the queue. 2.
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Table 27-22. Baud Rate Values Baud Rate Scaler Values Baud Rate Divider Prescaler Values 27.8.3 2 3 5 7 2 25.0MHz 16.7MHz 10.0MHz 7.14MHz 4 12.5MHz 8.33MHz 5.00MHz 3.57MHz 6 8.33MHz 5.56MHz 3.33MHz 2.38MHz 8 6.25MHz 4.17MHz 2.50MHz 1.79MHz 16 3.12MHz 2.08MHz 1.25MHz 893KHz 32 1.56MHz 1.04MHz 625KHz 446KHz 64 781KHz 521KHz 312KHz 223KHz 128 391KHz 260KHz 156KHz 112KHz 256 195KHz 130KHz 78.1KHz 55.8KHz 512 97.7KHz 65.1KHz 39.1KHz 27.9KHz 1024 48.
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Initialization and Application Information Table 27-23. Delay Values Delay Scaler Values Delay Prescaler Values 27.8.4 1 3 5 7 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 µs 32 320.0 ns 960.0 ns 1.6 µs 2.2 µs 64 640.0 ns 1.9 µs 3.2 µs 4.5 µs 128 1.3 µs 3.8 µs 6.4 µs 9.0 µs 256 2.6 µs 7.7 µs 12.8 µs 17.9 µs 512 5.1 µs 15.4 µs 25.6 µs 35.8 µs 1024 10.
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Tx FIFO Register +1 Tx FIFO Base – – Entry A (First In) Entry B Entry C Entry D (Last In) – – Tx FIFO Counter Transmit Data Pointer Shift Register DSPISOUT –1 Figure 27-23. Tx FIFO Pointers and Counter 27.8.4.
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Chapter 28 I2C Interface 28.1 Introduction This chapter describes the I2C™ module, including I2C protocol, clock synchronization, and I2C programming model registers. It also provides extensive programming examples. 28.1.1 Block Diagram A block diagram of the I2C module is shown in Figure 28-1.
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I2C Overview 28.1.2 I2C is a two-wire, bidirectional serial bus which provides a simple, efficient method of data exchange between devices. This two-wire bus minimizes the interconnection between the devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
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Memory Map/Register Definition 28.3 Memory Map/Register Definition I2C Register Map 28.3.1 Table 28-2. I2C Memory Map . MBAR Offset 0x8F00 Name Byte0 I2C Address Register 2 Byte1 Byte2 Byte3 Access I2ADR — R/W 0x8F04 I C Frequency Divider Register I2FDR — R/W 0x8F08 I2C Control Register I2CR — R/W 2 0x8F0C I C Status Register I2SR — R/W 0x8F10 I2C Data I/O Register I2DR — R/W — R/W 0x8F14 – 0x8F1C 0x8F20 28.3.
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28.3.2.2 I2C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 28-3, provides a programmable prescaler to configure the I2C clock for bit-rate selection. R 7 6 0 0 0 0 5 4 3 2 1 0 0 0 0 IC W Reset 0 Reg Addr 0 0 MBAR + 0x8F04 Figure 28-3. I2C Frequency Divider Register (I2FDR) Table 28-4. I2FDR Field Descriptions Bits Name Description 7–6 — Reserved, should be cleared. 5–0 IC I2C clock rate. Prescales the clock for bit-rate selection.
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Memory Map/Register Definition 28.3.2.3 I2C Control Register (I2CR) The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master. R 7 6 5 4 3 2 1 0 IEN IIEN MSTA MTX TXAK RSTA 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x8F08 Figure 28-4. I2C Control Register (I2CR) Table 28-5. I2CR Field Descriptions Bits Name Description 7 IEN I2C enable. Controls the software reset of the entire I2C module.
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R 7 6 5 4 3 2 1 0 ICF IAAS IBB IAL 0 SRW IIF RXAK 1 0 0 0 0 0 0 1 W Reset Reg Addr MBAR + 0x8F0C Figure 28-5. I2C Status Register (I2SR) Table 28-6. I2SR Field Descriptions Bits Name Description 7 ICF 6 IAAS 5 IBB I2C bus busy bit. Indicates the status of the bus. 0 Bus is idle. If a STOP signal is detected, IBB is cleared. 1 Bus is busy. When START is detected, IBB is set. 4 IAL Arbitration lost. Set by hardware in the following circumstances.
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Memory Map/Register Definition 28.3.2.5 I2C Data I/O Register (I2DR) While in master-receive mode, reading the I2DR allows a read to occur and initiates the next data byte to be received. In slave mode, the same function is available once the I2C has received its slave address. 7 6 5 4 R 3 2 1 0 0 0 0 0 DATA W Reset Reg Addr 0 0 0 0 MBAR + 0x8F10 Figure 28-6. I2C Data I/O Register (I2DR) Table 28-7. I2DR Field Description Bit Name Description 7–0 DATA I2C data.
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R 7 6 5 4 3 2 1 0 0 0 0 0 BNBE TE RE IE 0 0 0 1 0 0 0 1 W Reset Reg Addr MBAR + 0x8F20 Figure 28-7. Interrupt Control Register Table 28-8. I2ICR Field Descriptions Bits Name 7–4 — 3 BNBE 5-6 — Reserved, should be cleared. 2 TE Routes the interrupt for the I2C module to the TX requestor at the multichannel DMA. Reset condition disables this bit.
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Functional Description Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. The parts of a communication are described briefly in the following sections and illustrated in Figure 28-8. 28.4.1 START Signal When the bus is free—that is, when no master device is engaging the bus (both SCL and SDA lines are at logical high)—a master may initiate communication by sending a START signal.
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Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 28-8 shows. SCL is pulsed once for each data bit, with the msb being sent first. The receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. (See Figure 28-9).
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Functional Description 28.4.6 Repeated Start A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode without releasing the bus. Various combinations of read/write formats are then possible: • The first example in Figure 28-11 is the case of a master-transmitter transmitting to a slave-receiver. The transfer direction is not changed.
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Devices with shorter low periods enter a high wait state during this time (see Figure 28-13). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again.
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Initialization Sequence 2. Update the I2ADR to define it as a slave device (give it a slave address) 3. Set I2CR[IEN] to enable the I2C interface system 4. Modify the I2CR to select master/slave mode, transmit/receive mode, or interrupt enable NOTE If I2SR[IBB] is set when the I C bus module is enabled, execute the following code sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in an idle state as if it were just power-cycled on.
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/* Wait for I2SR.IBB (bus busy) to be set */ while ( !(MCF5_I2C_I2SR & MCF_I2C_I2SR_BB) ); 28.5.2 Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (ICF) to 1, which indicates one byte of communication is finished. The interrupt bit (IIF) is set also; an interrupt will be generated if the interrupt function was enabled during initialization (by setting the IEN bit). Software must clear the IIF bit in the interrupt service routine first.
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Initialization Sequence 28.5.3 Generation of STOP A data transfer ends with a STOP signal generated by the ‘master’ device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data.
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/* Generate STOP by clearing I2CR.MSTA */ MCF_I2C_I2CR = 0x80; } /*Store received data and release SDA */ rx_buffer[i] = MCF_I2C_I2DR; } 28.5.4 Generation of Repeated START At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. This is done by writing a 1 to I2CR[MSTA]. 28.5.
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Initialization Sequence /* Set I2CR.MTX to put the module in transit mode */ MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX; /* Send the contents of tx_buffer until NACK is detected */ i = 0; while (1) { /*Put TX data into I2DR */ MCF_I2C_I2DR = tx_buffer[i]; /*Wait for transfer to complete */ while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF) ); /* Clear IIF bit */ MCF_I2C_I2SR &= 0xFD; /*Detect when no ACK is received */ if(MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) { /*Finish the transfer by putting the module into its idle state.
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/* Receive data from master device and store in rx-buffer */ for(i=0; i
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Initialization Sequence Clear IIF Master Mode ? Yes Tx Rx Tx/Rx ? Yes No Yes Last Byte to be Read ? No RXAK=0 ? Arbitration Lost ? Clear IAL Yes Last Byte Transmitted ? No Yes End of Addr Cycle (Master Rx) ? No IAAS=1 ? No Yes Yes No Yes Yes IAAS=1 ? Address Cycle Second Last Byte to be Read ? No Data Cycle No Yes (Read) SRW=1 ? Tx/Rx ? Rx No No (Write) Write Next Byte to I2DR Set TXAK=1 Generate STOP Signal Tx Yes Set Tx Mode ACK from Receiver ? No Write Data to I
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MCF548x Reference Manual, Rev.
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Chapter 29 USB 2.0 Device Controller 29.1 Introduction This chapter provides an overview of the USB 2.0 device controller module of the xMCF548x. Connection examples and circuit board layout considerations are also provided. The USB Specification, Revision 2.0 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this specification, Terms and Abbreviations, provides definitions of many of the terms found here. 29.1.
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29.1.3 Block Diagram A block diagram of the complete USB 2.0 Device controller module is shown in Figure 29-1. FIFO RAM Comm Bus FIFO RAM Manager Arbiter FIFO Control Descriptor RAM Interrupt USB Controller and Synchronization Logic USB 2.0 Device Controller Integrated USB 2.0 PHY Figure 29-1. USB 2.0 Device Controller Block Diagram 29.1.3.
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Introduction 29.1.3.3 FIFO Controller The FIFO controller implements the data FIFOs in such a way that they can communicate with the ColdFire core or with the multichannel DMA. There are two physical RAMs that are shared by all of the FIFO controllers. For maximum performance, the two RAMs can be configured such that one stores transmit (IN) endpoint data and the other stores receive (OUT) endpoint data.
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29.1.3.5.4 USBCLKIN Input pin for the 12-MHz USB crystal circuit. 29.1.3.5.5 USBCLKOUT Output pin for the 12-MHz USB crystal circuit. 29.2 Memory Map/Register Definition This section contains a detailed description of each register and its specific function. 29.2.1 USB Memory Map Table 29-1 contains a memory map for all the USB 2.0 Device Controller registers. NOTE Registers should only be accessed using their full size.
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Memory Map/Register Definition Table 29-1.
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Table 29-1.
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Memory Map/Register Definition Table 29-1.
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Table 29-1.
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Memory Map/Register Definition Table 29-1. USB Memory Map (Continued) Address (MBAR +) Name 0xB4D0– 0xB4FF EP3 FIFO registers 0xB500– 0xB52F EP4 FIFO registers 0xB530– 0xB55F EP5 FIFO registers 0xB560– 0xB58F EP6 FIFO registers 29.2.2 Byte0 Byte1 Byte2 Byte3 USB Request, Control, and Status Registers The following registers provide an application interface to the request, control, and status functionality of the USB 2.0 device controller. 29.2.2.
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Table 29-2. USBSR Field Descriptions Bits Name 6–4 — 3–0 29.2.2.2 Description Reserved, should be cleared. ISOERREP Isochronous error endpoint. This is the endpoint number for the isochronous OUT endpoint that has experienced a PID sequencing error and caused the ISO_ERR interrupt to assert. The value in this register will always reflect the endpoint number for the last isochronous OUT endpoint to experience a PID sequencing error (or 0x0 if no PID sequencing errors have occurred).
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Memory Map/Register Definition Table 29-3. USBCR Field Descriptions Bits Name 31–6 — 5 Description Reserved, should be cleared. RAMSPLIT RAM split. The endpoint FIFO RAM can be configured for maximum flexibility or for maximum performance. The individual FIFO base and depth values (in the EPnFRCFGR) should be carefully programmed taking into account the respective direction (IN/OUT) of each FIFO and the value of this control register.
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Table 29-3. USBCR Field Descriptions (Continued) Bits 1 Name Description APPLOCK Application Lock. This bit should be asserted to ensure the indivisibility of read-modify-write (RMW) operations on certain USB 2.0 device registers. Many register bits can be written to by the user software and the internal logic.
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Memory Map/Register Definition Table 29-4. DRAMCR Field Descriptions Bits Name Description 31 START Start. This bit initiates the GET_DESCRIPTOR handler. Before setting this bit, the software must set the DSIZE[10:0] and DADR[9:0] values to the appropriate values for the current GET_DESCRIPTOR request. This bit automatically resets to 0 after a write. Writing a 0 to this bit has no effect. 30 BSY 29–27 — 26–16 DSIZE 15–10 — 9–0 DADR Busy.
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Table 29-5. DRAMDR Field Descriptions Bits Name 31—8 — 7–0 DDAT 29.2.2.5 Description Reserved, should be cleared. Descriptor data. For descriptor access, software programs address into the DADR[9:0] bits in the DRAMCR register and follow with a read or write to the DRAMDR register to complete the access. Upon the read/write access, the address in DADR[9:0] will increment automatically. User access to this register is only allowed when the USBCR[EN] bit is cleared.
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Memory Map/Register Definition Table 29-6. USBISR Field Descriptions (Continued) Bits Name Description 5 RSTSTOP Reset stop. This indicates the end of reset signalling on the USB. 0 Reset signalling has not stopped. Does not imply that reset signalling is occurring, just that no end-of-reset event has occurred. 1 Reset signalling has stopped. 4 UPDSOF 3 RES Resume. This is used to indicate a state change from suspend to resume in the USB module.
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Table 29-7. USBIMR Field Descriptions Bits Name 31—8 — 7 MSOF 6 SOF Description Reserved, should be cleared. Missed start of frame interrupt. 0 Missed start of frame interrupts enabled. 1 Missed start of frame interrupts disabled. Start of frame interrupt. 0 Start of frame interrupts enabled. 1 Start of frame interrupts disabled. 5 RSTSTOP Reset stop. This indicates the end of reset signalling on the USB. 0 Reset signalling stopped interrupts enabled.
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Memory Map/Register Definition R 7 6 5 4 3 2 1 0 EPSTALL CTROVFL ACK TRANSERR EPHALT OUT IN SETUP 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xB000 Figure 29-8. USB Application Interrupt Status Register (USBAISR) Table 29-8. USBAISR Field Descriptions Bits Name Description 7 EPSTALL Endpoint stall. This bit is set when the PSTALL bit in either EPnOUTSR or EPnINSR is set and is relevant only for control endpoints.
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7 6 R EPSTALLEN CTROVFLEN 5 ACKEN 4 3 TRANSEREN EPHALTEN 2 1 0 OUTEN INEN SETUPEN 1 1 1 W Reset 1 1 Reg Addr 1 1 1 MBAR + 0xB001 Figure 29-9. USB Application Interrupt Mask Register (USBAIMR) Table 29-9. USBAIMR Field Descriptions Bits Name 7 EPSTALLEN Endpoint stall interrupt enable. 0 Endpoint stall interrupt enabled. 1 Endpoint stall interrupt disabled. 6 CTROVFLEN Counter overflow interrupt enable. 0 Counter overflow interrupt enabled.
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Memory Map/Register Definition R 7 6 5 4 0 0 0 0 0 0 0 0 3 2 1 EPNUM 0 EPDIR W Reset Reg Addr 0 0 0 0 MBAR + 0xB003 Figure 29-10. Endpoint Info Register (EPINFO) Table 29-10. EPINFO Field Descriptions Bits Name Description 7–4 — 3–1 EPNUM Endpoint number. Indicates the currently active endpoint. 0 EPDIR Endpoint direction. Indicates the direction of the current endpoint. 0 OUT 1 IN Reserved, should be cleared. 29.2.2.
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R 7 6 5 4 3 2 1 0 1 RMTWKEUP 1 0 0 0 0 0 1 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0xB005 Figure 29-12. USB Configuration Attribute Register (CFGAR) Table 29-12. CFGAR Field Descriptions Bits Name Description 7 — 6 RMTWKEUP 5 — Reserved. Write a 1. 4–0 — Reserved, should be cleared. Reserved. Write a 1. Remote wakeup. The Remote Wakeup bit is updated by the USB 2.
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Memory Map/Register Definition 29.2.2.13 USB Frame Number Register (FRMNUMR) 15 14 13 12 0 0 0 0 0 0 0 0 R 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FRMNUM W Reset 0 0 0 Reg Addr 0 0 0 0 MBAR + 0xB00E Figure 29-14. USB Frame Number Register (FRMNUMR) Table 29-14. FRMNUMR Field Descriptions Bits Name 16–12 — 11–0 FRMNUM Description Reserved, should be cleared. This register contains the frame number of an SOF packet and is updated each time an SOF packet is received.
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Table 29-15. EPTNR Field Descriptions Bits Name 15–12 — 11–0 EPnT Description Reserved, should be cleared. Endpoint transactions. Indicates the number of transactions required by high-speed isochronous endpoints. 00 1 transaction 01 2 transactions 10 3 transactions 11 Reserved 29.2.2.15 USB Application Interface Update Register (IFUR) The IFUR is used by the USB application to perform a high-speed update of the alternate setting of a specified interface. It cannot be addressed as 8 bits.
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Memory Map/Register Definition 15 14 13 12 R 11 10 9 8 7 6 5 4 IFNUM 3 2 1 0 0 0 0 ALTSET W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg MBAR + 0xB040 (IFR0); 0xB042 (IFR1); 0xB044 (IFR2), 0xB046 (IFR4); 0xB048 (IFR5); 0xB04A (IFR6); Addr 0xB04C (IFR7); 0xB04E (IFR8); 0xB050 (IFR9); 0xB052 (IFR10); 0xB054 (IFR11); 0xB056 (IFR12); 0xB058 (IFR13); 0xB05A (IFR14); 0xB05C (IFR15); 0xB05E (IFR16); 0xB060 (IFR17); 0xB062 (IFR18); 0xB064 (IFR19); 0xB066 (IFR20); 0xB068 (IFR21); 0xB06A (
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29.2.3.2 USB Dropped Packet Counter Register (DPCNT) 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DPCNT W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0xB082 Figure 29-19. USB Dropped Packet Counter Register (DPCNT) Table 29-19. DPCNT Field Descriptions Bits Name 15–0 DPCNT 29.2.3.3 Description Packet dropped counter. This register counts the number of packets that have been dropped by the USB due to errors.
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Memory Map/Register Definition Table 29-21. BSECNT Field Descriptions Bits Name 15–0 BSECNT 29.2.3.5 Description Bitstuffing error counter. This register counts the occurrences of bitstuffing errors in the incoming packets. USB PID Error Counter Register (PIDECNT) 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PIDECNT W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0xB088 Figure 29-22. USB PID Error Counter Register (PIDECNT) Table 29-22.
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29.2.3.7 USB Transmitted Packet Counter Register (TXPCNT) 15 14 13 12 11 10 9 8 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXPCNT W Reset 0 0 0 0 0 0 Reg Addr 0 0 0 MBAR + 0xB08C Figure 29-24. USB Transmitted Packet Counter Register (TXPCNT) Table 29-24. TXPCNT Field Descriptions Bits Name Description 15–0 TXPCNT Transmitted packet counter. This register counts the number of packets transmitted by the USB. 29.2.3.
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Memory Map/Register Definition Table 29-25. CNTOVR Field Descriptions (Continued) Bits Name 3 BSECNT 2 Description Bitstuffing error counter overflow flag. 0 The bitstuffing error counter has not overflowed. 1 The bitstuffing error counter has overflowed. CRCECNT CRC error counter overflow flag. 0 The CRC error counter has not overflowed. 1 The CRC error counter has overflowed. 1 DPCNT Dropped packet counter overflow flag. 0 The dropped packet counter has not overflowed.
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R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 TTYPE 0 0 0 0 0 0 Uninitialized W Reset Reg Addr MBAR + 0xB149 (EP1NACR); 0xB179 (EP2NACR); 0xB1A9 (EP3INACR); 0xB1D9 (EP4INACR); 0xB209 (EP5INACR); 0xB239 (EP6INACR) Figure 29-27. Endpoint n Attribute Control Register IN (EPnINACR) Table 29-26. EPnOUTACR and EPnINACR Field Descriptions Bits Name 7–2 — 1–0 TTYPE 29.2.4.2 Description Reserved, should be cleared. Transfer type.
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Memory Map/Register Definition 15 14 13 0 0 0 0 0 0 R 12 11 10 9 8 7 6 ADDTRANS 5 4 3 2 1 0 0 0 0 0 0 MAXPKTSZ W Reset Reg Addr 0 0 0 0 0 0 0 0 MBAR + 0xB14A (EP1NPSR); 0xB17A (EP2NPSR); 0xB1AA (EP3INPSR); 0xB1DA (EP4INPSR); 0xB20A (EP5INPSR); 0xB23A (EP6INPSR) Figure 29-29. Endpoint n Max Packet Size Register IN (EPnINMPSR) Table 29-27. EPnOUTMPSR and EPnINMPSR Field Descriptions Bits Name 15–13 — Description Reserved, should be cleared.
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7 6 5 4 R 3 2 1 0 0 0 0 0 IFNUM W Reset 0 Reg Addr 0 0 0 MBAR + 0xB14C(EP1NIFNUM); 0xB17C(EP2NIFNUM); 0xB1AC(EP3INIFR); 0xB1DC(EP4INIFR); 0xB20C(EP5INIFR); 0xB23C(EP6INIFR) Figure 29-31. Endpoint n Interface Number Register IN (EPnINIFR) Table 29-28. EPnOUTIFR and EPnINIFR Field Descriptions Bits Name Description 7–0 IFNUM Interface number. This register contains the interface number associated with the specified endpoint. The interface number may range from 0x00 through 0xFF. 29.
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Memory Map/Register Definition Table 29-29. EPnOUTSR and EPnINSR Field Descriptions Bits Name Description 5 TXZERO Transmit a zero byte packet. This bit should only be set by the application and cleared by the USB module. 0 NOP (default). 1 Transmit a zero-byte packet 4 — 3 CCOMP Control command complete. Relevant only for control endpoints. This bit should only be set by the application and cleared by the USB module. 0 Control command in process (default). 1 Control command completed.
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Table 29-30. BMRTR Field Descriptions Bits Name 7 DIR 6–5 TYPE TYPE 00 Standard 01 Class 10 Vendor 11 Reserved 4–0 REC Recipient. 0x0 Device 0x1 Interface 0x2 Endpoint 0x3 Other 0x4–0x1F Reserved 29.2.4.6 Description Direction. Data transfer direction. 0 Host to device. 1 Device to host. bRequest Type Register (BRTR) The BRTR records the bRequest field of a SETUP transaction on Endpoint 0. 7 6 5 4 R 3 2 1 0 0 0 0 0 BREQ W Reset 0 0 0 0 Reg Addr MBAR + 0xB107 Figure 29-35.
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Memory Map/Register Definition Table 29-32. WVALUER Field Descriptions Bits Name Description 15–0 WVALUE wValue of setup transaction. This register records the wValue field of a SETUP transaction for the specified endpoint. 29.2.4.8 wIndex Register (WINDEXR) The WINDEXR records the wIndex field of a SETUP transaction on Endpoint 0. 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WINDEX W Reset 0 0 0 0 0 0 0 Reg Addr 0 0 MBAR + 0xB10A Figure 29-37.
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When the host directs a SYNCH_FRAME control read query at this register’s endpoint, the contents of this register are returned to the host. FRMNUM may range from 0x000 through 0x7FF. 15 14 13 12 11 0 0 0 0 0 0 0 0 0 0 R 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FRMNUM W Reset Reg Addr 0 0 0 0 0 0 MBAR + 0xB13E (EP1OUTSFR); 0xB16E (EP2OUTSFR); 0xB19E (EP3OUTSFR); 0xB1CE (EP4OUTSFR); 0xB1FE (EP5OUTSFR); 0xB22E (EP6OUTSFR) Figure 29-39.
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Memory Map/Register Definition R 31 30 29 28 0 0 0 0 27 26 25 24 23 22 21 20 19 18 17 16 BYTECNT W Reset R Uninitialized 0 0 0 0 0 0 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 DIR 0 0 0 0 0 W FLUSH RST Reset Reg Addr Uninitialized 0 Uninitialized 0 0 MBAR + 0xB440 (EP0STAT); 0xB470 (EP1STAT); 0xB4A0 (EP2STAT); 0xB4D0 (EP3STAT); 0xB500 (EP4STAT); 0xB530 (EP5STAT); 0xB560 (EP6STAT) Figure 29-41.
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If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the write. R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 EOT 0 EOF Unin. 0 Unin.
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Memory Map/Register Definition Table 29-37. EPnISR Field Descriptions Bits Name 3 — 2 EOT Description Reserved, should be cleared. End of transfer. This is the end of transfer indicator. This indicates that the last packet of a USB OUT data transfer has crossed out of the USB. The last packet is identified by its length. Any packet shorter than the maximum packet size for the associated OUT endpoint is considered to be an end of transfer marker.
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Table 29-38. EPnIMR Field Descriptions Bits Name 31–9 — Reserved, should be cleared. 8 FU FIFO full. This bit enables FIFO Full interrupts. 0 FIFO FULL interrupts enabled. 1 FIFO FULL interrupts disabled. 7 EMT FIFO empty. This bit enables FIFO Empty interrupts. 0 FIFO EMPTY interrupts enabled. 1 FIFO EMPTY interrupts disabled. 6 ERR FIFO error. This bit enables FIFO error interrupts. 0 FIFO ERROR interrupts enabled. 1 FIFO ERROR interrupts disabled. 5 FIFOHI FIFO high.
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Memory Map/Register Definition 31 30 29 28 0 0 0 0 R 27 26 25 24 23 22 21 20 19 18 17 16 4 3 2 1 0 BASE W Reset Uninitialized 15 14 13 0 0 0 R 12 11 10 9 8 7 6 5 DEPTH W Reset Uninitialized Reg MBAR + 0xB44C (EP0FRCFGR); 0xB47C (EP1FRCFGR); 0xB4AC (EP2FRCFGR); 0xB4DC (EP3FRCFGR); Addr 0xB50C (EP4FRCFGR); 0xB53C (EP5FRCFGR); 0xB56C (EP6FRCFGR) Figure 29-44. USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR) Table 29-39.
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Table 29-40. EPnFDR Field Descriptions Bits Name 31–0 TXDATA This is the transmit FIFO write data 31–0 RXDATA This is the receive FIFO read data 29.2.5.
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Memory Map/Register Definition Table 29-41. EPnFSR Field Descriptions Bits Name Description 23 FAE Frame accept error. This bit indicates a frame accept error in the FIFO controller and will assert in two scenarios. 1) The user has over-written data in a transmit FIFO for a packet (frame) that needs to be retried. 2) The user has read data from a receive FIFO for a packet (frame) that has subsequently been rejected.
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29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR) 31 30 R SHAD 0 29 28 27 26 WFR TMR FRM 25 24 GR 22 21 20 19 18 IP FAE RXW UF OF TXW MSK MSK MSK MSK MSK MSK W Reset 23 17 16 0 0 0 Unin.
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Memory Map/Register Definition Table 29-42. EPnFCR Field Descriptions (Continued) Bits Name Description 26-24 GR Granularity. The functionality of this field depends on the direction of the FIFO. The direction, type, and packet size are defined in the EPnSTAT registers. For Transmitter (IN): These bits control the high “watermark” point at which the FIFO will negate its alarm condition (i.e. request for data). It represents the number of Free Bytes multiplied by 4.
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29.2.5.8 R USB Endpoint n FIFO Alarm Register (EPnFAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 W Reset R Uninitialized 15 14 13 12 0 0 0 0 11 10 9 8 7 ALRMP W Reset Reg Addr Uninitialized 0 0 0 0 0 0 0 MBAR + 0xB45C (EP0FAR); 0xB48C (EP1FAR); 0xB4BC (EP2FAR); 0xB4EC (EP3FAR); 0xB51C (EP4FAR); 0xB54C (EP5FAR); 0xB57C (EP6FAR) Figure 29-48.
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Memory Map/Register Definition 29.2.5.9 USB Endpoint n FIFO Read Pointer (EPnFRP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 R W Reset Uninitialized 15 14 13 12 0 0 0 0 R 11 10 9 8 7 RP W Reset Uninitialized Reg Addr 0 0 0 0 0 0 MBAR + 0xB460 (EP0FRP); 0xB490 (EP1FRP); 0xB4C0 (EP2FRP); 0xB4F0 (EP3FRP); 0xB520 (EP4FRP); 0xB550 (EP5FRP); 0xB580 (EP6FRP) Figure 29-49.
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Table 29-45. EPnFWP Field Descriptions Bits Name 31–12 — 11–0 WP Description Reserved, should be cleared. Write pointer. This value is maintained by the FIFO hardware and is not normally written. Writing to these bits will disrupt the integrity of the data flow. This value represents the Write address being presented to the FIFO RAM. 29.2.5.
PAGE 921
Functional Description 29.2.5.12 USB Endpoint n Last Write Frame Pointer (EPnLWFP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 R W Reset Uninitialized 15 14 13 12 0 0 0 0 R 11 10 9 8 7 LWFP W Reset Uninitialized Reg Addr 0 0 0 0 0 0 0 MBAR + 0xB46C (EP0LWFP); 0xB49C (EP1LWFP); 0xB4CC (EP2LWFP); 0xB4FC (EP3LWFP); 0xB52C( EP4LWFP); 0xB55C (EP5LWFP); 0xB58C (EP6LWFP) Figure 29-52.
PAGE 922
At power-up time, the USB module contains no configuration information. The USB module does not know how many endpoints it has available or how to find the descriptors. Initialization for the device consists of downloading this information to the appropriate memories and configuring the datapath to match the intended application. The following steps are involved in the initialization process: 1. Perform a hard reset or a USB reset (set USBCR[USBRST]). 2.
PAGE 923
Software Interface Download of the descriptor data consists of the following steps: 1. Verify that the USBCR[RAMEN] bit is clear. This ensures that the datapath to the descriptor RAM is open to the application. 2. Write the starting address of the descriptors into the DADR field of the DRAMCR. The address written to this register is the address of the descriptors within the descriptor RAM. 3. Write each byte of the descriptor table to the DDAT field of the DRAMDR.
PAGE 924
29.4.1.4 FIFO Sizes FIFO sizes must be programmed to match the traffic sent across the USB. The EPnFRCFGR along with the USBCR[RAMSPLIT] bit allow software to specify the memory configuration that is to be used at any given time. In most cases, all endpoints should be disabled and all FIFOs should be flushed following the reconfiguration of the FIFO sizes. 29.4.1.5 Enable the Device One of the last steps in initializing the module is to enable it for processing via the RAMEN bit in the USBCR. 29.4.
PAGE 925
Software Interface 29.4.3.1 USB Packets Data moves across the USB in units called packets. Packets range in size from 0 to 1024 bytes, and depending on the transfer mode, the packet size is restricted to a small set of values. Control packet sizes are limited to 8, 16, 32, or 64 bytes. Bulk packet sizes are limited to 8, 16, 32, 64, or 512 bytes. Isochronous and interrupt data packets can take any size from 0 to 1024 bytes.
PAGE 926
2. On receiving EOF interrupt, prepare to read a complete packet of data. Clear the EOF interrupt so that software will receive notification of the next frame. 3. Read the EPnFDR to read in the next piece of data. 4. Read the EPnFSR to get the end of frame status bits. If the end of frame bit is set for the current transfer, then stop reading data. 5. Go back to step 3. 29.4.3.3.1 Programming the FIFO Controller The FIFO controller module has two modes of operation: frame and non-frame.
PAGE 927
Software Interface further requests from the host. This guarantees that data from two different transfers will never get intermixed within the FIFO. NOTE The DMA extensions do not define a zero length frame. Thus, it is necessary to have the CPU monitor the EOT interrupts and use them as a basis for delineating individual transfers. USB traffic flow is halted until the EOT interrupt has been serviced to ensure that data from different data transfers does not get mixed-up in the FIFOs. 29.4.3.
PAGE 928
4. Handle the request appropriately. If a data transfer is implied by the command, set up and perform the data transfer. Be careful not to send back more bytes to the USB host than were requested in the wLength field of the SETUP packet. The USB device controller hardware does not check for incorrect data phase length. The EOT interrupt will assert on completion of the data phase. 5. Set CCOMP in either the EPnOUTSR or EPnINSR and TXZERO in EPnOUTSR or EPnINSR to complete the transfer.
PAGE 929
Software Interface 29.4.3.8 Isochronous Operations Isochronous operations are a special case of USB traffic. Instead of guaranteeing delivery with unbounded latency, isochronous traffic flows over the bus at a guaranteed rate with no error checking. 29.4.3.8.1 Isochronous Transfer Summary The USB host guarantees an endpoint at most 3 isochronous packets per microframe (or 24 packets per frame or 24 MBytes per second). Isochronous packets may range from 0 bytes to 1023 bytes.
PAGE 930
MCF548x Reference Manual, Rev.
PAGE 931
Chapter 30 Fast Ethernet Controller (FEC) 30.1 Introduction This Fast Ethernet Controller (FEC) chapter provides a functional block diagram, a feature-set overview, and transceiver connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. 30.1.
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Comm Bus Slave Interface MII EnMDIO EnMDEN Interrupt IP Bus FEC FIFO Controller CSR Transmit FIFO Receive FIFO MIB Counters Transmit Receive EnMDIO EnTXEN EnTXD[3:0] EnTXER I/O Pad EnMDIO EnMDC EnTXCLK EnCRS EnCOL EnRXCLK EnRXDV EnRXD[3:0] EnRXER MII/7-Wire Data Option Figure 30-1. FEC Block Diagram 30.1.3 Overview The Fast Ethernet Controller is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
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Introduction 30.1.4 Features The FEC incorporates the following features: • Support for three different Ethernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 10-Mbps 7-wire interface • IEEE 802.3 full duplex flow control • Programmable max frame length supports IEEE 802.
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transceiver via this interface in the following sections: Section 30.4.3, “Network Interface Options,” Section 30.4.13, “MII Data Frame,” and Section 30.4.14, “MII Management Frame Structure.” 30.1.5.2.2 10 Mpbs 7-Wire Interface Operation The FEC supports a 7-wire interface as used by many 10 Mbps Ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the 10 Mbps, 7-wire mode is enabled. 30.1.5.
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External Signals 30.2.5 Transmit Error (EnTXER) Assertion of this output signal for one or more clock cycles while EnTXEN is asserted shall cause the PHY to transmit one or more illegal symbols. Asserting EnTXER has no affect when operating at 10 Mbps or when EnTXEN is de-asserted This signal transitions synchronously with respect to EnTXCLK. 30.2.6 Receive Data Valid (EnRXDV) When this input signal is asserted, the PHY is indicating that a valid nibble is present on the MII.
PAGE 936
. Table 30-2. MII: Valid Encoding of EnTXD, EnTXEN and EnTXER EnTXEN EnTXER EnTXD[3:0] Indication 0 0 0000 through 1111 Normal inter-frame 0 1 0000 through 1111 Reserved 1 0 0000 through 1111 Normal data transmission 1 1 0000 through 1111 Transmit error propagation A false carrier condition occurs if the PHY detects a bad start-of-stream delimiter. This condition is signaled to the MII by asserting EnRXER and placing 1110 on EnRXD. EnRXDV must also be de-asserted.
PAGE 937
Memory Map/Register Definition 30.3.2 Detailed Memory Map (Control/Status Registers) Table 30-5 shows the FEC register memory map with each register address, name, and a brief description. Table 30-5.
PAGE 938
Table 30-5.
PAGE 939
Memory Map/Register Definition which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well. Table 30-6.
PAGE 940
Table 30-6.
PAGE 941
Memory Map/Register Definition Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR, XFUN, XFERR, and RFERR. Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts because these errors will be visible to network management via the MIB counters.
PAGE 942
Table 30-7. EIR Descriptions (Continued) Bits Name 26–24 — Reserved, should be cleared. 23 MII MII interrupt. This bit indicates that the MII has completed the data transfer requested. This bit is cleared by writing a 1 to it. 22 — Reserved, should be cleared. 21 LC Late collison. This bit indicates that a collision occurred beyond the collision window (slot time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
PAGE 943
Memory Map/Register Definition 31 30 29 28 R HBERR BABR BABT GRA 27 26 25 24 23 22 21 20 TXF 0 0 0 MII 0 LC RL 19 18 17 16 XFUN XFERR RFERR 0 W Reset R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x9008 (FEC0), 0x9808 (FEC1) Figure 30-3. Ethernet Interrupt Mask Register (EIMR) Table 30-8.
PAGE 944
Table 30-9. ECR Field Descriptions Bits Name 31–2 — 1 Description Reserved, should be cleared. ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame.
PAGE 945
Memory Map/Register Definition Table 30-10. MMFR Field Descriptions (Continued) Bit Name Description 27–23 PA PHY address. This field specifies one of up to 32 attached PHY devices. 22–18 RA Register address. This field specifies one of up to 32 registers within the specified PHY device. 17–16 TA Turn around. This field must be programmed to 0x10 to generate a valid MII management frame. 15–0 DATA Management frame data.
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R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DIS_PRE AMBLE 0 0 0 0 0 0 0 0 0 W Reset R W Reset Reg Addr MII_SPEED 0 0 0 0 0 0 0 0 MBAR + 0x9044 (FEC0), 0x9844 (FEC1) Figure 30-6. MII Speed Control Register (MSCR) Table 30-11.
PAGE 947
Memory Map/Register Definition 30.3.3.6 MIB Control Register (MIBC) The MIBC is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user software if there is a need to disable the MIB block operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1.
PAGE 948
31 30 29 28 27 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 26 25 24 23 22 21 20 19 18 17 16 0 1 1 1 0 5 4 3 2 1 0 0 FCE BC_REJ PROM MII_ MODE DRT LOOP 0 0 0 0 0 0 1 MAX_FL W Reset R W Reset Reg Addr MBAR + 0x9084 (FEC0), 0x9884 (FEC1) Figure 30-8. Receive Control Register (RCR) Table 30-14.
PAGE 949
Memory Map/Register Definition 31 30 29 28 27 R FCE MULT CAST 26 25 24 HASH 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R Uninitialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x9088 (FEC0), 0x9888 (FEC1) Figure 30-9. Receive Hash Register (RHR) Table 30-15.
PAGE 950
Table 30-16. TCR Field Descriptions Bits Name 31–5 — Description Reserved, should be cleared. 4 RFC_PAUSE Receive frame control pause. This read-only status bit will be set when a full duplex flow control pause frame has been received and the transmitter is paused for the duration defined in this pause frame. This bit will automatically clear when the pause duration is complete. 3 TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when set.
PAGE 951
Memory Map/Register Definition 31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PADDR1 W Reset Uninitialized 15 14 13 12 11 10 9 R 8 7 PADDR1 W Reset Uninitialized Reg Addr MBAR + 0x90E4 (FEC0), 0x98E4 (FEC1) Figure 30-11. Physical Address Low Register (PALR) Table 30-17.
PAGE 952
Table 30-18. PAHR Field Descriptions BIts Name Description 31–16 PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. 15–0 TYPE Type field in PAUSE frames. These 16-bits are a constant value of 0x8808. 30.3.3.12 Opcode/Pause Duration Register (OPD) The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a PAUSE frame.
PAGE 953
Memory Map/Register Definition 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 IADDR1 W Reset Uninitialized 15 14 13 12 11 10 9 8 R 7 IADDR1 W Reset Uninitialized Reg Addr MBAR + 0x9118 (FEC0), 0x9918 (FEC1) Figure 30-16. Individual Address Upper Register (IAUR) Table 30-20.
PAGE 954
Table 30-21. IALR Field Descriptions Bits Name Description 31–0 IADDR2 Individual Address Lower - The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. 30.3.3.15 Group Address Upper Register (GAUR) The GAUR is written by the user.
PAGE 955
Memory Map/Register Definition 31 30 29 28 27 26 25 24 R 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 GADDR2 W Reset Uninitialized 15 14 13 12 11 10 9 8 R 7 GADDR2 W Reset Uninitialized Reg Addr MBAR + 0x9124 (FEC0), 0x9924 (FEC1) Figure 30-19. Group Address Lower Register (GALR) Table 30-23.
PAGE 956
Table 30-24. FECTFWR Field Descriptions Bits Name Descriptions 31–4 — 3–0 X_WMRK Reserved, should be cleared. Transmit FIFO watermark. Frame transmission will begin when the number of bytes selected by this field have been written into the transmit FIFO or if an end of frame has been written to the FIFO or if the FIFO is full before the selected number of bytes have been written. Number of bytes written = 64 (X_WMRK + 1) 30.3.3.
PAGE 957
Memory Map/Register Definition 31 30 29 28 R IP 0 0 0 W w1c Reset R 27 26 25 24 FRM 23 22 21 20 19 18 FAE RXW UF OF FRM RDY FU w1c w1c w1c w1c 17 16 ALARM EMT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Reg Addr MBAR + 0x9188 (FEC0), 0x9988 (FEC1) Figure 30-22.
PAGE 958
Table 30-26. FECRFSR Field Descriptions (Continued) Bits Name Descriptions 21 UF FIFO underflow. This bit signifies the read pointer has surpassed the write pointer. If not masked, a one in this bit will cause a RFERR in the EIR. This bit will remain set until a 1 is written to this bit location. 0 No FIFO underflow. 1 Signifies an underflow condition in the FIFO. 20 OF FIFO Overflow. This bit signifies the write pointer has surpassed the read pointer.
PAGE 959
Memory Map/Register Definition R 31 30 29 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 0 0 W Reset 28 27 26 TIMER FRM EN 25 24 GR R 23 22 21 20 19 18 17 16 1 0 0 0 1 0 0 4 3 2 1 0 0 0 0 0 0 IP_ FAE_ RXW_ UF_ OF_ MSK MSK MSK MSK MSK COUNTER W Reset 0 0 Reg Addr 0 0 0 0 0 0 0 MBAR + 0x918C (FEC0), 0x998C (FEC1) Figure 30-23. FEC Receive FIFO Control Register (FECRFCR) Table 30-27.
PAGE 960
Table 30-27. FECRFCR Field Descriptions (Continued) Bits Name 18-16 — 15–0 Descriptions Reserved COUNTER Timer mode counter. When the TIMER bit is set, the value of the COUNTER[15:0] bits are used to determine the period of time that the frame ready request is suppressed. A request for service will be made every (COUNTER[15:0] * 64) cycles as long as a valid frame exists in the FIFO. 30.3.3.
PAGE 961
Memory Map/Register Definition in-between the read and write pointers) into framed and unframed data. Data between the LWFP and write pointer constitutes an incomplete frame, while data between the read pointer and the LWFP has been received as whole frames. When FECRFCR[FRMEN] is not set, then this pointer has no meaning. The last written frame pointer is reset to zero, and non-functional bits of this pointer will always remain zero.
PAGE 962
R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R ALARM W Reset Reg Addr 0 0 0 0 0 0 MBAR + 0x9198 (FEC0), 0x9998 (FEC1) Figure 30-26. FEC Receive FIFO Alarm Register (FECRFAR) Table 30-30.
PAGE 963
Memory Map/Register Definition Table 30-31. FECRFRP Field Descriptions Bits Name 31–10 — 9–0 READ Descriptions Reserved, should be cleared. Read pointer. This pointer indicates the next location to be read by the FIFO controller. 30.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFWP) The write pointer is a FIFO maintained pointer which points to the next FIFO location to be written. The write pointer can be both read and written.
PAGE 964
31 30 29 28 27 26 25 R 24 23 22 21 20 19 18 17 16 FIFO_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R FIFO_DATA W Reset 0 0 0 0 0 Reg Addr 0 0 0 0 MBAR + 0x91A4 (FEC0), 0x99A4 (FEC1) Figure 30-29. FEC Transmit FIFO Data Register (FECTFDR) Table 30-33. FECTFDR Field Descriptions Bits 31–0 Name Descriptions FIFO_DATA Transmit FIFO data.
PAGE 965
Memory Map/Register Definition Table 30-34. FECTFSR Field Descriptions Bits Name Descriptions 31 IP Illegal pointer. This bit signifies an illegal pointer condition in the FIFO controller. For example, if a value larger than the FIFO controller’s memory range is written to a Read, Write, Last Read, or Last Write Pointer, the IP bit will assert. If not masked, a one in this bit will cause a XFERR in the EIR. This bit will remain set until a one is written to this bit location.
PAGE 966
30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR) The FIFO transmit control register provides programmability of FIFO behaviors, including last transfer granularity and frame operation. Last transfer granularity allows the user to control when the FIFO controller stops requesting data transfers through the FIFO alarm by modifying the clearing point of the alarm, ensuring the data stream is stopped at a valid point, or there remains enough space in the FIFO to unload the input data pipeline.
PAGE 967
Memory Map/Register Definition Table 30-35. FECTFCR Field Descriptions (Continued) Bits Name Descriptions 26–24 GR Last transfer granularity. A transmit alarm request is cleared when there are less than (4 * GR[2:0]) free bytes remaining in the FIFO. 23 IP_MSK llegal pointer mask. When this bit is set, the FIFO controller masks the status register’s IP bit from generating a XFERR in the EIR. 22 FAE_MSK Frame accept error mask.
PAGE 968
R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R LRFP W Reset Reg Addr 0 0 0 0 0 MBAR + 0x91B0 (FEC0), 0x99B0 (FEC1) Figure 30-32. FEC Transmit FIFO Last Write Frame Pointer Register (FECTLRFP) Table 30-36.
PAGE 969
Memory Map/Register Definition R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R LWFP W Reset Reg Addr 0 0 0 0 0 0 MBAR + 0x91B4 (FEC0), 0x99B4 (FEC1) Figure 30-33. FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP) Table 30-37.
PAGE 970
Table 30-38. FECTFAR Field Descriptions Bits Name 31–10 — 9–0 ALARM Descriptions Reserved, should be cleared. Alarm pointer. This pointer indicates the point at which to set the FIFO alarm bit. This value is compared with the number of data bytes in the FIFO. 30.3.3.32 FEC Transmit FIFO Read Pointer Register (FECTFRP) The read pointer is a FIFO maintained pointer which points to the next FIFO location to be read. The read pointer can be both read and written.
PAGE 971
Memory Map/Register Definition 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset R WRITE W Reset Reg Addr 0 0 0 0 0 0 MBAR + 0x91C0 (FEC0), 0x99C0 (FEC1) Figure 30-36. FEC Transmit FIFO Write Pointer Register (FECTFWP) Table 30-40.
PAGE 972
Table 30-41. FECFRST Field Descriptions Bits Name Descriptions 31–26 — 25 SW_RST Software Reset. This bit controls the soft reset of the FEC FIFOs. A soft reset will reset the FIFO pointers and byte counters but notthe status and control registers. To cause a soft reset this bit should be set and then cleared by application software. 24 RST_CTL Reset control. Setting this bit allows the FEC controller to perform a soft reset of the FIFOs when the FEC is disabled (ECR[ETHER_EN] cleared).
PAGE 973
Functional Description 30.4 Functional Description This section describes the operation of the FEC, beginning with the hardware and software initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving frames. Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC. 30.4.
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Table 30-44. User Initialization (Before Asserting ECR[ETHER_EN]) (Continued) Description Set MSCR (optional) Clear MIB RAM (locations MBAR + 0x9200–0x92E3 and MBAR + 0x9A00–0x9AE3) Reset Comm Bus FIFOs in the FIFO Reset register Set Comm Bus FIFO Alarm and Control Registers 30.4.2 Frame Control/Status Words In the FEC, transmit frame control words and receive frame status words are appended to frame data in the FIFO. These words use the format shown below. 30.4.2.
PAGE 975
Functional Description Table 30-45. RFSW Field Descriptions (Continued) Bits Name Description 20 NO Receive Nonoctet Aligned Frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set the CR bit will not be set. 19 — Reserved, should be cleared. 18 CR Receive CRC Error, written by the FEC.
PAGE 976
30.4.3 Network Interface Options The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode (RCR[MII_MODE] = 1), the following 12 signals are defined by the IEEE 802.3 standard and supported by the FEC. These signals are shown in Table 30-47 below. Table 30-47.
PAGE 977
Functional Description When the transmit FIFO fills to the watermark (defined by FECTFWR) or a complete (small) frame is placed in the FIFO, the FEC transmit logic will assert EnTXEN and start transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy (EnCRS asserts).
PAGE 978
During reception, the Ethernet controller checks for various error conditions and once the entire frame is written into the FIFO, a 32-bit frame status word (RFSW) is written into the FIFO. This receive frame status word contains the M, BC, MC, LG, NO, CR, OF and TR status bits, and the frame length. See Section 30.4.12.2, “Reception Errors” for more details.
PAGE 979
Functional Description Accept/Reject Frame True Broadcast Addr ? False Receive Address Recognition False Hash Match ? BC_REJ = 1 ? Receive Frame Set BC bit in Rcv BD True False True Receive Frame Set MC bit in RFSW if multicast True Exact Match ? False True Pause Frame ? False PROM = 1 ? True False Reject Frame Reject Frame Receive Frame Receive Frame Set M (Miss) bit in Rcv BD Set MC bit in Rcv BD if multicast NOTES: Set BC bit in Rcv BD if broadcast BC_REJ - field in RCR register (Bro
PAGE 980
The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is: x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 8 7 5 4 2 +x +x +x +x +x +x+1 Eqn. 30-1 A table of example destination addresses and corresponding hash values is included below for reference. Table 30-49.
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Functional Description Table 30-49.
PAGE 982
Table 30-49. Destination Address to 6-Bit Hash (Continued) 30.4.8 48-bit Destination Address 6-bit Hash (in Hex) Hash Decimal Value FD:FF:FF:FF:FF:FF 0x3C 60 DD:FF:FF:FF:FF:FF 0x3D 61 9D:FF:FF:FF:FF:FF 0x3E 62 BD:FF:FF:FF:FF:FF 0x3F 63 Full Duplex Flow Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
PAGE 983
Functional Description Table 30-51. Transmit Pause Frame Registers PAUSE Frame Fields FEC Register Register Contents 48-bit destination address Internal 0x0180_C200_0001 48-bit Source Address {PALR[31:0], PAHR[31:16]} Physical Address 16-bit type PAHR[15:0] 0x8808 16-bit opcode OPD[31:16] 0x0001 16-bit PAUSE duration OPD[15:0] 0x0000 to 0xFFFF The user must specify the desired pause duration in the OPD register.
PAGE 984
transmit side and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow. For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback. 30.4.12 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the receive frame status words (RFSWs), the EIR register, and the MIB block counters. 30.4.12.1 Transmission Errors 30.4.12.1.
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Functional Description 30.4.12.2 Reception Errors 30.4.12.2.1 Overrun Error If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the receive frame status word (RFSW). All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available. At this point the RFSW is written into the FIFO with the OV bit set.
PAGE 986
The data portion of the frame consists of N octets which corresponds to 2N nibbles being transmitted. The order of each nibble is defined in the figure below. LSB First Bit First Nibble Second Nibble D0 D1 D2 D3 D0 D1 D2 D3 LSB MII Nibble D4 MSB D5 D6 D7 MSB Figure 30-42. MII Nibble/Octet to Octet/Nibble Mapping The End-of-Frame delimiter is indicated by the de-assertion of the ETXEN signal for data on ETXD.
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Functional Description Table 30-52. MII Management Register Set (Continued) Register Addr. Register Name Basic/Extended 4 Auto-Negotiation (AN) Advertisement E 5 AN Link Partner Ability E 6 AN Expansion E 7 AN Next Page Transmit E 8-15 Reserved E 16-31 Vendor Specific E MCF548x Reference Manual, Rev.
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MCF548x Reference Manual, Rev.
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Part V Mechanical Part V provides mechanical descriptions of the MCF548x. Contents • Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the MCF548x. MCF548x Reference Manual, Rev.
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MCF548x Reference Manual, Rev.
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Chapter 31 Mechanical Data This chapter contains drawings showing the pinout, packaging, and mechanical characteristics of the MCF548x. See the website http://www.freescale.com/coldfire for any updated information. 31.1 Package The MCF548x is assembled in a 388-pin, thermally enhanced plastic BGA package. 31.2 Pinout The MCF548x pinout is detailed in Table 31-1, including the primary and alternate functions of multiplexed signals. Table 31-1.
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Table 31-1.
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Pinout Table 31-1.
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Table 31-1.
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Pinout Table 31-1.
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Table 31-1.
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Pinout Table 31-1.
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31.3 31.3.1 Mechanical Diagrams MCF5485/5484 Mechanical Diagram Figure 31-1–Figure 31-4 show the pinout for the each quadrant of the MCF5485/MCF5484 388 PBGA package. Figure 31-1 shows the pinout for the upper left quadrant.
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Mechanical Diagrams Figure 31-2 shows the pinout for the upper right quadrant of the MCF5485/MCF5484 pinout for the 388 PBGA package.
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Figure 31-3 shows the pinout for the lower left quadrant of the MCF5485/MCF5484 pinout for the 388 PBGA package.
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Mechanical Diagrams Figure 31-4 shows the pinout for the lower left quadrant of the MCF5485/MCF5484 pinout for the 388 PBGA package.
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31.3.2 MCF5483/5482 Mechanical Diagram Figure 31-5–Figure 31-8 show the pinout for the each quadrant of the MCF5483/MCF5482 388 PBGA package. Figure 31-5 shows the pinout for the upper left quadrant.
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Mechanical Diagrams Figure 31-6 shows the pinout for the upper right quadrant of the MCF5483/MCF5482 pinout for the 388 PBGA package.
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Figure 31-7 shows the pinout for the lower left quadrant of the MCF5483/MCF5482 pinout for the 388 PBGA package.
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Mechanical Diagrams Figure 31-8 shows the pinout for the lower left quadrant of the MCF5483/MCF5482 pinout for the 388 PBGA package.
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31.4 MCF5481/5480 Mechanical Diagram Figure 31-9–Figure 31-12 show the pinout for the each quadrant of the MCF5481/MCF5480 388 PBGA package. Figure 31-9 shows the pinout for the upper left quadrant.
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MCF5481/5480 Mechanical Diagram Figure 31-10 shows the pinout for the upper right quadrant of the MCF5481/MCF5480 pinout for the 388 PBGA package.
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Figure 31-11 shows the pinout for the lower left quadrant of the MCF5481/MCF5480 pinout for the 388 PBGA package.
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MCF5481/5480 Mechanical Diagram Figure 31-12 shows the pinout for the lower left quadrant of the MCF5481/MCF5480 pinout for the 388 PBGA package.
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31.5 Mechanicals 388-pin PBGA Package Outline 31.6 Case Drawing Figure 31-13 shows the MCF548x case drawing. Figure 31-13. 388-pin BGA Case Outline MCF548x Reference Manual, Rev.
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Appendix A MCF548x Memory Map Table A-1 lists an overview of the memory map for the on-chip modules. Table A-1.
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Table A-1.
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Table A-1. MCF548x Module Memory Map Overview (continued) Address Name (abbreviation) Description MBAR + 0x1_FF00 – 0x1_FFFF SRAMCFG 32KB System SRAM Configuration registers. MBAR + 0x2_0000 – 0x3_FFFF SEC Integrated Security Engine NOTE Read and write accesses to reserved MBAR spaces will result in undefined behavior that may result in a non-terminated bus cycle. This applies to the reserved locations between modules and the reserved locations within valid module address ranges.
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MCF548x Reference Manual, Rev.
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Index condition code (CCR) 3-9 data (Dn) 3-9 module base address (MBAR) 3-13 RAM base address (RAMBAR) 3-13 status (SR) 3-12 user stack pointer (A7) 3-9 vector base (VBR) 3-12, 3-37 Crypto-channel 22-3, 22-11, 22-18 A Acknowledge error (ACKERR) 21-16 Addressing modes 3-18 Associated functions 15-3 B BDM, see debug Bit error (BITERR) 21-16 Bus off interrupt (BOFFINT) 21-17 Bus, see FlexBus 17-1 Byte lanes 17-2 C Cache cache-inhibited accesses 7-13 initialization 7-30 interaction with SRAM 7-1 line states 7
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configuration/status (CSR) 8-11 data breakpoint/mask (DBR, DBMR) 8-22 extended trigger definition (XTDR) 8-25 PC breakpoint ASID (PBASID) 8-24 PC breakpoint ASID control (PBAC) 8-14 program counter breakpoint/mask (PBRn, PBMR) 8-20 trigger definition (TDR) 8-17 signals 8-2 taken branch 8-6 virtual environment 5-7 DMA initiators 24-23 LURC 24-31 master DMA engine 24-27 memory map 24-3 prioritization 24-24 registers current pointer (CP) 24-7 end pointer (EP) 24-8 external request address mask (EREQMASK) 24-21
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port interrupt enable (EPIER) 14-4 Error counters 21-30 Ethernet address recognition 30-48 collision handling 30-53 errors handling 30-54 reception CRC 30-55 frame length 30-55 non-octet 30-55 overrun 30-55 truncation 30-55 transmission attempts limit expired 30-54 heartbeat 30-54 late collision 30-54 underrun 30-54 frame reception 30-47 frame transmission 30-46 hash table 30-49 initialization 30-43 interpacket gap time 30-53 memory map control and stauts registers 30-7 MIB block counters 30-8 operation 10/
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structure 21-19 time stamp 21-28 transmit codes 21-22 error status flag (TXWARN) 21-16 priority 21-24 operation 21-19–21-31 bit timing configuration 21-29 debug mode 21-3 listen-only mode 21-4 receive process 21-24 registers control (CANCTRL) 21-8 error and status (ESTAT) 21-15 interrupt flag (IFLAG) 21-18 interrupt mask (IMASK) 21-17 module configuration (CANMCR) 21-6 Rx 14 mask (RX14MASK) 21-13 Rx 15 Mask (RX15MASK) 21-13 Rx global mask (RXGMASK) 21-12 transmit process 21-23 FPU data formats 3-17 floating
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repeated start 28-11 signals SCL 28-2 SDA 28-2 START 28-9 STOP 28-9 Instructions architecture additions 3-19 branch acceleration 3-4 debug 8-54, 8-60 EMAC execution timing 4-11 summary 4-11 execution timing 3-27 branch 3-33 EMAC 3-34 FPU 3-35 miscellaneous 3-32 MOVE 3-28 one-operand 3-30 two-operand 3-31 fetch pipeline 3-3 JTAG BYPASS 23-9 CLAMP 23-9 ENABLE_TEST_CTRL 23-9 EXTEST 23-8 HIGHZ 23-9 IDCODE 23-8 SAMPLE/PRELOAD 23-8 MOVEC 8-45 PULSE 8-6 STOP 8-7, 8-29 summary 3-22 WDDATA 8-6 Interrupt controller f
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Mechanical data case drawing 31-20 diagram 31-8 pinout 31-1 Memory maps debug 8-10 DMA 24-3 DSPI 27-4 EMAC 4-5 EPORT 14-2 Ethernet control and status registers 30-7 MIB block counters 30-8 FlexCAN 21-5 I2C 28-3 interrupt controller 13-4 JTAG 23-4 MMU 5-11 PCI controller 19-4 PSC 26-3 SEC 22-8 SIU 9-1 SRAM 16-2 timers CTM 25-3 GPT 11-2 SLT 12-1 USB 29-4 Message buffers frames overload 21-28 remote 21-27 self-received 21-25 handling 21-25 receive codes 21-21 deactivation 21-26 error status flag (RXWARN) 21-17
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initiator window 2 base/translation address (PCIIW2BTAR) 19-19 initiator window configuration (PCIIWCR) 19-19 revision ID/class code (PCICCRIR) 19-9 Rx done counts (PCIRDCR) 19-41 Rx enable (PCIRER) 19-38 Rx FIFO alarm (PCIRFAR) 19-46 Rx FIFO control (PCIRFCR) 19-45 Rx FIFO data (PCIRFDR) 19-43 Rx FIFO status (PCIRFSR) 19-44 Rx FIFO write pointer (PCIRFWPR) 19-47 Rx next address (PCIRNAR) 19-40 Rx packet size (PCIRPSR) 19-36 Rx start address (PCIRSAR) 19-36 Rx status (PCIRSR) 19-42 Rx transaction control (P
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R RAMBAR 3-13 Registers cache access control (ACRn) 3-13, 5-5, 5-6, 7-22 configuration (CACR) 3-13 control (CACR) 5-5, 7-19 core address (An) 3-9 condition code (CCR) 3-9 data (Dn) 3-9 module base address (MBAR) 3-13 RAM base address (RAMBAR) 3-13 status (SR) 3-12 user stack pointer (A7) 3-9 vector base (VBR) 3-12, 3-37 debug address attribute (BAAR) 8-15 address breakpoint (ABLR, ABHR) 8-21 attribute trigger (AATR, AATR1) 8-16 configuration/status (CSR) 8-11 data breakpoint/mask (DBR, DBMR) 8-22 extended t
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PCI grant pin assignment (PAR_PCIBG) 15-25 PCI request pin assignment (PAR_PCIBR) 15-26 port clear output data (PCLRR_x) 15-18–15-20 port x data direction (PDDR_x) 15-11–15-14 port x output data (PODR_x) 15-8–15-11 port x pin assignment (PAR_x) 15-21 port x pin data/set data (PPDSDR_x) 15-14–15-17 PSC0 pin assignment (PAR_PSC0) 15-29 PSC1 pin assignment (PAR_PSC1) 15-28 PSC2 pin assignment (PAR_PSC2) 15-28 PSC3 pin assignment (PAR_PSC3) 15-27 I2C address (I2AR) 28-3 control (I2CR) 28-5 data I/O (I2DR) 28-7
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infrared FIR divide (PSCIRFDRn) 26-26 infrared MIR divide (PSCIRMDRn) 26-25 infrared SIR divide (PSCIRSDRn) 26-25 input port (PSCIP) 26-21 input port (PSCIPn) 26-21 input port change (PSCIPCRn) 26-17 interrupt mask (PSCIMRn) 26-19 interrupt status (PSCISRn) 26-18 mode 1 (PSCMR1) 26-5 mode 1 (PSCMR1n) 26-5 mode 2 (PSCMR2n) 26-6 output port bit reset (PSCOPRESETn) 26-22 output port bit set (PSCOPSETn) 26-22 PSC/IrDA control (PSCSICRn) 26-23 receiver and transmitter buffer (PSCRBn, PSCTBn) 26-14 RxFIFO and TxF
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USB application interface update (IFUR) 29-22 application interrupt mask (USBAIMR) 29-17 application interrupt status (USBIASR) 29-16 bitstuffing error counter (BSECNT) 29-24 bmrequest type (BMRTR) 29-31 brequest type (BRTR) 29-32 configuration attribute (CFGAR) 29-19 configuration interface (IFRn) 29-22 configuration value (CFGR) 29-19 control (USBCR) 29-10 counter overflow (CNTOVR) 29-26 CRC error counter (CRCECNT) 29-24 descriptor RAM control (DRAMCR) 29-12 descriptor RAM data (DRAMDR) 29-13 device speed
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execution units access 22-11 AESU 22-6, 22-83 AFEU 22-5, 22-67 DEU 22-4, 22-72 MDEU 22-6, 22-77 multifunction data packet descriptors 22-90 multiple assignment 22-11 RNG 22-8, 22-82 memory map 22-8 registers AESU interrupt mask (AESIMR) 22-54 AESU interrupt status (AESISR) 22-53 AESU reset control (AESRCR) 22-50 AESU status (AESSR) 22-51 AFEU interrupt mask (AFIMR) 22-32 AFEU interrupt status (AFISR) 22-31 AFEU reset control (AFRCR) 22-28 AFEU status (AFSR) 22-29 crypto-channel configuration (CCCRn) 22-19 c
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transfer burst (TBST) 2-17, 17-4 transfer size (TSIZn) 2-17, 17-4 transfer start (TS) 2-17, 17-4 FlexCAN receive (CANRX0, CANRX1) 2-27 transmit (CANTX0, CANTX1) 2-27 general-purpose timers inputs (TINn) 2-29 outputs (TOUTn) 2-29 GPIO 15-3–15-7 I2C SCL 28-2 SDA 28-2 serial clock (SCL) 2-28 serial data (SDA) 2-28 interrupts IRQn 2-21 JTAG MTMOD0 23-2 test clock input (TCK) 23-3, 23-9 test data input/development serial input (TDI/DSI) 23-3 test data output/development serial output (TDO/DSO) 23-4 test mode sel
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write data byte mask (SDDMn) 2-19 write data byte mask (SDDMn) 18-3 write enable (SDWE) 2-19, 18-3 test mode (MTMODn) 2-30 timers GPT TINn 11-2 USB differential data 29-3 differential data (USBD+, USBD–) 2-26 USBCLKIN 2-26, 29-4 USBCLKOUT 2-26, 29-4 USBRBIAS 2-26, 29-3 USBVBUS 2-26, 29-3 SIU memory map 9-1 registers JTAG device ID (JTAGID) 9-5 module base address (MBAR) 9-2 reset status (RSR) 9-5 SEC sequential access control (SECSACR) 9-4 system breakpoint control (SBCR) 9-3 SLT memory map 12-1 SRAM access
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device speed (SPEEDR) 29-20 dropped packet counter (DPCNT) 29-24 endpoint info (EPINFO) 29-18 endpoint n attribute control 29-27 endpoint n FIFO alarm (EPnFAR) 29-44 endpoint n FIFO control (EPnFCR) 29-42 endpoint n FIFO data (EPnFDR) 29-39 endpoint n FIFO RAM configuration (EPnFRCFGR) 29-38 endpoint n FIFO read pointer (EPnFRP) 29-45 endpoint n FIFO status (EPnFSR) 29-40 endpoint n FIFO write pointer (EPnFWP) 29-45 endpoint n interface number 29-29 endpoint n interrupt mask (EPnIMR) 29-37 endpoint n interr
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MCF548x Reference Manual, Rev.
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Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Controller (PCI) PCI Bus Arbiter (PCIARB) FlexCAN Integrated Secuity Engine (SEC) IEEE 1149.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A IND Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus SDRAM Controller (SDRAMC) PCI Bus Contro