Microcontrollers Data Sheet

I/O Registers
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 171
13.7.2 SCI Control Register 2
SCI control register 2 (SCC2):
• Enables these CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC3 enables SCTE CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
Table 13-4. Character Format Selection
Control Bits Character Format
M PEN:PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
0 0X 1 8 None 1 10 bits
1 0X 1 9 None 1 11 bits
0 10 1 7 Even 1 10 bits
0 11 1 7 Odd 1 10 bits
1 10 1 8 Even 1 11 bits
1 11 1 8 Odd 1 11 bits
Address: $0039
Bit 7654321Bit 0
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Figure 13-9. SCI Control Register 2 (SCC2)