MC68HC908MR32 MC68HC908MR16 Data Sheet M68HC08 Microcontrollers MC68HC908MR32 Rev. 6.1 07/2005 freescale.
MC68HC908MR32 MC68HC908MR16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved.
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level August, 2001 3.0 October, 2001 4.0 December, 2001 5.0 Page Number(s) Description Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect Register (FLBPR) at address location $FF7E 29 Figure A-1.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 1.4.10 1.4.11 1.4.12 1.4.13 1.4.14 1.4.15 1.4.16 1.4.17 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . .
Table of Contents 2.8.7 2.8.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. .
4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.5 4.5.1 4.5.2 4.5.3 4.6 4.7 4.8 4.8.1 4.8.2 4.8.3 4.8.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Chapter 7 Central Processor Unit (CPU) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.4 10.4.1 10.4.2 10.5 10.6 10.6.1 10.6.2 10.7 10.7.1 10.7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 12.6.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Initialization and the PWMEN Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.7.3 13.7.4 13.7.5 13.7.6 13.7.7 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 15.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 17 Timer Interface B (TIMB) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.1 TIMB Counter Prescaler. . . . . . . . . .
Table of Contents 18.3 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.2 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 General Description 1.1 Introduction The MC68HC908MR32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908MR16 with the exceptions shown in Appendix A MC68HC908MR16. 1.
General Description • • • • • Available packages: – 64-pin plastic quad flat pack (QFP) – 56-pin shrink dual in-line package (SDIP) Low-power design, fully static with wait mode Master reset pin (RST) and power-on reset (POR) Stop mode as an option Break module (BRK) supports setting the in-circuit simulator (ICS) single break point Features of the CPU08 include: • Enhanced M68HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the M68HC05) • 16-bit index reg
Freescale Semiconductor PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTER
General Description 1.4 Pin Assignments PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 VSSAD OSC2 OSC1 CGMXFC VDDAD 62 61 60 59 58 57 56 55 54 53 52 51 50 PTB2/ATD2 1 49 RST PTB0/ATD0 63 64 PTB1/ATD1 Figure 1-2 shows the 64-pin QFP pin assignments and Figure 1-3 shows the 56-pin SDIP pin assignments.
Pin Assignments PTA2 1 56 PTA1 PTA3 2 55 PTA0 PTA4 3 54 VSSA PTA5 4 53 OSC2 PTA6 5 52 OSC1 PTA7 6 51 CGMXFC PTB0/ATD0 7 50 VDDA PTB1/ATD1 8 49 RST PTB2/ATD2 9 48 IRQ PTB3/ATD3 10 47 PTF5/TxD PTB4/ATD4 11 46 PTF4/RxD PTB5/ATD5 12 45 VSS PTB6/ATD5 13 44 VDD PTB7/ATD7 14 43 PTE7/TCH3A PTC0/ATD8 15 42 PTE6/TCH2A VDDAD 16 41 PTE5/TCH1A VSSAD/VREFL 17 40 PTE4/TCH0A VREFH 18 39 PTE3/TCLKA PTC2 19 38 NC PTC3 20 37 PWM6 PTC4 21 36 PW
General Description 1.4.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1.
Pin Assignments 1.4.6 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module (CGM). 1.4.7 Analog Power Supply Pins (VDDAD and VSSAD) VDDAD and VSSAD are the power supply pins for the analog-to-digital converter. Decoupling of these pins should be per the digital supply. See Chapter 3 Analog-to-Digital Converter (ADC). 1.4.
General Description 1.4.15 PWM Ground Pin (PWMGND) PWMGND is the ground pin for the pulse-width modulator module (PWMMC). This dedicated ground pin is used as the ground for the six high-current PWM pins. See Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC). 1.4.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA and PTE2/TCH1B–PTE0/TCLKB) Port E is an 8-bit special function port that shares its pins with the two timer interface modules (TIMA and TIMB).
Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 32 Kbytes of FLASH • 768 bytes of random-access memory (RAM) • 46 bytes of user-defined vectors • 240 bytes of monitor read-only memory (ROM) 2.2 Unimplemented Memory Locations Some addresses are unimplemented. Accessing an unimplemented address can cause an illegal address reset.
Memory 2.4 I/O Section Addresses $0000–$005F, shown in Figure 2-2, contain most of the control, status, and data registers.
Memory Map $0000 ↓ I/O REGISTERS — 96 BYTES $005F $0060 ↓ RAM — 768 BYTES $035F $0360 ↓ UNIMPLEMENTED — 31,904 BYTES $7FFF $8000 ↓ FLASH — 32,256 BYTES $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE04 RESERVED $FE05 RESERVED $FE06 RESERVED $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 UNIMPLEMENTED $FE0A UNIMPLEMENTED $FE0B UNIMPLEMENTED $FE0C SIM BREAK ADDRESS R
Memory Addr. $0000 $0001 $0002 $0003 $0004 $0005 Register Name Port A Data Register Read: (PTA) Write: See page 103. Reset: Port B Data Register Read: (PTB) Write: See page 104. Reset: Port D Data Register (PTD) Write: See page 107. Reset: 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTC2 PTC1 PTC0 Unaffected by reset PTB7 Port E Data Register Read: (PTE) Write: See page 108. Reset: Port F Data Register Read: (PTF) Write: See page 110.
Memory Map Addr. Register Name Bit 7 Read: $000E TIMA Status/Control Register (TASC) Write: See page 226. Reset: TOF $0019 Bit 0 PS2 PS1 PS0 0 0 0 0 0 TIMA Counter Register High Read: (TACNTH) Write: See page 227. Reset: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 R R R R R R R R 0 0 0 0 0 0 0 0 TIMA Counter Register Low Read: (TACNTL) Write: See page 227.
Memory Addr. Register Name Read: $001A $001B $001C $001D TIMA Channel 2 Register High (TACH2H) Write: See page 232. Reset: TIMA Channel 2 Register Low Read: (TACH2L) Write: See page 232. Reset: TIMA Channel 3 Status/Control Read: Register (TASC3) Write: See page 229. Reset: TIMA Channel 3 Register High Read: (TACH3H) Write: See page 232. Reset: Read: $001E TIMA Channel 3 Register Low (TACH3L) Write: See page 232. Reset: Configuration Register Read: (CONFIG) Write: See page 74.
Memory Map Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 PWM Counter Register High (PCNTH) Write: See page 143. Reset: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 PWM Counter Register Low Read: (PCNTL) Write: See page 143.
Memory Addr. Register Name Read: PWM 5 Value Register High (PMVAL5H) Write: See page 145. Reset: $0032 PWM 5 Value Register Low Read: (PVAL5L) Write: See page 145. Reset: $0033 PWM 6 Value Register High Read: (PVAL6H) Write: See page 145. Reset: $0034 PWM 6 Value Register Low Read: (PMVAL6L) Write: See page 145. Reset: $0035 Read: Dead-Time Write-Once Register (DEADTM) Write: See page 150. Reset: $0036 $0037 PWM Disable Mapping Read: Write-Once Register (DISMAP) Write: See page 137.
Memory Map Addr. Register Name Bit 7 6 SCI Baud Rate Register (SCBR) Write: See page 177. Reset: 0 0 R R 0 0 IRQ Status/Control Register Read: (ISCR) Write: See page 94. Reset: 0 0 R R 0 0 0 0 0 AIEN ADCO ADCH4 0 0 0 0 R Read: $003E $003F $0040 $0041 ADC Data Register High Read: Right Justified Mode (ADRH) Write: See page 54. Reset: Read: ADC Data Register Low Right Justified Mode (ADRL) Write: See page 54.
Memory Addr. Register Name Read: TIMB Counter Register Low (TBCNTL) Write: See page 246. Reset: $0053 $0054 $0055 $0056 TIMB Counter Modulo Register Read: High (TBMODH) Write: See page 246. Reset: TIMB Counter Modulo Register Read: Low (TBMODL) Write: See page 246. Reset: TIMB Channel 0 Status/Control Read: Register (TBSC0) Write: See page 247. Reset: Read: $0057 $0058 $0059 $005A TIMB Channel 0 Register High (TBCH0H) Write: See page 250.
Memory Map Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 SIM Break Status Register (SBSR) Write: See page 191. Reset: R R R R R R BW R SIM Reset Status Register Read: (SRSR) Write: See page 192.
Memory Table 2-1 is a list of vector locations. Table 2-1.
Monitor ROM Table 2-1.
Memory During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.8 FLASH Memory (FLASH) The FLASH memory is an array of 32,256 bytes with an additional 46 bytes of user vectors and one byte of block protection.
FLASH Memory (FLASH) HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit Setting this read/write bit configures the 32-Kbyte FLASH array for mass erase operation.
Memory 2.8.3 FLASH Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH memory. 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms). 7. Clear the ERASE and MASS bits.
FLASH Memory (FLASH) 2.8.4 FLASH Program Operation Use the following step-by-step procedure to program a row of FLASH memory. Figure 2-4 shows a flowchart of the programming algorithm. NOTE Only bytes which are currently $FF may be programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4.
Memory ALGORITHM FOR PROGRAMMING A ROW (64 BYTES) OF FLASH MEMORY 1 2 3 4 5 6 7 8 SET PGM BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED WAIT FOR A TIME, tNVS SET HVEN BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO 10 11 CLEAR PGM BIT WAIT FOR A TIME, tNVH Note: The time between each FLASH address change (step 7 to step 7), or
FLASH Memory (FLASH) 2.8.5 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
Memory 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH BLOCK PROTECT 1 FLBPR VALUE 0 0 0 0 0 0 0 Figure 2-6. FLASH Block Protect Start Address Refer to Table 2-2 for examples of the protect start address. Table 2-2. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range $00 The entire FLASH memory is protected. $01 (0000 0001) $8080 (1000 0000 1000 0000) $02 (0000 0010) $8100 (1000 0001 0000 0000) and so on...
Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • 10 channels with multiplexed input • Linear successive approximation • 10-bit resolution, 8-bit accuracy • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode • High impedance buffered ADC input 3.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Functional Description INTERNAL DATA BUS PTB/Cx ADC CHANNEL x READ PTB/PTC DISABLE ADC DATA REGISTERS INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC VOLTAGE IN ADVIN ADC CHANNEL SELECT ADCH[4:0] COCO ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 3-2. ADC Block Diagram 3.3.1 ADC Port I/O Pins PTC1/ATD9:PTC0/ATD8 and PTB7/ATD7:PTB0/ATD0 are general-purpose I/O pins that are shared with the ADC channels.
Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADSCR. A conversion is between 16 and 17 ADC clock cycles, therefore: 16 to17 ADC Cycles Conversion time = ADC Frequency Number of Bus Cycles = Conversion Time x CPU Bus Frequency The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is either the bus clock or CGMXCLK and is selectable by ADICLK located in the ADC clock register.
Functional Description significant bits (LSB), located in the ADC data register low, ADRL, can be ignored. However, ADRL must be read after ADRH or else the interlocking will prevent all new conversions from being stored. Right justification will place only the two MSBs in the corresponding ADC data register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This mode of operation typically is used when a 10-bit unsigned result is desired.
Analog-to-Digital Converter (ADC) 3.4 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 3.5 Wait Mode The WAIT instruction can put the MCU in low power-consumption standby mode. The ADC continues normal operation during wait mode.
I/O Registers 3.6.5 ADC Voltage In (ADVIN) ADVIN is the input voltage signal from one of the 10 ADC channels to the ADC module. 3.6.6 ADC External Connections This section describes the ADC external connections: VREFH and VREFL, ANx, and grounding. 3.6.6.1 VREFH and VREFL Both ac and dc current are drawn through the VREFH and VREFL loop. The AC current is in the form of current spikes required to supply charge to the capacitor array at each successive approximation step.
Analog-to-Digital Converter (ADC) 3.7.1 ADC Status and Control Register This section describes the function of the ADC status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion. Address: $0040 Bit 7 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 1 1 1 1 1 Read: COCO Write: R Reset: 0 0 R = Reserved Figure 3-4.
I/O Registers The voltage levels supplied from internal reference nodes as specified in Table 3-1 are used to verify the operation of the ADC both in production test and for user applications. Table 3-1.
Analog-to-Digital Converter (ADC) 3.7.2 ADC Data Register High In left justified mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
I/O Registers Address: $0042 Bit 7 6 5 4 3 2 1 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: R R R R R R R R R = Reserved Reset: Unaffected by reset Figure 3-8. ADC Data Register Low (ADRL) Right Justified Mode In 8-bit mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated each time an ADC conversion completes. In 8-bit mode, this register contains no interlocking with ADRH.
Analog-to-Digital Converter (ADC) ADICLK — ADC Input Clock Select Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at fADIC, correct operation can be guaranteed.
Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module (CGM, version A). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system integration module (SIM) derives the system clocks. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
Clock Generator Module (CGM) CRYSTAL OSCILLATOR OSC2 CGMXCLK CLOCK SELECT CIRCUIT OSC1 A ÷2 CGMOUT B S* TO SIM TO SIM *WHEN S = 1, CGMOUT = B SIMOSCEN CGMRDV CGMRCLK VDDA BCS CGMXFC USER MODE VSS PTC2 VRS[7:4] MONITOR MODE VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PHASE DETECTOR PLL ANALOG LOCK DETECTOR LOCK AUTO CGMINT INTERRUPT CONTROL BANDWIDTH CONTROL ACQ PLLIE PLLF MUL[7:4] CGMVDV CGMVCLK FREQUENCY DIVIDER Figure 4-1. CGM Block Diagram Addr.
Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
Clock Generator Module (CGM) The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. 4.3.2.2 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: 1.
Functional Description The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX and require fast startup. These conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear.
Clock Generator Module (CGM) 5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES. fBUS = Example: N = fVCLK 4 32 MHz = 8 MHz 4 MHz 6. If the calculated fBUS is not within the tolerance limits of the application, select another fBUSDES or another fRCLK. 7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL. fVCLK ) L = round ( f NOM Example: L = 32 MHz = 7 MHz 4.9152 MHz 8.
Functional Description two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected.
Clock Generator Module (CGM) Figure 4-3 also shows the external components for the PLL: • Bypass capacitor, CBYP • Filter capacitor, CF NOTE Routing should be done with great care to minimize signal cross talk and noise. (See 4.8 Acquisition/Lock Time Specifications for routing information and more information on the filter capacitor’s value and its effects on PLL performance.) 4.4 I/O Signals This section describes the CGM input/output (I/O) signals. 4.4.
CGM Registers 4.4.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 4-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup. 4.4.
Clock Generator Module (CGM) 4.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. Address: $005C Bit 7 Read: Write: Reset: PLLIE 6 PLLF R 0 0 R = Reserved 5 4 PLLON BCS 1 0 3 2 1 Bit 0 1 1 1 1 R R R R 1 1 1 1 Figure 4-5.
CGM Registers if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See 4.3.3 Base Clock Selector Circuit. PCTL[3:0] — Unimplemented Bits These bits provide no function and always read as logic 1s. 4.5.
Clock Generator Module (CGM) XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. To check the status of the crystal reference, follow these steps: 1. Write a logic 1 to XLD. 2. Wait N × 4 cycles. (N is the VCO frequency multiplier.) 3. Read XLD. The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT.
Interrupts NOTE The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS[7:4] — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency fVRS. See 4.3.2.1 PLL Circuits, 4.3.2.4 Programming the PLL and 4.5.1 PLL Control Register. VRS[7:4] cannot be written when the PLLON bit in the PLL control register (PCTL) is set. See 4.3.2.
Clock Generator Module (CGM) 4.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 4.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
Acquisition/Lock Time Specifications required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency, fXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor.
Clock Generator Module (CGM) The K factor in the equations is derived from internal PLL parameters. KACQ is the K factor when the PLL is configured in acquisition mode, and KTRK is the K factor when the PLL is configured in tracking mode. See 4.3.2.2 Acquisition and Tracking Modes.
Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration register (CONFIG). This register contains bits that configure these options: • Resets caused by the low-voltage inhibit (LVI) module • Power to the LVI module • Computer operating properly (COP) module • Top-side pulse-width modulator (PWM) polarity • Bottom-side PWM polarity • Edge-aligned versus center-aligned PWMs • Six independent PWMs versus three complementary PWM pairs 5.
Configuration Register (CONFIG) 5.3 Configuration Register Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD 0 0 0 0 1 1 0 0 Figure 5-1. Configuration Register (CONFIG) EDGE — Edge-Align Enable Bit EDGE determines if the motor control PWM will operate in edge-aligned mode or center-aligned mode. See Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC).
Chapter 6 Computer Operating Properly (COP) 6.1 Introduction This section describes the computer operating properly module, a free-running counter that generates a reset if allowed to overflow. The computer operating properly (COP) module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. 6.2 Functional Description Figure 6-1 shows the structure of the COP module. A summary of the input/output (I/O) register is shown in Figure 6-2.
Computer Operating Properly (COP) Addr. $FFFF Register Name Bit 7 COP Control Register (COPCTL) See page 77. 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 6-2. COP I/O Register Summary The COP counter is a free-running, 6-bit counter preceded by the 13-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218–24 CGMXCLK cycles. With a 4.
COP Control Register 6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register (CONFIG). 6.4 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Computer Operating Properly (COP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide Exclusive OR M with A Increment M ← $00 A ← $00 X ← $00 H ← $00 M ← $00
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 0
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 8 External Interrupt (IRQ) 8.1 Introduction This section describes the external interrupt (IRQ) module, which supports external interrupt functions. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin, IRQ • Hysteresis buffers 8.3 Functional Description A logic 0 applied to any of the external interrupt pins can latch a CPU interrupt request. Figure 8-1 shows the structure of the IRQ module.
External Interrupt (IRQ) Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. • Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR).
IRQ Pin FROM RESET YES I BIT SET? NO INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 8-3. IRQ Interrupt Flowchart MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
External Interrupt (IRQ) A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level- sensitive. With MODE1 set, both of these actions must occur to clear the IRQ1 latch: • Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal to clear the latch.
IRQ Status and Control Register IMASK1 — IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE1 — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE1.
External Interrupt (IRQ) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 9 Low-Voltage Inhibit (LVI) 9.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage. 9.2 Features Features of the LVI module include: • Programmable LVI reset • Programmable power consumption • Digital filtering of VDD pin level • Selectable LVI trip voltage 9.3 Functional Description Figure 9-1 shows the structure of the LVI module.
Low-Voltage Inhibit (LVI) Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VLVRX + VLVHX. VDD must be above VLVRX + VLVHX for only one CPU cycle to bring the MCU out of reset. See 14.3.2.6 Low-Voltage Inhibit (LVI) Reset. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISCR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. See 19.5 DC Electrical Characteristics.
LVI Status and Control Register 9.4 LVI Status and Control Register The LVI status register (LVISCR) flags VDD voltages below the VLVRX level. Address: $FE0F Bit 7 6 5 Read: LVIOUT 0 Write: R R Reset: 0 0 R = Reserved TRPSEL 0 4 3 2 1 Bit 0 0 0 0 0 0 R R R R R 0 0 0 0 0 Figure 9-3. LVI Status and Control Register (LVISCR) LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VLVRX voltage for 32 to 40 CGMXCLK cycles. See Table 9-1.
Low-Voltage Inhibit (LVI) With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset and bring the MCU out of wait mode. 9.7 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 Introduction Thirty-seven bidirectional input-output (I/O) pins and seven input pins form six parallel ports. All I/O pins are programmable as inputs or outputs. When using the 56-pin package version: • Set the data direction register bits in DDRC such that bit 1 is written to a logic 1 (along with any other output bits on port C).
Input/Output (I/O) Ports (PORTS) Addr. $0005 $0006 Register Name Data Direction Register B (DDRB) See page 105. Data Direction Register C (DDRC) See page 106. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 PTE2 PTE1 PTE0 PTF2 PTF1 PTF0 Read: 0 Write: R Reset: 0 $0007 $0008 $0009 Unimplemented Port E Data Register (PTE) See page 108.
Port A 10.2 Port A Port A is an 8-bit, general-purpose, bidirectional I/O port. 10.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins. Address: Read: Write: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Reset: Unaffected by reset Figure 10-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable.
Input/Output (I/O) Ports (PORTS) READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx PTAx READ PTA ($0000) Figure 10-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-1 summarizes the operation of the port A pins. Table 10-1.
Port B 10.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 10-6.
Input/Output (I/O) Ports (PORTS) 10.4 Port C Port C is a 7-bit, general-purpose, bidirectional I/O port that shares two of its pins with the analog-to-digital convertor module (ADC). 10.4.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. Address: $0002 Bit 7 Read: 0 Write: R 6 5 4 3 2 1 Bit 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Reset: Unaffected by reset R = Reserved Figure 10-8.
Port D Figure 10-10 shows the port C I/O logic. READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx READ PTC ($0002) Figure 10-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-3 summarizes the operation of the port C pins.
Input/Output (I/O) Ports (PORTS) INTERNAL DATA BUS Figure 10-12 shows the port D input logic. READ PTD ($0003) PTDx Figure 10-12. Port D Input Circuit Reading address $0003 reads the voltage level on the pin. Table 10-4 summarizes the operation of the port D pins. Table 10-4. Port D Pin Functions PTD Bit Accesses to PTD Pin Mode (1) Input, X Hi-Z(2) Read Write Pin PTD[6:0](3) 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. 10.
Port E 10.6.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $000C Bit 7 6 5 4 3 2 1 Bit 0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 0 Figure 10-14.
Input/Output (I/O) Ports (PORTS) 10.7 Port F Port F is a 6-bit, special function port that shares four of its pins with the serial peripheral interface module (SPI) and two pins with the serial communications interface (SCI). 10.7.1 Port F Data Register The port F data register (PTF) contains a data latch for each of the six port F pins. Address: $0009 Bit 7 6 Read: 0 0 Write: R R R = Reserved 5 4 3 2 1 Bit 0 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Reset: Unaffected by reset Figure 10-16.
Port F Figure 10-18 shows the port F I/O logic. READ DDRF ($000D) INTERNAL DATA BUS WRITE DDRF ($000D) RESET DDRFx WRITE PTF ($0009) PTFx PTFx READ PTF ($0009) Figure 10-18. Port F I/O Circuit When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-6 summarizes the operation of the port F pins.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 11 Power-On Reset (POR) 11.1 Introduction This section describes the power-on reset (POR) module. 11.2 Functional Description The POR module provides a known, stable signal to the microcontroller unit (MCU) at power-on. This signal tracks VDD until the MCU generates a feedback signal to indicate that it is properly initialized. At this time, the POR drives its output low. The POR is not a brown-out detector, low-voltage detector, or glitch detector.
Power-On Reset (POR) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) 12.1 Introduction This section describes the pulse-width modulator for motor control (PWMMC, version A). The PWM module can generate three complementary PWM pairs or six independent PWM signals. These PWM signals can be center-aligned or edge-aligned. A block diagram of the PWM module is shown in Figure 12-2. A12-bit timer PWM counter is common to all six channels.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Features 8 CPU BUS PWM1 PIN PWM2 PIN PWM CHANNELS 3 AND 4 FAULT PROTECTION OUTPUT CONTROL CONTROL LOGIC BLOCK PWM CHANNELS 1 AND 2 PWM3 PIN PWM4 PIN PWM5 PIN PWM CHANNELS 5 AND 6 PWM6 PIN FAULT INTERRUPT PINS 4 12 TIMEBASE 3 COIL CURRENT POLARITY PINS Figure 12-2. PWM Module Block Diagram Addr. Register Name $0020 PWM Control Register 1 (PCTL1) See page 146. $0021 $0022 $0023 $0024 PWM Control Register 2 (PCTL2) See page 148. Fault Control Register (FCR) See page 150.
Pulse-Width Modulator for Motor Control (PWMMC) Addr. $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F Register Name Bit 7 PWM Output Control Register (PWMOUT) See page 154. PWM Counter Register High (PCNTH) See page 143. PWM Counter Register Low (PCNTL) See page 143. PWM Counter Modulo Register High (PMODH) See page 144. PWM Counter Modulo Register Low (PMODL) See page 144. PWM 1 Value Register High (PVAL1H) See page 145. PWM 1 Value Register Low (PVAL1L) See page 145.
Features Addr. $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 Register Name PWM 4 Value Register High (PVAL4H) See page 145. PWM 4 Value Register Low (PVAL4L) See page 145. PWM 5 Value Register High (PVAL5H) See page 145. PWM 5 Value Register Low (PVAL5L) See page 145. PWM 6 Value Register High (PVAL6H) See page 145. PWM 6 Value Register Low (PMVAL6L) See page 145. Dead-Time Write-Once Register (DEADTM) See page 150. PWM Disable Mapping Write-Once Register (DISMAP) See page 150.
Pulse-Width Modulator for Motor Control (PWMMC) 12.3 Timebase This section provides a discussion of the timebase. 12.3.1 Resolution In center-aligned mode, a 12-bit up/down counter is used to create the PWM period. Therefore, the PWM resolution in center-aligned mode is two clocks (highest resolution is 250 ns @ fOP = 8 MHz) as shown in Figure 12-4. The up/down counter uses the value in the timer modulus register to determine its maximum count.
Timebase For edge-aligned mode, a 12-bit up-only counter is used to create the PWM period. Therefore, the PWM resolution in edge-aligned mode is one clock (highest resolution is125 ns @ fOP = 8 MHz) as shown in Figure 12-5. Again, the timer modulus register is used to determine the maximum count. The PWM period will equal: (timer modulus) x (PWM clock period) Center-aligned operation versus edge-aligned operation is determined by the option EDGE. See 5.2 Functional Description.
Pulse-Width Modulator for Motor Control (PWMMC) 12.3.2 Prescaler To permit lower PWM frequencies, a prescaler is provided which will divide the PWM clock frequency by 1, 2, 4, or 8. Table 12-1 shows how setting the prescaler bits in PWM control register 2 affects the PWM clock frequency. This prescaler is buffered and will not be used by the PWM generator until the LDOK bit is set and a new PWM reload cycle begins. Table 12-1.
PWM Generators For ease of software, the LDFQx bits are buffered. When the LDFQx bits are changed, the reload frequency will not change until the previous reload cycle is completed. See Figure 12-6. NOTE When reading the LDFQx bits, the value is the buffered value (for example, not necessarily the value being acted upon). RELOAD RELOAD RELOAD RELOAD RELOADRELOADRELOAD CHANGE RELOAD FREQUENCY TO EVERY 4 CYCLES CHANGE RELOAD FREQUENCY TO EVERY CYCLE Figure 12-6.
Pulse-Width Modulator for Motor Control (PWMMC) LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) UP/DOWN COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMF SET LDOK = 0 MODULUS = 3 PWM VALUE = 2 PWMF SET LDOK = 1 MODULUS = 3 PWM VALUE = 2 PWMF SET LDOK = 0 MODULUS = 3 PWM VALUE = 1 PWMF SET PWM Figure 12-8.
PWM Generators LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) UP-ONLY COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 2 PWMF SET LDOK = 1 MODULUS = 4 PWM VALUE = 2 PWMF SET LDOK = 1 MODULUS = 2 PWM VALUE = 2 PWMF SET LDOK = 0 MODULUS = 1 PWM VALUE = 2 PWMF SET PWM Figure 12-11. Edge-Aligned Modulus Loading 12.4.2 PWM Data Overflow and Underflow Conditions The PWM value registers are 16-bit registers. Although the counter is only 12 bits, the user may write a 16-bit signed value to a PWM value register.
Pulse-Width Modulator for Motor Control (PWMMC) 12.5 Output Control This subsection discusses output control. 12.5.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs The PWM outputs can be configured as six independent PWM channels or three complementary channel pairs. The option INDEP determines which mode is used (see 5.2 Functional Description). If complementary operation is chosen, the PWM pins are paired as shown in Figure 12-12.
Output Control When complementary operation is used, two additional features are provided: • Dead-time insertion • Separate top/bottom pulse width correction to correct for distortions caused by the motor drive characteristics If independent operation is chosen, each PWM has its own PWM value register. 12.5.2 Dead-Time Insertion As shown in Figure 12-13, in complementary mode, each PWM pair can be used to drive top-side/bottom-side transistors.
Pulse-Width Modulator for Motor Control (PWMMC) PREDT (TOP) OUTX SELECT DEAD-TIME POSTDT (TOP) MUX PWMPAIR56 (TOP) PWM (TOP) PREDT (TOP) OUTX SELECT PWM1 BOTTOM (PWM2) PWM2 TOP (PWM3) BOTTOM (PWM4) POLARITY/OUTPUT DRIVE PWM (TOP) TOP (PWM1) FAULT DEAD-TIME POSTDT (TOP) MUX PWMPAIR34 (TOP) TOP/BOTTOM GENERATION DEAD-TIME 6 CURRENT SENSING PWMGEN<1:6> PWM GENERATOR PREDT (TOP) OUTX SELECT DEAD-TIME POSTDT (TOP) DEAD-TIME PWM (TOP) DEAD-TIME MUX PWMPAIR12 (TOP) TOP/BOTTOM GENERATION
Output Control UP/DOWN COUNTER MODULUS = 4 PWM VALUE = 2 PWM VALUE = 2 PWM VALUE = 3 PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME = 2 2 PWM2 W/ DEAD-TIME = 2 2 2 2 2 2 Figure 12-15. Effects of Dead-Time Insertion UP/DOWN COUNTER MODULUS = 3 PWM VALUE = 1 PWM VALUE = 1 PWM VALUE = 3 PWM VALUE = 3 PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME = 2 PWM2 W/ DEAD-TIME = 2 2 2 2 2 Figure 12-16.
Pulse-Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MOUDULUS = 3 PWM VALUE = 2 PWM VALUE = 3 PWM VALUE = 2 PWM VALUE = 1 PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME = 3 3 3 PWM2 W/ DEAD-TIME = 3 3 3 3 3 Figure 12-17. Dead-Time and Small Pulse Widths 12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing Ideally, when complementary pairs are used, the PWM pairs are inversions of each other, as shown in Figure 12-18.
Output Control For a typical motor drive inverter as shown in Figure 12-13, for a given top/bottom transistor pair, only one of the transistors will be effective in controlling the output voltage at any given time depending on the direction of the motor current for that pair. To achieve distortion correction, one of two different correction factors must be added to the desired PWM value, depending on whether the top or bottom transistor is controlling the output voltage.
Pulse-Width Modulator for Motor Control (PWMMC) To allow for correction based on different current sensing methods or correction controlled by software, the ISENS1 and ISENS0 bits in PWM control register 1 are provided to choose the correction method. These bits provide correction according to Table 12-5. Table 12-5.
Output Control PWM VALUE REG. 2 = 2 PWM VALUE REG. 1 = 1 IS1 POSITIVE PWM = 1 IS1 POSITIVE PWM = 1 IS1 NEGATIVE PWM = 2 IS1 NEGATIVE PWM = 2 PWM1 PWM2 Figure 12-20. Top/Bottom Correction for PWMs 1 and 2 12.5.4 Output Polarity The output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG. The top polarity option, TOPNEG, controls the polarity of PWMs 1, 3, and 5. The bottom polarity option, BOTNEG, controls the polarity of PWMs 2, 4, and 6.
Pulse-Width Modulator for Motor Control (PWMMC) CENTER-ALIGNED POSITIVE POLARITY EDGE-ALIGNED POSITIVE POLARITY UP-ONLY COUNTER MODULUS = 4 UP/DOWN COUNTER MODULUS = 4 PWM <= 0 PWM <= 0 PWM = 1 PWM = 1 PWM = 2 PWM = 2 PWM = 3 PWM = 3 PWM >= 4 PWM >= 4 CENTER-ALIGNED NEGATIVE POLARITY EDGE-ALIGNED NEGATIVE POLARITY UP-ONLY COUNTER MODULUS = 4 UP/DOWN COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM <= 0 PWM = 2 PWM = 1 PWM = 3 PWM = 2 PWM = 3 PWM >= 4 PWM >= 4 Figure 12-21.
Output Control 12.5.5 PWM Output Port Control Conditions may arise in which the PWM pins need to be individually controlled. This is made possible by the PWM output control register (PWMOUT) shown in Figure 12-22. Address: $0025 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 OUTCTL OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 0 0 0 0 0 0 0 = Unimplemented Figure 12-22. PWM Output Control Register (PWMOUT) If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx bits.
Pulse-Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MODULUS = 4 DEAD-TIME = 2 PWM VALUE = 3 OUTCTL OUT1 OUT2 PWM1 PWM2 PWM1/PWM2 DEAD-TIME 2 2 2 DEAD-TIME INSERTED AS PART OF DEAD-TIME INSERTED DUE NORMAL PWM OPERATION AS TO SETTING OF OUT1 BIT CONTROLLED BY CURRENT SENSING AND PWM GENERATOR DEAD-TIME INSERTED DUE TO CLEARING OF OUT1 BIT Figure 12-23.
Fault Protection 12.6 Fault Protection Conditions may arise in the external drive circuitry which require that the PWM signals become inactive immediately, such as an overcurrent fault condition. Furthermore, it may be desirable to selectively disable PWM(s) solely with software.
Pulse-Width Modulator for Motor Control (PWMMC) DISX CYCLE START SOFTWARE X DISABLE S Q R FMODE2 TWO SAMPLE FILTER FAULT PIN2 AUTO MODE FPIN2 LOGIC HIGH FOR FAULT ONE SHOT BANK X DISABLE FAULT PIN 2 DISABLE S Q FFLAG2 R S Q R MANUAL MODE CLEAR BY WRITING 1 TO FTACK4 INTERRUPT REQUEST FINT2 The example is of fault pin 2 with DISX. Fault pin 4 with DISY is logically similar and affects BANK Y disable.
Fault Protection BIT 7 DISABLE PWM PIN 1 BIT 6 BANK X DISABLE BIT 5 DISABLE PWM PIN 2 BIT 4 DISABLE PWM PIN 3 BIT 3 BANK Y DISABLE DISABLE PWM PIN 4 BIT 2 BIT 1 DISABLE PWM PIN 5 BIT 0 DISABLE PWM PIN 6 Figure 12-27. PWM Disabling Decode Scheme 12.6.1.1 Fault Pin Filter Each fault pin incorporates a filter to assist in determining a genuine fault condition.
Pulse-Width Modulator for Motor Control (PWMMC) FILTERED FAULT PIN PWM(S) ENABLED PWM(S) DISABLED (INACTIVE) PWM(S) ENABLED Figure 12-28. PWM Disabling in Automatic Mode IIf prior to a vector fetch, the interrupt request latch is cleared by one of the actions listed, a CPU interrupt will no longer be requested. A vector fetch does not alter the state of the PWMs, the FFLAGx event flag, or FINTx.
Fault Protection FILTERED FAULT PIN 2 OR 4 PWM(S) ENABLED PWM(S) DISABLED PWM(S) ENABLED FFLAGX CLEARED Figure 12-30. PWM Disabling in Manual Mode (Example 2) 12.6.2 Software Output Disable Setting PWM disable bit DISX or DISY in PWM control register 1 immediately disables the corresponding PWM pins as determined by the bank and disable mapping register. The PWM pin(s) remain disabled until the PWM disable bit is cleared and a new PWM cycle begins as shown in Figure 12-31.
Pulse-Width Modulator for Motor Control (PWMMC) 12.7 Initialization and the PWMEN Bit For proper operation, all registers should be initialized and the LDOK bit should be set before enabling the PWM via the PWMEN bit. When the PWMEN bit is first set, a reload will occur immediately, setting the PWMF flag and generating an interrupt if PWMINT is set. In addition, in complementary mode, PWM value registers 1, 3, and 5 will be used for the first PWM cycle if current sensing is selected.
PWM Operation in Wait Mode 12.8 PWM Operation in Wait Mode When the microcontroller is put in low-power wait mode via the WAIT instruction, all clocks to the PWM module will continue to run. If an interrupt is issued from the PWM module (via a reload or a fault), the microcontroller will exit wait mode. Clearing the PWMEN bit before entering wait mode will reduce power consumption in wait mode because the counter, prescaler divider, and LDFQ divider will no longer be clocked.
Pulse-Width Modulator for Motor Control (PWMMC) 12.9.2 PWM Counter Modulo Registers The PWM counter modulus registers (PMODH and PMODL) hold a 12-bit unsigned number that determines the maximum count for the up/down or up-only counter. In center-aligned mode, the PWM period will be twice the modulus (assuming no prescaler). In edge-aligned mode, the PWM period will equal the modulus. See Figure 12-35 and Figure 12-36.
Control Logic Block 12.9.3 PWMx Value Registers Each of the six PWMs has a 16-bit PWM value register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bold = Buffered Figure 12-37. PWMx Value Registers High (PVALxH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bold = Buffered Figure 12-38.
Pulse-Width Modulator for Motor Control (PWMMC) 12.9.4 PWM Control Register 1 PWM control register 1 (PCTL1) controls PWM enabling/disabling, the loading of new modulus, prescaler, PWM values, and the PWM correction method. In addition, this register contains the software disable bits to force the PWM outputs to their inactive states (according to the disable mapping register).
Control Logic Block Table 12-7. Correction Methods Current Correction Bits ISENS1 and ISENS0 Correction Method 00 01 Bits IPOL1, IPOL2, and IPOL3 are used for correction. 10 Current sensing on pins IS1, IS2, and IS3 occurs during the dead-time. 11 Current sensing on pins IS1, IS2, and IS3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. 1. The polarity of the ISx pin is latched when both the top and bottom PWMs are off.
Pulse-Width Modulator for Motor Control (PWMMC) 12.9.5 PWM Control Register 2 PWM control register 2 (PCTL2) controls the PWM load frequency, the PWM correction method, and the PWM counter prescaler. For ease of software and to avoid erroneous PWM periods, some of these register bits are buffered. The PWM generator will not use the prescaler value until the LDOK bit has been set, and a new PWM cycle is starting.
Control Logic Block NOTE When reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). The IPOLx bits take effect at the beginning of the next load cycle, regardless of the state of the load okay bit, LDOK. IPOL2 — Top/Bottom Correction Bit for PWM Pair 2 (PWMs 3 and 4) This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be achieved without current sensing. 1 = Use PWM value register 4.
Pulse-Width Modulator for Motor Control (PWMMC) 12.9.6 Dead-Time Write-Once Register The dead-time write-once register (DEADTM) holds an 8-bit value which specifies the number of CPU clock cycles to use for the dead-time when complementary PWM mode is selected. After this register is written for the first time, it cannot be rewritten unless a reset occurs. Dead-time is not affected by changes to the prescaler value.
Control Logic Block FMODE4 —Fault Mode Selection for Fault Pin 4 Bit (automatic versus manual mode) This read/write bit allows the user to select between automatic and manual mode faults. For further descriptions of each mode, see 12.6 Fault Protection. 1 = Automatic mode 0 = Manual mode FINT3 — Fault 3 Interrupt Enable Bit This read/write bit allows the CPU interrupt caused by faults on fault pin 3 to be enabled. The fault protection circuitry is independent of this bit and will always be active.
Pulse-Width Modulator for Motor Control (PWMMC) 12.9.9 Fault Status Register The fault status register (FSR) is a read-only register that indicates the current fault status. Address: $0023 Bit 7 6 5 4 3 2 1 Bit 0 Read: FPIN4 FFLAG4 FPIN3 FFLAG3 FPIN2 FFLAG2 FPIN1 FFLAG1 U 0 U 0 U 0 U 0 Write: Reset: = Unimplemented U = Unaffected Figure 12-44.
Control Logic Block FFLAG1 — Fault Event Flag 1 The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register. 1 = A fault has occurred on fault pin 1. 0 = No new fault on fault pin 1. 12.9.10 Fault Acknowledge Register The fault acknowledge register (FTACK) is used to acknowledge and clear the FFLAGs.
Pulse-Width Modulator for Motor Control (PWMMC) DT2 — Dead-Time 2 Bit Current sensing pin IS1 is monitored immediately before dead-time ends due to the assertion of PWM2. DT1 — Dead-Time 1 Bit Current sensing pin IS1 is monitored immediately before dead-time ends due to the assertion of PWM1. 12.9.11 PWM Output Control Register The PWM output control register (PWMOUT) is used to manually control the PWM pins.
PWM Glossary 12.10 PWM Glossary CPU cycle — One internal bus cycle (1/fOP) PWM clock cycle (or period) — One tick of the PWM counter (1/fOP with no prescaler). See Figure 12-47. PWM cycle (or period) • Center-aligned mode: The time it takes the PWM counter to count up and count down (modulus * 2/fOP assuming no prescaler). See Figure 12-47. • Edge-aligned mode: The time it takes the PWM counter to count up (modulus/fOP). See Figure 12-47.
Pulse-Width Modulator for Motor Control (PWMMC) PWM Load Frequency — Frequency at which new PWM parameters get loaded into the PWM. See Figure 12-48. LDFQ1:LDFQ0 = 01 — Reload Every Two Cycles PWM LOAD CYCLE (1/PWM LOAD FREQUENCY) RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 Figure 12-48. PWM Load Cycle/Frequency Definition MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 13 Serial Communications Interface Module (SCI) 13.1 Introduction This section describes the serial communications interface module (SCI, version D), which allows high-speed asynchronous communications with peripheral devices and other microcontroller units (MCUs). 13.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Functional Description 13.3 Functional Description Figure 13-2 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Serial Communications Interface Module (SCI) Addr. $0038 $0039 $003A $003B $003C Register Name SCI Control Register 1 (SCC1) See page 169. SCI Control Register 2 (SCC2) See page 171. SCI Control Register 3 (SCC3) See page 173. SCI Status Register 1 (SCS1) See page 174. SCI Status Register 2 (SCS2) See page 176. SCI Data Register (SCDR) See page 177. $003D $003E SCI Baud Rate Register (SCBR) See page 177.
Functional Description 13.3.2 Transmitter Figure 13-5 shows the structure of the SCI transmitter.
Serial Communications Interface Module (SCI) 13.3.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 13.3.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PTF5/TxD pin.
Functional Description 13.3.2.4 Idle Characters An idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the PTF5/TxD pin becomes idle after completion of the transmission in progress.
Serial Communications Interface Module (SCI) INTERNAL BUS SCR2 SCR1 SCP0 SCR0 BAUD PRESCALER DIVIDER fOP DATA RECOVERY PTF4/RxD ALL 1s M WAKE ILTY PEN PTY H 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 L ALL 0s RPF CPU INTERRUPT REQUEST ERROR CPU INTERRUPT REQUEST BKF STOP ÷ 16 MSB ÷4 SCI DATA REGISTER START SCP1 SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE RWU IDLE R8 ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Figure 13-6.
Functional Description 13.3.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the PTF4/RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read.
Serial Communications Interface Module (SCI) Table 13-1. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-2 summarizes the results of the data bit samples. Table 13-2.
Functional Description 13.3.3.4 Framing Errors If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. The FE flag is set at the same time that the SCRF bit is set. A break character that has no stop bit also sets the FE bit. 13.3.3.5 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state.
Serial Communications Interface Module (SCI) • • • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop bit.
I/O Registers 13.6.2 PTF4/RxD (Receive Data) The PTF4/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTF4/RxD pin with port F. When the SCI is enabled, the PTF4/RxD pin is an input regardless of the state of the DDRF4 bit in data direction register F (DDRF). 13.
Serial Communications Interface Module (SCI) ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
I/O Registers Table 13-4. Character Format Selection Control Bits Character Format M PEN:PTY Start Bits Data Bits Parity Stop Bits Character Length 0 0X 1 8 None 1 10 bits 1 0X 1 9 None 1 11 bits 0 10 1 7 Even 1 10 bits 0 11 1 7 Odd 1 10 bits 1 10 1 8 Even 1 11 bits 1 11 1 8 Odd 1 11 bits 13.7.
Serial Communications Interface Module (SCI) SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests.
I/O Registers 13.7.
Serial Communications Interface Module (SCI) 13.7.
I/O Registers IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit.
Serial Communications Interface Module (SCI) In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the PTF4/RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set.
I/O Registers RPF —Reception-in-Progress Flag This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress.
Serial Communications Interface Module (SCI) SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 13-6. Reset clears SCR2–SCR0. Table 13-6.
I/O Registers Table 13-7. SCI Baud Rate Selection Examples SCP1:SCP0 Prescaler Divisor (PD) SCR2:SCR1:SCR0 Baud Rate Divisor (BD) Baud Rate (fOP = 7.3728 MHz) Baud Rate (fOP = 4.
Serial Communications Interface Module (SCI) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 14 System Integration Module (SIM) 14.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 14-1. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE WAIT WAIT CONTROL CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL RESET PIN LOGIC CLOCK GENERATORS INTERNAL CLOCKS LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU INTERFACE Figure 14-
Reset and System Initialization CGMXCLK OSC1 CLOCK SELECT CIRCUIT CGMVCLK ÷2 A CGMOUT B S* *When S = 1, CGMOUT = B BUS CLOCK GENERATORS ÷2 SIM BCS PLL SIM COUNTER PTC2 MONITOR MODE USER MODE CGM Figure 14-2. CGM Clock Signals 14.2.3 Clocks in Wait Mode In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
System Integration Module (SIM) Table 14-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) CGMOUT RST IAB VECT H PC VECT L Figure 14-3. External Reset Timing 14.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals.
Reset and System Initialization 14.3.2.1 Power-On Reset (POR) When power is first applied to the MCU, the power-on reset (POR) module generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
System Integration Module (SIM) signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VHI on the RST pin disables the COP module. 14.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset.
Exception Control 14.5 Exception Control Normal, sequential program execution can be changed in three different ways: 1. Interrupts: a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 14.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts.
System Integration Module (SIM) FROM RESET BREAK OR SWI I BIT SET? INTERRUPT? YES NO YES I BIT SET? NO INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 14-8. Interrupt Processing MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Exception Control MODULE INTERRUPT I BIT IAB SP – 4 IDB SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 14-9. Interrupt Recovery 14.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
System Integration Module (SIM) 14.5.1.2 Software Interrupt (SWI) Instruction The software interrupt (SWI) instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. 14.5.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 14.6 Low-Power Mode Executing the WAIT instruction puts the MCU in a low power-consumption mode for standby situations.
SIM Registers 32 CYCLES IAB 32 CYCLES $6E0B IDB $A6 $A6 RST VCT H RST VCT L $A6 RST CGMXCLK Figure 14-13. Wait Recovery from Internal Reset 14.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.
System Integration Module (SIM) SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 14.7.2 SIM Reset Status Register The SIM reset status register (SRSR) contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
SIM Registers 14.7.3 SIM Break Flag Control Register The SIM break control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 BIt 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 14-16. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
System Integration Module (SIM) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 15 Serial Peripheral Interface Module (SPI) 15.1 Introduction The serial peripheral interface (SPI) module allows full-duplex, synchronous, serial communications with peripheral devices. 15.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Functional Description 15.4 Functional Description Figure 15-2 shows the structure of the SPI module and Figure 15-3 shows the locations and contents of the SPI I/O registers. The SPI module allows full-duplex, synchronous, serial communication between the microcontroller unit (MCU) and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt-driven. All SPI interrupts can be serviced by the CPU.
Serial Peripheral Interface Module (SPI) Addr. $0044 Register Name SPI Control Register Read: (SPCR) Write: See page 211. Reset: $0045 SPI Status and Control Read: Register (SPSCR) Write: See page 212. Reset: $0046 SPI Data Register Read: (SPDR) Write: See page 214.
Transmission Formats SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit. 15.4.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0.
Serial Peripheral Interface Module (SPI) The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
Transmission Formats When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS.
Serial Peripheral Interface Module (SPI) When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. See Figure 15-8 The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set.
Error Conditions 15.6 Error Conditions These flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. • Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI.
Serial Peripheral Interface Module (SPI) In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit.
Error Conditions OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes these events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared.
Serial Peripheral Interface Module (SPI) 15.7 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests as shown in Table 15-2. Table 15-2.
Resetting the SPI 15.8 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O.
Serial Peripheral Interface Module (SPI) WRITE TO SPDR 1 SPTE 3 2 8 5 10 SPSCK CPHA:CPOL = 1:0 MSBBIT BIT BIT BIT BIT BIT LSBMSBBIT BIT BIT BIT BIT BIT LSBMSBBIT BIT BIT 6 5 4 6 5 4 3 2 1 6 5 4 3 2 1 BYTE 1 BYTE 2 BYTE 3 MOSI 9 4 SPRF 6 READ SPSCR 11 7 READ SPDR 12 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 7 CPU READS SPDR, CLEARING SPRF BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
I/O Signals The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 15.11.
Serial Peripheral Interface Module (SPI) When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. See 15.12.2 SPI Status and Control Register. NOTE A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state.
I/O Registers Address: $0044 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 0 1 0 1 0 0 0 R = Reserved Figure 15-14. SPI Control Register (SPCR) SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
Serial Peripheral Interface Module (SPI) SPE — SPI Enable Bit This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See 15.8 Resetting the SPI. Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE— SPI Transmit Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
I/O Registers OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit.
Serial Peripheral Interface Module (SPI) Table 15-4. SPI Master Baud Rate Selection SPR1:SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = -------------------------2 × BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor 15.12.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register.
Chapter 16 Timer Interface A (TIMA) 16.1 Introduction This section describes the timer interface module A (TIMA). The TIMA is a 4-channel timer that provides: • Timing reference with input capture • Output compare • Pulse-width modulator functions Figure 16-2 is a block diagram of the TIMA. 16.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Features TCLK PTE3/TCLKA PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL ELS0B CHANNEL 0 ELS0A TOV0 CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L CH0F 16-BIT LATCH MS0A ELS1B CHANNEL 1 MS0B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L CH0IE CH1F 16-BIT LATCH CH1IE MS1A ELS2B CHANNEL 2 ELS2A TOV2 CH2MAX 16-BIT COMPARATOR TCH2H:TCH2L CH2F 16-BIT LATCH MS2A ELS3B CHANNEL 3 MS2B ELS3A TOV3
Timer Interface A (TIMA) Addr. $000E $000F $0010 $0011 $0012 $0013 Register Name Bit 7 $0015 $0016 $0017 $0019 TOIE TSTOP 4 3 0 0 TRST R 2 1 Bit 0 PS2 PS1 PS0 TOF 0 0 1 0 0 0 0 0 TIMA Counter Register High Read: (TACNTH) Write: See page 227.
Functional Description Addr. Register Name Read: $001A $001B $001C $001D TIMA Channel 2 Register High (TACH2H) Write: See page 232. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 Indeterminate after reset TIMA Channel 2 Register Low Read: (TACH2L) Write: See page 232. Reset: TIMA Channel 3 Status/Control Read: Register (TASC3) Write: See page 229. Reset: TIMA Channel 3 Register High Read: (TACH3H) Write: See page 232.
Timer Interface A (TIMA) x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.
Functional Description Use this method to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.
Timer Interface A (TIMA) to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the TIMA to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1). The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments.
Functional Description duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 16.3.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE4/TCH0A pin.
Timer Interface A (TIMA) 4. In TIMA channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 16-2.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB–ELSxA.
I/O Signals The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction. 16.6 I/O Signals Port E shares five of its pins with the TIMA: • PTE3/TCLKA is an external clock input to the TIMA prescaler.
Timer Interface A (TIMA) Address: $000E Bit 7 6 5 TOIE TSTOP 1 Read: TOF Write: 0 Reset: 0 0 R = Reserved 4 3 0 0 TRST R 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 Figure 16-5. TIMA Status and Control Register (TASC) TOF — TIMA Overflow Flag This read/write flag is set when the TIMA counter reaches the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic 0 to TOF.
I/O Registers PS[2:0] — Prescaler Select Bits These read/write bits select either the PTE3/TCLKA pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 16-1 shows. Reset clears the PS[2:0] bits. Table 16-1. Prescaler Selection PS[2:0] TIMA Clock Source 000 Internal bus clock ÷1 001 Internal bus clock ÷ 2 010 Internal bus clock ÷ 4 011 Internal bus clock ÷ 8 100 Internal bus clock ÷ 16 101 Internal bus clock ÷ 32 110 Internal bus clock ÷ 64 111 PTE3/TCLKA 16.7.
Timer Interface A (TIMA) 16.7.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TAMODH) inhibits the TOF bit and overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo registers.
I/O Registers Register Name and Address: Bit 7 Read: CH0F Write: 0 Reset: 0 TASC0 — $0013 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Register Name and Address: Bit 7 Read: CH1F Write: 0 Reset: 0 TASC1 — $0016 6 CH1IE 0 Register Name and Address: Bit 7 Read: CH2F Write: 0 Reset: 0 Read: CH3F Write: 0 Reset: 0 R 0 TASC2 — $0019 6 5 4 3 2 1 Bit 0 CH2IE MS2B MS
Timer Interface A (TIMA) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0 and TIMA channel 2 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1A pin to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TCH3A pin to general-purpose I/O. Reset clears the MSxB bit.
I/O Registers Table 16-2.
Timer Interface A (TIMA) 16.7.5 TIMA Channel Registers These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIMA channel x registers (TACHxH) inhibits input captures until the low byte (TACHxL) is read.
I/O Registers Register Name and Address: Read: Write: TACH2L — $001B Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after reset Register Name and Address: Read: Write: TACH3H — $001D Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Register Name and Address: Read: Write: Reset: TACH3L — $001E Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
Timer Interface A (TIMA) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 17 Timer Interface B (TIMB) 17.1 Introduction This section describes the timer interface module B (TIMB). The TIMB is a 2-channel timer that provides: • Timing reference with input capture • Output compare • Pulse-width modulation functions Figure 17-2 is a block diagram of the TIMB. NOTE The TIMB module is not available in the 56-pin shrink dual in-line package (SDIP). 17.
PTA PTA7–PTA0 PTB PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0 PTC PTC6 PTC5 PTC4 PTC3 PTC2 PTC1/ATD9(1) PTC0/ATD8 PTD PTD6/IS3 PTD5/IS2 PTD4/IS1 PTD3/FAULT4 PTD2/FAULT3 PTD1/FAULT2 PTD0/FAULT1 PTE CONTROL AND STATUS REGISTERS — 112 BYTES DDRA ARITHMETIC/LOGIC UNIT PTE7/TCH3A PTE6/TCH2A PTE5/TCH1A PTE4/TCH0A PTE3/TCLKA PTE2/TCH1B(1) PTE1/TCH0B(1) PTE0/TCLKB(1) LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE DDRB CPU REGISTERS USER FLASH — 32,
Functional Description TCLK PTE0/TCLKB PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL ELS0B CHANNEL 0 ELS0A TOV0 CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L CH0F ELS1B CHANNEL 1 CH0IE MS0B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L CH1F PTE2 LOGIC PTE2/TCH1B INTERRUPT LOGIC 16-BIT LATCH CH1IE MS1A PTE1/TCH0B INTERRUPT LOGIC 16-BIT LATCH MS0A PTE1 LOGIC Figure 17-2.
Timer Interface B (TIMB) Addr. Register Name Bit 7 Read: $0056 $0057 $0058 $0059 TIMB Channel 0 Status/Control Register Write: (TBSC0) See page 247. Reset: TIMB Channel 0 Register High Read: (TBCH0H) Write: See page 250. Reset: TIMB Channel 0 Register Low Read: (TBCH0L) Write: See page 250. Reset: TIMB Channel 1 Status/Control Read: Register Write: (TBSC1) See page 247. Reset: Read: $005A $005B TIMB Channel 1 Register High (TBCH1H) Write: See page 250.
Functional Description whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this value is stored in the input capture register two bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event.
Timer Interface B (TIMB) 17.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE1/TCH0B pin. The TIMB channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTE1/TCH0B pin.
Functional Description The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers produces a duty cycle of 128/256 or 50 percent. 17.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 17.3.4 Pulse-Width Modulation (PWM).
Timer Interface B (TIMB) currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 17.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b.
Interrupts 17.4 Interrupts These TIMB sources can generate interrupt requests: • TIMB overflow flag (TOF) — The timer overflow flag (TOF) bit is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit, TOIE, enables TIMB overflow interrupt requests. TOF and TOIE are in the TIMB status and control registers. • TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
Timer Interface B (TIMB) 17.7 I/O Registers These input/output (I/O) registers control and monitor TIMB operation: • TIMB status and control register (TBSC) • TIMB control registers (TBCNTH–TBCNTL) • TIMB counter modulo registers (TBMODH–TBMODL) • TIMB channel status and control registers (TBSC0 and TBSC1) • TIMB channel registers (TBCH0H–TBCH0L and TBCH1H–TBCH1L) 17.7.
I/O Registers TSTOP — TIMB Stop Bit This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit. 1 = TIMB counter stopped 0 = TIMB counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIMB is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until TSTOP is cleared.
Timer Interface B (TIMB) 17.7.2 TIMB Counter Registers The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
I/O Registers 17.7.
Timer Interface B (TIMB) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB channel 0. Setting MS0B disables the channel 1 status and control register and reverts TCH1B to general-purpose I/O. Reset clears the MSxB bit.
I/O Registers Table 17-2.
Timer Interface B (TIMB) 17.7.5 TIMB Channel Registers These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown. In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMB channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL) is read.
Chapter 18 Development Support 18.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 18.2 Break Module (BRK) The break module (BRK) can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 CONTROL BREAK 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 18-1. Break Module Block Diagram Addr. Register Name $FE00 SIM Break Status Register Read: (SBSR) Write: See page 255. Reset: $FE03 SIM Break Flag Control Read: Register (SBFCR) Write: See page 255. Reset: $FE0C Break Address Register High Read: (BRKH) Write: See page 254.
Break Module (BRK) 18.2.1.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 18.2.1.
Development Support 18.2.3.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: Read: Write: Reset: $FE0E Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 18-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7.
Monitor ROM (MON) 18.2.3.3 Break Status Register The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R BW R 0 Reset: Figure 18-6. SIM Break Status Register (SBSR) BW — Break Wait Bit This read/write bit is set when a break interrupt causes an exit from wait mode.
Development Support Features include: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • 4800 baud–28.8 Kbaud communication with host computer • Execution of code in random-access memory (RAM) or ROM • FLASH programming 18.3.1 Functional Description The monitor ROM receives and executes commands from a host computer.
Monitor ROM (MON) VDD 10 kΩ MC68HC908MR16/ MC68HC908MR32 S1 RST 0.1 µF VHI 10 kΩ IRQ VDDA 1 10 µF MC145407 VDDA 20 + + 3 18 4 17 0.1 µF 10 µF VDDAD VDDAD 0.1 µF 10 µF + 2 19 + 10 µF VREFH VDD VREFH 0.1 µF CGMXFC 0.02 µF DB-25 2 5 16 3 6 15 OSC1 X1 4.9152 MHz 20 pF 7 10 MΩ OSC2 VDD 1 MC74HC125 VREFL VSSAD VSSA PWMGND VSS 20 pF 14 2 3 6 5 VDD VDD 4 7 0.
Development Support 258 Table 18-2. Monitor Mode Signal Requirements and Options For Serial PTC2 External Bus CGMOUT (S2) Clock(1) Frequency Communication(2) RESET (S1) $FFFE /$FFFF X GND X X X X X X 0 0 Disabled VTST VDD or VTST X OFF 1 0 0 4.9152 MHz 4.9152 MHz 2.4576 MHz Disabled VTST VDD or VTST X 9.8304 MHz 4.9152 MHz 2.4576 MHz Disabled VDD VDD $FFFF Blank OFF 9.8304 MHz 4.9152 MHz 2.
Monitor ROM (MON) Enter monitor mode by either: • Executing a software interrupt instruction (SWI) or • Applying a logic 0 and then a logic 1 to the RST pin Once out of reset, the MCU waits for the host to send eight security bytes. After receiving the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate.
Development Support 18.3.1.5 Echoing As shown in Figure 18-11, the monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking. SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW ECHO DATA RESULT Figure 18-11. Read Transaction Any result of a command appears after the echo of the last byte of the command. 18.3.1.6 Break Signal A start bit followed by nine low bits is a break signal. See Figure 18-12.
Monitor ROM (MON) Table 18-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ ADDRESS HIGH READ ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA ECHO RETURN Table 18-4.
Development Support Table 18-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Single data byte Data Returned Opcode None $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 18-7.
Monitor ROM (MON) 18.3.1.8 Baud Rate With a 4.9152-MHz crystal and the PTC2 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. If the PTC2 pin is at logic 0 during reset, the monitor baud rate is 9600. See Table 18-9. Table 18-9. Monitor Baud Rate Selection VCO Frequency Multiplier (N) Monitor baud rate 1 2 3 4 5 6 4800 9600 14,400 19,200 24,000 28,800 18.3.
Development Support VDD 4096 + 32 CGMXCLK CYCLES RST 24 BUS CYCLES PA7 COMMAND BYTE 8 BYTE 2 BYTE 1 256 BUS CYCLES (MINIMUM) FROM HOST PA0 3 1 1 1 3 2 1 NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Wait 1 bit time before sending next byte. COMMAND ECHO BREAK BYTE 8 ECHO BYTE 2 ECHO BYTE 1 ECHO FROM MCU Figure 18-13. Monitor Mode Entry Timing MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Chapter 19 Electrical Specifications 19.1 Introduction This section contains electrical and timing specifications. 19.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. For guaranteed operating conditions, refer to 19.5 DC Electrical Characteristics. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.
Electrical Specifications 19.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to 85 –40 to 105 °C VDD 5.0 ± 10% V Symbol Value Unit Thermal resistance, 64-pin QFP θJA 76 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) K Average junction temperature Operating temperature range(1) MC68HC908MR24CFU MC68HC908MR24VFU Operating voltage range 1.
DC Electrical Characteristics 19.5 DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILoad = –2.0 mA) all I/O pins VOH VDD –0.8 — — V Output low voltage (ILoad = 1.6 mA) all I/O pins VOL — — 0.4 V PWM pin output source current (VOH = VDD –0.8 V) IOH –7 — — mA PWM pin output sink current (VOL = 0.8 V) IOL 20 — — mA Input high voltage, all ports, IRQs, RESET, OSC1 VIH 0.
Electrical Specifications 19.6 FLASH Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz FLASH page erase time <1 K cycles >1 K cycles tErase 0.9 3.6 1 4 1.1 5.
Serial Peripheral Interface Characteristics 19.
Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPCK, CPOL = 0 OUTPUT NOTE SPCK, CPOL = 1 OUTPUT NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 10 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SCK pin.
Serial Peripheral Interface Characteristics SS INPUT 3 1 SPCK, CPOL = 0 INPUT 11 5 4 2 SPCK, CPOL = 1 INPUT 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined, but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPCK, CPOL = 0 INPUT 5 4 2 3 SPCK, CPOL = 1 INPUT 8 MISO INPUT MOSI OUTPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1
Electrical Specifications 19.9 TImer Interface Module Characteristics Characteristic Input capture pulse width Input clock pulse width Symbol Min Max Unit tTIH, tTIL 125 — ns tTCH, tTCL (1/fOP) + 5 — ns 19.
CGM Acquisition/Lock Time Specifications 19.12 CGM Acquisition/Lock Time Specifications Description Symbol Min Typ Max Notes Filter capacitor multiply factor CFACT — 0.0154 — F/sV Acquisition mode time factor KACQ — 0.1135 — V Tracking mode time factor KTRK — 0.
Electrical Specifications 19.13 Analog-to-Digital Converter (ADC) Characteristics Characteristic Symbol Min Typ Max Unit Notes Supply voltage VDDAD 4.5 — 5.5 V VDDAD should be tied to the same potential as VDD via separate traces Input voltages VADIN 0 — VDDAD V VADIN <= VDDAD Resolution BAD 10 — 10 Bits Absolute accuracy AAD — — ±4 LSB Includes quantization ADC internal clock fADIC 500 k — 1.
Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction This section provides ordering information for the MC68HC908MR16 and MC68HC908MR32 along with the dimensions for: • 64-lead plastic quad flat pack (QFP) • 56-pin shrink dual in-line package (SDIP) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office. 20.2 Order Numbers Table 20-1.
Ordering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack (QFP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
56-Pin Shrink Dual In-Line Package (SDIP) 20.4 56-Pin Shrink Dual In-Line Package (SDIP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Ordering Information and Mechanical Specifications MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
Appendix A MC68HC908MR16 The information contained in this document pertains to the MC68HC908MR16 with the exception of that shown in Figure A-1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.
MC68HC908MR16 $0000 ↓ $005F I/O REGISTERS — 96 BYTES $0060 ↓ $035F RAM — 768 BYTES $0360 ↓ $7FFF UNIMPLEMENTED — 31,904 BYTES $8000 ↓ $BEFF FLASH — 16,128 BYTES $BF00 ↓ $FDFF UNIMPLEMENTED — 16,128 BYTES $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE04 RESERVED $FE05 RESERVED $FE06 RESERVED $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 UNIMPLEMENTED $FE0A UNIMPLEMENTED
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