Microcontrollers Data Sheet

Advance Information MC68HC(7)08KH12 — Rev. 1.1
82 Freescale Semiconductor
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-18 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
Figure 7-18. Stop Mode Entry Timing
Figure 7-19. Stop Mode Recovery from Interrupt or Break
STOP ADDR + 1 SAME SAMEIAB
IDB
PREVIOUS DATA NEXT OPCODE SAME
STOP ADDR
SAME
R/W
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
CGMXCLK
INT/BREAK
IAB
STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3
STOP +1
STOP RECOVERY PERIOD