Microcontrollers Data Sheet

Advance Information MC68HC(7)08KH12 — Rev. 1.1
178 Freescale Semiconductor
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Address: $0016 TSC0
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0
CH0MAX
Write: 0
Reset:00000000
Address: $0019 TSC1
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1
CH1MAX
Write: 0
Reset:00000000
= Unimplemented
Figure 11-6. TIM Channel Status and Control Registers (TSC0:TSC1)