Microcontrollers Data Sheet

Advance Information MC68HC(7)08KH12 — Rev. 1.1

106 Freescale Semiconductor

MUL[11:0] — Multiplier select bits

These read/write bits control the modulo feedback divider that selects

the VCO frequency multiplier N. (See 8.4.3 PLL Circuits and 8.4.6

Programming the PLL.) MUL[11:0] cannot be written when the

PLLON bit in the PCTL is set. A value of $0000 in the multiplier select

registers configures the modulo feedback divider the same as a value

of $0001. Reset initializes the registers to $002 for a default multiply

value of 2.

NOTE: The multiplier select bits have built-in protection such that they cannot

be written when the PLL is on (PLLON = 1).

8.6.4 PLL Reference Divider Select Register (PRDS)

The PLL reference divider select register contains the programming

information for the modulo reference divider.

RDS[3:0] — Reference Divider Select Bits

These read/write bits control the modulo reference divider that selects

the reference division factor R. (See 8.4.3 PLL Circuits and 8.4.6

Programming the PLL.) RDS[7:0] cannot be written when the

PLLON bit in the PCTL is set. A value of $00 in the reference divider

select register configures the reference divider the same as a value of

$01. (See 8.4.7 Special Programming Exceptions.) Reset

initializes the register to $01 for a default divide value of 1.

NOTE: The reference divider select bits have built-in protection such that they

cannot be written when the PLL is on (PLLON = 1).

Address: $003F

Bit 7654321Bit 0

RDS3 RDS2 RDS1 RDS0

Write:

Reset:00000001

= Unimplemented

Figure 8-6. PLL Reference Divider Select Register (PRDS)