Microcontrollers Data Sheet

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M68HC08

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MC68HC08KH12

Data Sheet

Rev. 1.1

MC68HC08KH12/H

July 15, 2005

Summary of content (262 pages)

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MC68HC08KH12 Data Sheet M68HC08 Microcontrollers Rev. 1.1 MC68HC08KH12/H July 15, 2005 freescale.
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Advance Information — MC68HC(7)08KH12 List of Sections Section 1. General Description ....................................... 23 Section 2. Memory Map ................................................... 33 Section 3. Random-Access Memory (RAM) ................... 45 Section 4. Read-Only Memory (ROM) ............................. 47 Section 5. Configuration Register (CONFIG) ................. 49 Section 6. Central Processor Unit (CPU) ....................... 51 Section 7. System Integration Module (SIM) ...
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Advance Information 4 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Table of Contents General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 Pin Assignments . . . . . . . . .
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2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Section 3. Random-Access Memory (RAM) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . .
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Section 7. System Integration Module (SIM) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 65 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.
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7.8.2 7.8.3 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 84 Break Flag Control Register (BFCR). . . . . . . . . . . . . . . . . . 85 Section 8. Clock Generator Module (CGM) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.
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8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.8.2 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 108 8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 108 8.9.1 Acquisition/Lock Time Definitions . . . . . . . . .
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9.5.7 9.5.8 9.5.9 USB Embedded Device Control Register 2 (DCR2) . . . . . 146 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Section 10. Monitor ROM (MON) 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.2 Introduction . . . . . . . . . . . . . . . . .
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.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.8.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 172 11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . . 173 11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .
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.8.1 12.8.2 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 202 Data Direction Register F (DDRF). . . . . . . . . . . . . . . . . . . 203 12.9 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.9.1 Port Option Control Register (POC) . . . . . . . . . . . . . . . . . 204 Section 13. Computer Operating Properly (COP) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.
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14.4.1 IRQ1/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 217 14.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 217 Section 15. Keyboard Interrupt Module (KBI) 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.
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Section 16. Break Module (BREAK) 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . 244 16.
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17.12 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . . 255 17.13 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 17.14 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 256 17.15 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 257 17.15.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .257 17.15.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 257 17.15.
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Advance Information 16 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 List of Figures Figure Page 1-1 1-2 1-3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 64-Pin QFP Assignments (Top View) . . . . . . . . . . . . . . . . . . . . 28 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .
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Figure 18 Page 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . . 81 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . . 81 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . . 82 Break Status Register (BSR) . . . . . . . . . .
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Figure Title Page 9-20 USB Embedded Device Endpoint 0 Data Register (UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10-1 10-2 10-3 10-4 10-5 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure Title Page 12-20 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 203 12-21 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12-22 Port Option Control Register (POC) . . . . . . . . . . . . . . . . . . . .204 13-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . 210 13-3 COP Control Register (COPCTL) . . . . . . .
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Advance Information — MC68HC(7)08KH12 List of Tables Table Title Page 2-1 Vector Addresses .....................................................................43 7-1 7-2 7-3 7-4 Signal Name Conventions ........................................................ 65 PIN Bit Set Timing .................................................................... 67 Interrupt Sources ...................................................................... 76 SIM Registers .............................................
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Table 12-1 12-2 12-3 12-4 12-5 12-6 12-7 Title Page I/O Port Register Summary.....................................................184 Port A Pin Functions ............................................................... 188 Port B Pin Functions ............................................................... 190 Port C Pin Functions............................................................... 192 Port D Pin Functions...............................................................
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Advance Information — MC68HC(7)08KH12 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.1 Quad Flat Pack (QFP) Package .
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1.2 Introduction The MC68HC(7)08KH12 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.
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• Full Universal Serial Bus Specification 1.1 Composite HUB with Embedded1 Functions: – 1 × 12MHz Upstream Port – 4 × 12MHz/1.5MHz Downstream Ports – 1 × Hub Control Endpoint (Endpoint0) with 8 byte transmit buffer and 8 byte receive buffer – 1 × Hub Interrupt Endpoint (Endpoint1) with 1 byte transmit buffer – 1 × Device Control Endpoint (Endpoint0) with 8 byte transmit buffer and 8 byte receive buffer – Device Interrupt Endpoints (Endpoint1 and Endpoint2) share with 8 byte transmit buffer • On-chip 3.
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Features of the CPU08 include the following: • Enhanced HC05 Programming Model • Extensive Loop Control Functions • 16 Addressing Modes (Eight More Than the HC05) • 16-Bit Index Register and Stack Pointer • Memory-to-Memory Data Transfers • Fast 8 × 8 Multiply Instruction • Fast 16/8 Divide Instruction • Binary-Coded Decimal (BCD) Instructions • Optimization for Controller Applications • Third Party C Language Support 1.
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DDRD PORT D PTD7/KBD7– PTD0/KBD0 ➄ PTB7–PTB0 ➀ VDD1 PTA7–PTA0 PORT C PORT B PORT A DDRC DDRB DDRA POWER SUPPLY AND VOLTAGE REGULATION VSS1 VDD2 VSS2 PTE4 PTE3/KBE3– PTE0/KBE0 ➀➃➅ DDRE REGOUT PORT E MC68HC(7)08KH12 — Rev. 1.
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1.5 Pin Assignments 1.5.1 Quad Flat Pack (QFP) Package RST PTF0/KBF0 PTF1/KBF1 PTF2/KBF2 PTF3/KBF3 PTF4/KBF4 PTF5/KBF5 PTF6/KBF6 PTF7/KBF7 VSS2 VDD2 PTA7 PTA6 PTA5 PTA4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 IRQ1/VPP VDDA 64 Figure 1-2 Shows the 64-pin QFP assignments.
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1.5.2 Power Supply Pins (VDDA, VSSA, VDD1, VSS1, VDD2, and VSS2) VDDA and VSSA are the analog power supply and ground pins used by the on-chip Phase-Locked Loop circuit. VDD2 and VSS2 are the power supply and ground pins used by the internal circuitry of the chip. VDD1 and VSS1 are the power supply and ground pins to the I/O pads. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply.
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1.5.3 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. (See Section 8. Clock Generator Module (CGM).) 1.5.4 External Reset Pin (RST) A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. The RST pin contains an internal pullup device. ((See Section 7. System Integration Module (SIM).) 1.5.
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1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) PTA7–PTA0 are general-purpose bidirectional I/O port pins. (See Section 12. I/O Ports.) Each pin contains a software configurable pullup device when the pin is configured as an input. (See 12.9 Port Options.) 1.5.9 Port B I/O Pins (PTB7–PTB0) PTB7–PTB0 are general-purpose bidirectional I/O port pins. (See Section 12. I/O Ports.) Each pin contains a software configurable pullup device when the pin is configured as an input. (See 12.9 Port Options.) 1.5.
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1.5.13 Port F I/O Pins (PTF7/KBF7–PTF0/KBF0) PTF7/KBF7–PTF0/KBF0 are general-purpose bidirectional I/O port pins. (See Section 12. I/O Ports.) Any or all of the port F pins can be programmed to serve as external interrupt pins. (See Section 15. Keyboard Interrupt Module (KBI).) Advance Information 32 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: MC68HC(7)08KH12 — Rev. 1.
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$0000 ↓ $005F $0060 ↓ $01DF $01E0 ↓ $CDFF $D000 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 ↓ $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 ↓ $FEFF $FF00 ↓ $FF8D ↓ $FFE5 $FFE6 ↓ $FFFF I/O REGISTERS (80 BYTES) RAM (384 BYTES) UNIMPLEMENTED (52, 256 BYTES) ROM/OTPROM (11776 BYTES) BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (RSR) RESERVED BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) RESERVED RESERVED RESERVED (4 BYTES) BREAK ADDRESS
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2.3 I/O Section Addresses $0000–$005F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: MC68HC(7)08KH12 — Rev. 1.
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Addr.
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Addr.
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Addr.
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Addr.
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Addr.
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Addr.
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Addr.
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Table 2-1 is a list of vector locations. Table 2-1.
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Advance Information 44 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.2 Introduction This section describes the 384 bytes of RAM. 3.3 Functional Description Addresses $0060 through $01DF are RAM locations. The location of the stack RAM is programmable.
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During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Advance Information 46 Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 4. Read-Only Memory (ROM) 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.2 Introduction This section describes the 11,776 bytes of read-only memory (ROM) and 26 bytes of user vectors, available on the MC68HC08KH12 device (ROM part).
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Advance Information 48 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2 Introduction This section describes the configuration register (CONFIG).
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NOTE: The CONFIG register is a special register containing one-time writable latches after each reset. Upon a reset, the CONFIG register defaults to the predetermined settings as shown in Figure 5-1. Address: Read: $001F Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 SSREC COPRS STOP COPD 0 0 0 0 = Unimplemented Figure 5-1.
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Advance Information — MC68HC(7)08KH12 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1 Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 Index Register (H:X) .
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6.
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0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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6.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
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6.4.3 Stack Pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction also sets the least significant byte to $FF but does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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6.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
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6.4.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic one. The following paragraphs describe the functions of the condition code register. Read: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X Write: Reset: X = Indeterminate Figure 6-6.
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I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically.
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C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set.
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Advance Information 60 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 65 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . .
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7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.8.1 Break Status Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . 83 7.8.2 Reset Status Register (RSR) . . . . . . . .
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MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL RESET PIN LOGIC CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU I
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Addr.
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Table 7-1 shows the internal signal names used in this section. Table 7-1. Signal Name Conventions Signal Name Description CGMXCLK Buffered OSC1 from the oscillator CGMOUT The CGMXCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks (Bus clock = CGMXCLK divided by four) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal 7.
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7.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. 7.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter.
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An internal reset clears the SIM counter (see 7.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 7.8 SIM Registers.) 7.4.1 External Pin Reset The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing.
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IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 7-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR USB INTERNAL RESET Figure 7-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 7.4.2.
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OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK CGMOUT RST $FFFE IAB $FFFF Figure 7-7. POR Recovery 7.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF.
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7.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.4.2.
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7.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescalar for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of CGMXCLK. 7.5.
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7.6 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 7.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 7-8 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing.
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FROM RESET BREAK INTERRUPT? YES NO YES II BIT BIT SET? SET? NO IRQ1 INTERRUPT? YES NO USB INTERRUPT? YES NO OTHER INTERRUPTS? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCITON? YES NO RTI INSTRUCITON? YES UNSTACK CPU REGISTERS. NO EXECUTE INSTRUCTION. Figure 7-8. Interrupt Processing MC68HC(7)08KH12 — Rev. 1.
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At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-9 shows interrupt entry timing. Figure 7-10 shows interrupt recovery timing.
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set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
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7.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 7.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
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Table 7-3. Interrupt Sources Flag Mask(1) INT Register Flag Priority(2) Vector Address Port-D Keyboard Pin Interrupt KEYDF IMASKD IF9 9 $FFEA–$FFEB Port-F Keyboard Pin Interrupt KEYFF IMASKF IF10 10 $FFE8–$FFE9 Phase-locked Loop Interrupt PLLF PLLIE IF11 11 $FFE6–$FFE7 Source (1) The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. (2) 0= highest priority 7.6.2.
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7.6.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-13. Interrupt Status Register 2 (INT2) IF11–IF7 — Interrupt Flags 11–7 These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present 7.6.2.
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7.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.6.4 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 16. Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.6.
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below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 7-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
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IAB IDB $6E0B $A6 $A6 $6E0C $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 7-16. Wait Recovery from Interrupt or Break 32 Cycles $6E0B IAB IDB $A6 $A6 32 Cycles RSTVCTH RST VCTL $A6 RST CGMXCLKCGMXCLK Figure 7-17. Wait Recovery from Internal Reset 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode.
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A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing. NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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7.8 SIM Registers The SIM has three memory mapped registers. Table 7-4 shows the mapping of these registers. Table 7-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 RSR User $FE03 BFCR User 7.8.1 Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R 1 SBSW Note 1 Reset: Bit 0 R 0 R = Reserved 1.
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; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited ; by break TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too. DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode.
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POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of RSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of RSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of RSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of RSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or rea
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BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Advance Information 86 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4.
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8.6.4 8.7 PLL Reference Divider Select Register (PRDS) . . . . . . . . 106 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.8.2 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 108 8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . .
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8.
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OSCILLATOR (OSC) OSC2 CGMXCLK OSC1 SIMOSCEN CGMRDV CGMRCLK REFERENCE DIVIDER CLOCK SELECT CIRCUIT BCS RDS[3:0] ÷2 CGMOUT R VDDA CGMXFC CLOCK SELECT CIRCUIT VSSA VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER PHASE DETECTOR USBCLK 48MHz PLL ANALOG AUTOMATIC MODE CONTROL LOCK DETECTOR LOCK MUL[11:0] CGMVDV FREQUENCY DIVIDER AUTO N ACQ INTERRUPT CONTROL PLLIE PRE[1:0] FREQUENCY DIVIDER CGMINT PLLF P CGMVCLK CGMPCLK PHASE-LOCKED LOOP (PLL) Figure 8-1.
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8.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
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The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a range from roughly 40MHz to 56MHz, fVRS. Modulating the voltage on the CGM/XFC pin changes the frequency within this range. By design, fVRS is tuned to a nominal center-of-range frequency of 48MHz. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
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8.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 8.6.2 PLL Bandwidth Control Register (PBWC).
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noise hit and the software must take appropriate action, depending on the application. (See 8.7 Interrupts for information and precautions on using interrupts.) The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (See 8.6.2 PLL Bandwidth Control Register (PBWC).) is a read-only indicator of the mode of the filter. (See 8.4.4 Acquisition and Tracking Modes.
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2. Choose a practical PLL (crystal) reference frequency, fRCLK, and the reference clock divider, R. Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
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A zero value for R or N is interpreted exactly the same as a value of one. A zero value for L disables the PLL and prevents its selection as the source for the base clock. (See 8.4.8 Base Clock Selector Circuit.) 8.4.8 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the PLL clock, CGMPCLK, as the source of the base clock, CGMOUT.
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• Tuning capacitor, C2 (can also be a fixed capacitor) • Feedback resistor, RB • Series resistor, RS (optional) The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.
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8.5 I/O Signals The following paragraphs describe the CGM I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 8.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 8.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
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8.5.6 Buffered Crystal Clock Output (CGMVOUT) CGMVOUT buffers the OSC1 clock for external use. 8.5.7 CGMVSEL CGMVSEL must be tied low or floated. 8.5.8 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. 8.5.9 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
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8.6 CGM Registers These registers control and monitor operation of the CGM: • PLL control register (PCTL) (See 8.6.1 PLL Control Register (PCTL).) • PLL bandwidth control register (PBWC) (See 8.6.2 PLL Bandwidth Control Register (PBWC).) • PLL multiplier select registers (PMSH:PMSL) (See 8.6.3 PLL Multiplier Select Registers (PMSH:PMSL).) • PLL reference divider select register (PRDS) (See 8.6.4 PLL Reference Divider Select Register (PRDS).) Table 8-2 is a summary of the CGM registers.
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Table 8-2. CGM I/O Register Summary Addr.
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8.6.1 PLL Control Register (PCTL) The PLL control register contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power of two range selector bits. Address: $003A Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 0 5 4 3 2 PLLON BCS PRE1 PRE2 1 0 1 0 1 Bit 0 0 0 0 0 = Unimplemented Figure 8-3.
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PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 8.4.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS — Base Clock Select Bit This read/write bit selects either the crystal oscillator clock (CGMXCLK) or the VCO clocks (CGMPCLK and CGMVCLK) to use as base clocks for the MCU.
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Table 8-3. PRE[1:0] Programming PRE1 PRE0 P Prescaler Multiplier 0 0 0 1 0 1 1 2 1 0 2 4 1 1 3 8 8.6.2 PLL Bandwidth Control Register (PBWC) The PLL bandwidth control register: • Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode Address: $003B Bit 7 Read: Write: Reset: AUTO 0 6 LOCK 0 5 ACQ 0 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 8-4.
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logic zero and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a zero. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode.
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MUL[11:0] — Multiplier select bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N. (See 8.4.3 PLL Circuits and 8.4.6 Programming the PLL.) MUL[11:0] cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $002 for a default multiply value of 2.
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8.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic zero.
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8.8.2 CGM During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR).) To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit.
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Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered.
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The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections.
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8.9.3 Choosing a Filter Capacitor As described in 8.9.2 Parametric Influences on Reaction Time, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind.
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an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. V DDA 8 t ACQ =  -------------  -------------  f RDV   K ACQ V DDA 4 t AL =  -------------  ------------  f RDV   K TRK t LOCKMAX = t ACQ + t AL + 256t VRDV NOTE: The inverse proportionality between the lock time and the reference frequency. In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See 8.4.
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Advance Information — MC68HC(7)08KH12 Section 9. Universal Serial Bus Module (USB) 9.1 Contents 9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.4 I/O Register Description of the HUB function . . . . . . . . . . . . . 116 9.4.1 USB HUB Root Port Control Register (HRPCR) . . . . . . . . 120 9.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR) . .
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9.2 Features Features of the general USB Module include the following: • Integrated 3.3 Volt Regulator with 3.
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Features of the embedded device function include the following: • Device Control Endpoint 0 and Interrupt Endpoints 1 and 2 – 8-byte transmit buffer – 8-byte receive buffer • Device Interrupt Endpoints 1 and 2 – 8-byte transmit buffer • USB generated interrupts – transaction interrupt driven 9.3 Overview This section provides an overview of the Universal Serial Bus (USB) module developed for the MC68HC(7)08KH12.
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USBCLK (FROM CGM) 48MHz ENDPOINT 0 - 8/8 B (CONTROL) ROOR PORT SERIAL INTERFACE ENGINE TRANSCEIVER D0+ LOGIC HUB CONTROL ENDPOINT 1 - 1 B (INTERRUPT) 12MHz PORTS COUNTER FRAME LOGIC CONTROL EMBEDDED DEVICE REGISTERS DOWNSTREAM CPU BUS TRANSCEIVER HUB REPEATER D0– D1+ : D4+ D1– : D4– ENDPOINT 0 - 8/8 (CONTROL) ENDPOINT 1/2 - 8 B (TRANSMIT ONLY, INTERRUPT/BULK) REGULATOR 3.3V OUT Figure 9-1. USB Block Diagram 9.
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Table 9-1. HUB Control Register Summary Addr.
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Read: $005A Unimplemented Write: Reset: $005B $005C $005D $005E USB HUB Control Register 0 (HCR0) USB HUB Endpoint 1 Control and Data Register (HCDR) USB HUB Status Register (HSR) USB HUB Root Port Control Register (HRPCR) Read: TSEQ STALL0 TXE RXE TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0 0 0 0 0 0 0 0 0 STALL1 PNEW PCHG5 PCHG4 PCHG3 PCHG2 PCHG1 PCHG0 Reset: 0 0 0 0 0 0 0 0 Read: RSEQ SETUP TX1ST 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 X X X X 0 D0+ D0– 0 X X Write:
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Table 9-2. HUB Data Register Summary Addr. $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 Register Name USB HUB Endpoint 0 Data Register 0 (HE0D0) USB HUB Endpoint 0 Data Register 1 (HE0D1) USB HUB Endpoint 0 Data Register 2 (HE0D2) USB HUB Endpoint 0 Data Register 3 (HE0D3) USB HUB Endpoint 0 Data Register 4 (HE0D4) USB HUB Endpoint 0 Data Register 5 (HE0D5) USB HUB Endpoint 0 Data Register 6 (HE0D6) USB HUB Endpoint 0 Data Register 7 (HE0D7) MC68HC(7)08KH12 — Rev. 1.
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9.4.1 USB HUB Root Port Control Register (HRPCR) Address: Read: $005E Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 3 RESUM0 SUSPND 0 = Unimplemented 0 2 1 Bit 0 0 D0+ D0– 0 X X X = Indeterminate Figure 9-2. USB HUB Root Port Control Register (HRPCR) RESUM0 — Force Resume to the Root Port This read/write bit forces a resume signal (“K” state) onto the USB root port data lines to initiate a remote wakeup.
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EOF2 is generated by KH12 every millisecond, if SOF is not detected when three or more EOF2 has occurred, software can set the SUSPND-bit and put KH12 into suspend mode. D0+/D0– — Root Port Differential Data These read only bits are the differential data shown on the HUB root ports. When the bit SUSPND is 0, the data is the latched state at the last EOF2 sample point. When the bit SUSPND is 1, the data reflects the current state on the data line while accessing this register. 9.4.
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bit can be set to 1 by the host request only. It can be cleared either by hardware when a fault condition was detected or by software through the host request. Reset clears this bit. 1 = Downstream port is enabled 0 = Downstream port is disabled LOWSP1-LOWSP4 — Full Speed / Low Speed Port Control Bit This read/write bit specifies the attached device in the downstream port is low speed device or full speed device.
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SUSP1-SUSP4 — Downstream Port Selective Suspend Bit This read/write bit forces the downstream port entering the selective suspend mode. This bit can be set by the host request SetPortFeature (PORT_SUSPEND) only. When this bit is set, the hub prevents propagating any bus activity (except the port reset or port resume request or the global reset signal) downstream, and the port can only reflect upstream bus state changes via the endpoint 1 of the hub.
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SOFF — Start Of Frame Detect Flag This read only bit is set when a valid SOF PID is detected on the D0+ and D0– lines at the root port. Software must clear this flag by writing a logic 1 to SOFFR bit in the SIETSR register. Reset clears this bit. Writing to SOFF has no effect.
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SOFIE — Start Of Frame Interrupt Enable This read/write bit enables the Start Of Frame to generate a USB interrupt when the SOFF bit becomes set. Reset clears this bit. 1 = USB interrupt enabled for Start Of Frame 0 = USB interrupt disabled for Start Of Frame EOF2IE — The Second End of Frame Point Interrupt Enable This read/write bit enables the Second End Of Frame to generate a USB interrupt when the EOF2F bit becomes set. Reset clears this bit.
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RSTF — USB Reset Flag This read only bit is set when a valid reset signal state is detected on the D0+ and D0- lines. This reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. This bit is cleared by writing a logic 1 to the RSTFR bit. NOTE: ** Please note RSTF bit is only be reset by a POR reset. RSTFR — Clear Reset Indicator Bit Writing a logic 1 to this write only bit will clear the RSTF bit if it is set.
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9.4.5 USB HUB Address Register (HADDR) Address: Read: Write: Reset: $0058 Bit 7 6 5 4 3 2 1 Bit 0 USBEN ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0** 0 0 0 0 0 0 0 0** = Reset by POR only Figure 9-6. USB HUB Address Register (HADDR) USBEN — USB Module Enable This read/write bit enables and disables the USB module. When USBEN is cleared, the USB module will not respond to any tokens and the external regulated output REGOUT will be turned off.
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9.4.6 USB HUB Interrupt Register 0 (HIR0) Address: Read: $0059 Bit 7 6 5 4 TXDF RXDF 0 0 Write: Reset: 0 0 0 0 3 2 TXDIE RXDIE 0 0 1 Bit 0 0 0 TXDFR RXDFR 0 0 = Unimplemented Figure 9-7. USB HUB Interrupt Register 0 (HIR0) TXDF — HUB Endpoint 0 Data Transmit Flag This read only bit is set after the data stored in HUB Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received.
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TXDIE — HUB Endpoint 0 Transmit Interrupt Enable This read/write bit enables the Transmit HUB Endpoint 0 to generate CPU interrupt requests when the TXDF bit becomes set. Reset clears the TXDIE bit. 1 = USB interrupt enabled for Transmit HUB Endpoint 0 0 = USB interrupt disabled for Transmit HUB Endpoint 0 RXDIE — HUB Endpoint 0 Receive Interrupt Enable This read/write bit enables the Receive HUB Endpoint 0 to generate CPU interrupt requests when the RXDF bit becomes set. Reset clears the RXDIE bit.
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TSEQ — HUB Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at Endpoint 0. Toggling of this bit must be controlled by software. Reset clears this bit.
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TPSIZ3-TPSIZ0 — HUB Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for HUB Endpoint 0. These bits are cleared by reset. 9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR) Address: Read: Write: Reset: $005C Bit 7 6 5 4 3 2 1 Bit 0 STALL1 PNEW PCHG5 PCHG4 PCHG3 PCHG2 PCHG1 PCHG0 0 0 0 0 0 0 0 0 Figure 9-9.
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PCHG5-PCHG0 — HUB and Port Status Change Bits These read/write bits report the status change for the Hub, embedded device and the four downstream ports. The Status Change Bitmap is returned to the host through the HUB endpoint 1 if the bit PNEW is 1. These bits are cleared by reset.
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RSEQ — HUB Endpoint 0 Receive Sequence Bit This read only bit indicates the type of data packet last received for HUB Endpoint 0 (DATA0 or DATA1). 1 = DATA1 Token received in last HUB Endpoint 0 Receive 0 = DATA0 Token received in last HUB Endpoint 0 Receive SETUP — HUB SETUP Token Detect Bit This read only bit indicates that a valid SETUP token has been received.
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9.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7) Address: $0030 Bit 7 6 5 4 3 2 1 Bit 0 Read: HE0R07 HE0R06 HE0R05 HE0R04 HE0R03 HE0R02 HE0R01 HE0R00 Write: HE0T07 HE0T06 HE0T05 HE0T04 HE0T03 HE0T02 HE0T01 HE0T00 X X X X X X X Reset: X ↓ ↓ Address: $0037 Read: HE0R77 HE0R76 HE0R75 HE0R74 HE0R73 HE0R72 HE0R71 HE0R70 Write: HE0T77 HE0T76 HE0T75 HE0T74 HE0T73 HE0T72 HE0T71 HE0T70 X X X X X X X Reset: X X = Indeterminate Figure 9-11.
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Table 9-3. Embedded Device Control Register Summary Addr.
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Table 9-4. Embedded Device Data Register Summary Addr.
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$0028 $0029 $002A $002B $002C $002D $002E $002F USB Embedded Device Endpoint 1/2 Data Register 0 (DE1D0) USB Embedded Device Endpoint 1/2 Data Register 1 (DE1D1) USB Embedded Device Endpoint 1/2 Data Register 2 (DE1D2) USB Embedded Device Endpoint 1/2 Data Register 3 (DE1D3) USB Embedded Device Endpoint 1/2 Data Register 4 (DE1D4) USB Embedded Device Endpoint 1/2 Data Register 5 (DE1D5) USB Embedded Device Endpoint 1/2 Data Register 6 (DE1D6) USB Embedded Device Endpoint 1/2 Data Regis
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9.5.1 USB Embedded Device Address Register (DADDR) Address: Read: Write: Reset: $0048 Bit 7 6 5 4 3 2 1 Bit 0 DEVEN DADD6 DADD5 DADD4 DADD3 DADD2 DADD1 DADD0 0 0 0 0 0 0 0 0 Figure 9-12. USB Embedded Device Address Register (DADDR) DEVEN — Enable USB Embedded Device These bit enable or disable the embedded device function. It is used together with PEN1-PEN4 to control the enumeration sequence. Reset clears these bits.
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TXD0F — Embedded Device Endpoint 0 Data Transmit Flag This read only bit is set after the data stored in embedded device Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction.
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1 = Receive Embedded Device Endpoint 0 can generate a CPU interrupt request 0 = Receive Embedded Device Endpoint 0 cannot generate a CPU interrupt request TXD0FR — Embedded Device Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set. Writing a logic 0 to TXD0FR has no effect. Reset clears this bit. RXD0FR — Embedded Device Endpoint 0 Receive Flag Reset Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.
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1 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has occurred 0 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device has not occurred TXD1IE — Embedded Device Endpoint 1/2 Transmit Interrupt Enable This read/write bit enables the USB to generate CPU interrupt requests when the shared Transmit Endpoint 1/2 interrupt flag bit of the embedded device (TXD1F) becomes set. Reset clears the TXD1IE bit.
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1 = DATA1 Token active for next embedded device Endpoint 0 transmit 0 = DATA0 Token active for next embedded device Endpoint 0 transmit DSTALL0 — Embedded Device Endpoint 0 Force Stall Bit This read/write bit causes embedded device Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the host. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit.
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TP0SIZ3-TP0SIZ0 — Embedded Device Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for embedded device Endpoint 0. These bits are cleared by reset. 9.5.5 USB Embedded Device Control Register 1 (DCR1) Address: Read: Write: Reset: $004C Bit 7 6 5 T1SEQ ENDADD TX1E 0 0 0 4 0 0 3 2 1 Bit 0 TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 0 0 0 0 = Unimplemented Figure 9-16.
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1 = The data buffers are used for embedded device Endpoint 2 0 = The data buffers are used for embedded device Endpoint 1 TX1E — Embedded Device Endpoint 1/2 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to Endpoint 1 or Endpoint 2 of the embedded device. The appropriate endpoint enable bit, ENABLE1 or ENABLE2 bit in the DCR2 register, should also be set. Software should set the TX1E bit when data is ready to be transmitted.
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DRSEQ — Embedded Device Endpoint 0 Receive Sequence Bit This read only bit indicates the type of data packet last received for embedded device Endpoint 0 (DATA0 or DATA1). 1 = DATA1 Token received in last embedded device Endpoint 0 receive 0 = DATA0 Token received in last embedded device Endpoint 0 receive DSETUP — Embedded Device SETUP Token Detect Bit This read only bit indicates that a valid SETUP token has been received.
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9.5.7 USB Embedded Device Control Register 2 (DCR2) Address: Read: $0047 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 ENABLE2 ENABLE1 DSTALL2 DSTALL1 0 0 0 0 = Unimplemented Figure 9-18. USB Embedded Device Control Register 2 (DCR2) ENABLE2 — Embedded Device Endpoint 2 Enable This read/write bit enables embedded device Endpoint 2 and allows the USB to respond to IN packets addressed to this endpoint. Reset clears this bit.
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DSTALL1 — Embedded Device Endpoint 1 Force Stall Bit This read/write bit causes embedded device Endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default 9.5.
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9.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7) Address: $0028 Bit 7 6 5 4 3 2 1 Bit 0 DE1T06 DE1T05 DE1T04 DE1T03 DE1T02 DE1T01 DE1T00 X X X X X X X Read: Write: DE1T07 Reset: X ↓ ↓ Address: $002F Read: Write: DE1T77 Reset: X DE1T76 DE1T75 DE1T74 DE1T73 DE1T72 DE1T71 DE1T70 X X X X X X X = Unimplemented X = Indeterminate Figure 9-20.
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Advance Information — MC68HC(7)08KH12 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.4.2 Data Format . . . . . . . . . . . . . .
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10.3 Features Features of the monitor ROM include the following: • Normal User-Mode Pin Functionality • One Pin Dedicated to Serial Communication between Monitor ROM and Host Computer • Standard Mark/Space Non-Return-to-Zero (NRZ) Communication with Host Computer • 4800 Baud to 28.8 kBaud Communication with Host Computer • Execution of Code in RAM or ROM • OTPROM Programming 10.4 Functional Description The monitor ROM receives and executes commands from a host computer.
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VDD 10 kΩ 68HC708 RST 0.1µF VDD + VHI 10 Ω IRQ1/VPP VDD 1 10µF + MC145407 3 4 10µF + 2 VDDA 0.1µF 20 + 10µF 18 OSC1 17 19 DB-25 2 5 16 3 6 15 20pF + 10µF VDD X1 4.9152MHz 10MΩ OSC2 20pF VSS2 VSS1 VSSA VDD VDD1 7 VDD2 VDD 1 MC74HC125 14 2 3 6 5 4 7 VDD 10kΩ PA0 VDD 10kΩ A NOTES: Position A — Bus clock = CGMXCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 0.1µF (See NOTE.) B PC3 VDD 10kΩ PC0 PC1 PA7 Figure 10-1. Monitor Mode Circuit MC68HC(7)08KH12 — Rev. 1.
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10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. IRQ1/VPP Pin PC0 Pin PC1 Pin PA0 Pin PC3 Pin Table 10-1. Mode Selection Mode VDD + VHI 1 0 1 1 Monitor CGMXCLK ÷ 2 CGMOUT ÷ 2 VDD + VHI 1 0 1 0 Monitor CGMXCLK CGMOUT ÷ 2 CGMOUT Bus Frequency If PTC3 is low upon monitor mode entry, CGMOUT is equal to the crystal frequency. The bus frequency in this case is a divide-by-two of the input clock.
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When the host computer has completed downloading code into the MCU RAM, This code can be executed by driving PTA0 low while asserting RST low and then high. The internal monitor ROM firmware will interpret the low on PTA0 as an indication to jump to RAM, and execution control will then continue from RAM. Execution of an SWI from the downloaded code will return program control to the internal monitor ROM firmware.
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10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 10-2 and Figure 10-3.) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT BIT 7 NEXT START BIT Figure 10-2. Monitor Data Format $A5 START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BREAK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT STOP BIT NEXT START BIT NEXT START BIT Figure 10-3.
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10.4.4 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 10-5.) When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 10-5. Break Transaction 10.4.5 Commands The monitor ROM uses the following commands: MC68HC(7)08KH12 — Rev. 1.
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Table 10-3. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA ECHO RESULT Table 10-4.
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Table 10-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA RESULT ECHO Table 10-6.
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NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. Table 10-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW RESULT ECHO Table 10-8.
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10.4.6 Baud Rate The communication baud rate is controlled by crystal frequency and the state of the PTC3 pin upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the PTC3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 10-9. Monitor Baud Rate Selection MC68HC(7)08KH12 — Rev. 1.1 Freescale Semiconductor Crystal Frequency (MHz) PTC3 pin Baud Rate 4.9152MHz 0 9600 bps 4.
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Advance Information 160 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 11.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.4.2 Input Capture. . . . . . . .
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11.2 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIM. 11.
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11.4 Functional Description Figure 11-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
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Table 11-1. TIM I/O Register Summary Addr.
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$001A $001B TIM Channel 1 Register High (TCH1H) TIM Channel 1 Register Low (TCH1L) Read: Write: Reset: Read: Write: Reset: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 X X X X X X X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X X X X X X X = Unimplemented X = Indeterminate 11.4.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates from the internal bus clock.
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11.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
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channel 0 registers initially controls the output on the PTE1/TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused.
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OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH PTEx/TCHxA OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 11-2. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 11.9.
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write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse.
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control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. 11.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1.
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Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect.
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If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 11.7 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR).
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minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------- + t SU bus frequency The maximum TCLK frequency is: bus frequency ------------------------------------2 PTE0/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE0 bit in data direction register E. 11.8.
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• Resets the TIM counter • Prescales the TIM counter clock Address: $0010 Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 11-3. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter resets to $0000 after reaching the modulo value programmed in the TIM counter modulo registers.
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NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic zero. Reset clears the TRST bit.
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TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
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Address: Read: Write: Reset: Address: Read: Write: Reset: $0014 TMODH Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 $0015 TMODL Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 Figure 11-5. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. 11.9.
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Address: $0016 TSC0 Bit 7 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Read: CH0F Write: 0 Reset: 0 0 $0019 TSC1 Bit 7 6 Address: Read: CH1F Write: 0 Reset: 0 CH1IE 0 0 0 = Unimplemented Figure 11-6.
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MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit.
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Table 11-3.
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OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD PTEx/TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 11-7. CHxMAX Latency 11.9.5 TIM Channel Registers (TCH0H/L–TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown.
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Address: Read: Write: $0017 TCH0H Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Address: Read: Write: Indeterminate after reset $0018 TCH0L Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: Address: Read: Write: Indeterminate after reset $001A TCH1H Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Address: Read: Write: Reset: Indeterminate after reset $001B TCH
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Advance Information — MC68HC(7)08KH12 Section 12. I/O Ports 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 186 12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . 186 12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12.2 Introduction Forty-two bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Table 12-1. I/O Port Register Summary Addr.
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Read: $0007 $0008 Data Direction Register D (DDRD) Port E Data Register (PTE) DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 PTE4 PTE3 PTE2 PTE1 PTE0 PTF2 PTF1 PTF0 Write: Write: Reset: Read: $0009 Port F Data Register (PTF) Write: Unaffected by reset PTF7 PTF6 PTF5 Reset: Read: $000A Data Direction Register E (DDRE) $001C $001D Port Option Control Register (POC) 0 0 0 0 DDRF7 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0
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12.3 Port A Port A is an 8-bit general-purpose bidirectional I/O port with software configurable pullups. 12.3.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins. Address: Read: Write: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Reset: Unaffected by reset Figure 12-1. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable.
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Address: Read: Write: Reset: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Figure 12-2. Data Direction Register A (DDRA) DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs.
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Table 12-2. Port A Pin Functions DDRA Bit PTA Bit Accesses to DDRA I/O Pin Mode Accesses to PTA Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRA[7:0] Pin PTA[7:0](3) 1 X Output DDRA[7:0] PTA[7:0] PTA[7:0] 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. 12.4 Port B Port B is an 8-bit general-purpose bidirectional I/O port with software configurable pullups. 12.4.
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12.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-5.
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When bit DDRBx is a logic one, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins. Table 12-3.
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PTC[4:0] — Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. The port C pullup enable bit, PCP, in the port option control register (POC) enables pullups on port C pins if the respective pin is configured as an input. (See 12.9 Port Options.
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READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) RESET WRITE PTC ($0002) DDRCx PTCx PTCx READ PTC ($0002) Figure 12-9. Port C I/O Circuit When bit DDRCx is a logic one, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic zero, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins. Table 12-4.
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12.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: Read: Write: $0003 Bit 7 6 5 4 3 2 1 Bit 0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 KBD2 KBD1 KBD0 Reset: Alternate Function: Unaffected by reset KBD7 KBD6 KBD5 KBD4 KBD3 Figure 12-10. Port D Data Register (PTD) PTD[7:0] — Port D Data Bits These read/write bits are software programmable.
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Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 12-11. Data Direction Register D (DDRD) DDRD[7:0] — Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs.
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Table 12-5. Port D Pin Functions DDRD Bit PTD Bit Accesses to DDRD I/O Pin Mode Accesses to PTD Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRD[7:0] Pin PTD[7:0](3) 1 X Output DDRD[7:0] PTD[7:0] PTD[7:0] 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. 12.
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PTE[4:0] — Port E Data Bits PTE[4:0] are read/write, software-programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. TCH1-TCH0 — Timer Channel I/O Bits The PTE2/TCH1-PTE1/TCH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTE2/TCH1–PTE1/TCH0 pins are timer channel I/O pins or general-purpose I/O pins. See Section 11. Timer Interface Module (TIM).
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Address: Read: $000A Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 3 2 1 Bit 0 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 = Unimplemented Figure 12-14. Data Direction Register E (DDRE) DDRE[4:0] — Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[4:0], configuring all port E pins as inputs.
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Table 12-6. Port E Pin Functions DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Accesses to PTE Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRE[4:0] Pin PTE[4:0](3) 1 X Output DDRE[4:0] PTE[4:0] PTE[4:0] 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. 12.7.3 Port-E Optical Interface Enable Register Port E pins PTE3–PTE0, each has an optical coupling interface circuit which is specially built for optical mouse application.
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XREF2–XREF0 — Reference Voltage Selection X These bits sets the slicing reference voltage for optical interface associated with PTE0 and PTE1. YREF2–YREF0 — Reference Voltage Selection Y These bits sets the slicing reference voltage for optical interface associated with PTE2 and PTE3. MC68HC(7)08KH12 — Rev. 1.
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Y-VREF X - REFERENCE VOLTAGE SELECTOR X-VREF VOLTAGE DIVIDER ENABLE YREF2 YREF1 YREF0 XREF2 XREF1 XREF0 OIEY Y - REFERENCE VOLTAGE SELECTOR OIEX OPTICAL INTERFACE REGISTER ($001C) Figure 12-17. Optical Interface Voltage References Advance Information 200 MC68HC(7)08KH12 — Rev. 1.
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OUTPUT BUFFER 0 PTE0 MUX OPTICAL INTERFACE PTE0 PORT LOGIC 1 SELECT X-VREF OIEX (BIT0 OF $1C) OPTICAL INTERFACE SELECT 1 PTE1 MUX PTE1 PORT LOGIC MUX PTE2 PORT LOGIC 0 INTERNAL DATA BUS OUTPUT BUFFER OUTPUT BUFFER 0 PTE2 OPTICAL INTERFACE 1 SELECT Y-VREF OIEY (BIT1 OF $1C) OPTICAL INTERFACE SELECT 1 PTE3 MUX PTE3 PORT LOGIC 0 OUTPUT BUFFER Figure 12-18. Port E Optical Coupling Interface MC68HC(7)08KH12 — Rev. 1.
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12.8 Port F Port F is an 8-bit general-purpose bidirectional I/O port that shares its pins with the keyboard interrupt module (KBI). All Port F pins have builtin schmitt triggered input and software configurable pull-up. 12.8.1 Port F Data Register (PTF) The port F data register contains a data latch for each of the eight port F pins.
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12.8.2 Data Direction Register F (DDRF) Data direction register F determines whether each port F pin is an input or an output. Writing a logic one to a DDRF bit enables the output buffer for the corresponding port F pin; a logic zero disables the output buffer. Address: Read: Write: Reset: $000B Bit 7 6 5 4 3 2 1 Bit 0 DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 0 Figure 12-20.
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When bit DDRFx is a logic one, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic zero, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-7 summarizes the operation of the port F pins. Table 12-7.
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LDD — LED Direct Drive Control This read/write bit controls the output current capability of port C. When set, the port C pins have current limiting ability so that a LED can be connected directly between the port pin and VDD or VSS without the need of a series resistor.
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Advance Information 206 MC68HC(7)08KH12 — Rev. 1.
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Advance Information — MC68HC(7)08KH12 Section 13. Computer Operating Properly (COP) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.4.1 CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.4.2 COPCTL Write . . . .
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13.3 Functional Description Figure 13-1 shows the structure of the COP module. RESET CIRCUIT CLEAR STAGES 5–12 RESET STATUS REGISTER COP TIMEOUT STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH CLEAR ALL STAGES 12-BIT SIM COUNTER CGMXCLK COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG) RESET CLEAR COP COUNTER COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG) Figure 13-1. COP Block Diagram Table 13-1. COP I/O Port Register Summary Addr.
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The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 – 24 or 213 – 24 CGMXCLK cycles, depending on the setting of the COP rate select bit, COPRS, in the configuration register. With a 218 – 24 CGMXCLK cycle overflow option, a 6MHz crystal gives a COP timeout period of 43.688ms.
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13.4.3 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after power-up. 13.4.4 Internal Reset An internal reset clears the SIM counter and the COP counter. 13.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. 13.4.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). (See Figure 13-2 .
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COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP reset cycle is (213 –24)×CGMXCLK 0 = COP reset cycle is (218 –24)×CGMXCLK COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled 13.5 COP Control Register (COPCTL) The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period.
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13.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 13.8.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 13.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
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Advance Information — MC68HC(7)08KH12 Section 14. External Interrupt (IRQ) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 14.4.1 IRQ1/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.
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14.4 Functional Description A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 14-1 shows the structure of the IRQ module. Interrupt signals on the IRQ1/VPP pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch.
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INTERNAL ADDRESS BUS ACK1 RESET TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD VDD INTERNAL IRQF1 PULLUP DEVICE D CLR Q CK IRQ1/VPP SYNCHRONIZER IRQ1 INTERRUPT REQUEST HIGH VOLTAGE DETECT TO MODE SELECT LOGIC IRQ1 FF IMASK1 MODE1 Figure 14-1. IRQ Module Block Diagram Table 14-1. IRQ I/O Port Register Summary Addr.
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• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ1/VPP pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise.
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14.5 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 7. System Integration Module (SIM).) To allow software to clear the IRQ1 latch during a break interrupt, write a logic one to the BCFE bit.
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IRQF1 — IRQ1 Flag This read-only status bit is high when the IRQ1 interrupt is pending. 1 = IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic one to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic zero. Reset clears ACK1. IMASK1 — IRQ1 Interrupt Mask Bit Writing a logic one to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
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Advance Information — MC68HC(7)08KH12 Section 15. Keyboard Interrupt Module (KBI) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.4 Port-D Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . 222 15.4.1 Port-D Keyboard Interrupt Functional Description. . . . . . . 223 15.4.2 Port-D Keyboard Initialization . . . . . . . . . . .
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15.2 Introduction The keyboard module provides twenty independently maskable external interrupts which are accessible via PTD7-PTD0, PTE3-PTE0 and PTF7-PTF0. Though the functionality of the three keyboard interrupts on the three ports is similar, the implementation is quite different. On port-D, enabling keyboard interrupt on a pin also enables its internal pull-up device. On port-E, the pull-up device is control by the PEPEx bit resided in the Port-E Keyboard Interrupt Enable Register (KBEIER).
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Table 15-1. KBI I/O Register Summary Addr.
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Advance Information 222 15.4 Port-D Keyboard Interrupt Block Diagram INTERNAL BUS KBD0 ACKD VDD . TO PULLUP ENABLE KBDIE0 D . CLR VECTOR FETCH DECODER KEYDF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBD7 IMASKD MODED TO PULLUP ENABLE KBDIE7 MC68HC(7)08KH12 — Rev. 1.1 Freescale Semiconductor Figure 15-1.
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15.4.1 Port-D Keyboard Interrupt Functional Description Writing to the KBDIE7–KBDIE0 bits in the keyboard interrupt enable register independently enables or disables each port D pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port-D also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high.
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• Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODED bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODED clear, a vector fetch or software clear immediately clears the keyboard interrupt request.
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3. Write to the ACKD bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKD bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt for port-D: 1.
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KEYDF — Port-D Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port-D. Reset clears the KEYDF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKD — Port-D Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-D. ACKD always reads as logic 0. Reset clears ACKD.
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KBDIE7–KBDIE0 — Port-D Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-D to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBDx pin enabled as keyboard interrupt pin 0 = KBDx pin not enabled as keyboard interrupt pin MC68HC(7)08KH12 — Rev. 1.
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Advance Information 228 15.5 Port-E Keyboard Interrupt Block Diagram INTERNAL BUS KBE0 ACKE VDD . KBEIE0 TO PULLUP ENABLE PEPE0 D . CLR VECTOR FETCH DECODER KEYEF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBE3 IMASKE MODEE KBEIE3 TO PULLUP ENABLE PEPE3 MC68HC(7)08KH12 — Rev. 1.1 Freescale Semiconductor Figure 15-4.
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15.5.1 Port-E Keyboard Interrupt Functional Description Writing to the KBEIE3–KBEIE0 bits in the keyboard interrupt enable register independently enables or disables each port E pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port-E does not enable its internal pullup device. Writing to the PEPE3–PEPE0 bits in the keyboard interrupt enable register independently enables or disables each port E pin pull-up device.
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• Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEE bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEE clear, a vector fetch or software clear immediately clears the keyboard interrupt request.
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4. Write to the ACKE bit in the keyboard status and control register to clear any false interrupts. 5. Clear the IMASKE bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. 15.5.3 Port-E Keyboard Interrupt Registers 15.5.3.1 Port-E Keyboard Status and Control Register • Flags keyboard interrupt requests.
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ACKE — Port-E Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-E. ACKE always reads as logic 0. Reset clears ACKE. IMASKE — Port-E Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-E. Reset clears the IMASKE bit.
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KBEIE3–KBEIE0 — Port-E Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-D to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBEx pin enabled as keyboard interrupt pin 0 = KBEDx pin not enabled as keyboard interrupt pin MC68HC(7)08KH12 — Rev. 1.
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Advance Information 234 15.6 Port-F Keyboard Interrupt Block Diagram INTERNAL BUS KBF0 ACKF VDD . KBFIE0 TO PULLUP ENABLE PFPE0 D . CLR VECTOR FETCH DECODER KEYFF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBF3 IMASKF MODEF KBFIE7 TO PULLUP ENABLE PFPE7 MC68HC(7)08KH12 — Rev. 1.1 Freescale Semiconductor Figure 15-7.
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15.6.1 Port-F Keyboard Interrupt Functional Description Writing to the KBFIE7–KBFIE0 bits in the keyboard interrupt enable register independently enables or disables each port F pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port-F does not enable its internal pullup device. Writing to the PFPE7–PFPE0 bits in the pull-up enable register independently enables or disables each port F pin pull-up device.
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• Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEF bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEF clear, a vector fetch or software clear immediately clears the keyboard interrupt request.
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4. Write to the ACKF bit in the keyboard status and control register to clear any false interrupts. 5. Clear the IMASKF bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. 15.6.3 Port-F Keyboard Interrupt Registers 15.6.3.1 Port-F Keyboard Status and Control Register • Flags keyboard interrupt requests.
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ACKF — Port-F Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-F. ACKF always reads as logic 0. Reset clears ACKF. IMASKF — Port-F Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-F. Reset clears the IMASKF bit.
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15.6.3.3 Port-F Pull-up Enable Register The pulll-up enable register enables or disables the pull-up device for port F. Address: $0042 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PFPE7 PFPE6 PFPE5 PFPE4 PFPE3 PFPE2 PFPE1 PFPE0 1 1 1 1 1 1 1 1 Figure 15-10. Port F Pull-up Enable Register (PFPER) PFPE7–PFPE0 — Port F pull-up enable bits These read/write bits enable/disable the pull-up device. Reset sets DDRF7–DDRF0 to ‘1’s, enabling all port F pull-up devices.
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the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit.
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Advance Information — MC68HC(7)08KH12 Section 16. Break Module (BREAK) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . 244 16.4.2 CPU During Break Interrupts. . . . . . . . .
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16.3 Features Features of the break module include the following: • Accessible I/O Registers during the Break Interrupt • CPU-Generated Break Interrupts • Software-Generated Break Interrupts • COP Disabling during Break Interrupts 16.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM.
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IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 16-1. Break Module Block Diagram Table 16-1. Break I/O Register Summary Addr.
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16.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR) and see the Break Interrupts subsection for each module.) 16.4.
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16.5.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. Address: $FE0E Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 16-2. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit.
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Address: $FE0C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Address: $FE0D Read: Write: Reset: Figure 16-3. Break Address Registers (BRKH and BRKL) 16.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 16.6.
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Advance Information — MC68HC(7)08KH12 Section 17. Preliminary Electrical Specifications 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.6 DC Electrical Characteristics .
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17.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 17.6 DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply Voltage VDD –0.3 to +6.0 V Input Voltage (except USB port pins) VIN VSS –0.3 to VDD +0.3 V Programming Voltage VPP VSS –0.3 to 14.
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17.4 Functional Operating Range Characteristic Symbol Value Unit TA 0 to 85 °C VDD 4.0 to 5.5 V Symbol Value Unit Thermal Resistance QFP (64 Pins) θJA 70 °C/W I/O Pin Power Dissipation PI/O User Determined W Power Dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K PD x (TA + 273 °C) + PD2 × θJA W/°C Average Junction Temperature TJ TA + (PD × θJA) °C TJM 100 °C Operating Temperature Range Operating Voltage Range 17.
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17.6 DC Electrical Characteristics Symbol Min Typ(2) Max Unit Output High Voltage (ILOAD = –2.0mA) All I/O Pins VOH VDD – 0.8 — — V Output Low Voltage (ILOAD = 1.6mA) All I/O Pins VOL — — 0.4 V Input High Voltage All ports, IRQ1/VPP, RST, OSC1 VIH 0.7 × VDD — VDD V Input Low Voltage All ports, IRQ1/VPP, RST, OSC1 VIL VSS — 0.3 × VDD V Output High Current (VOH = 2.1V) Port C in LDD mode IOH 3 4.5 6 mA Output Low Current (VOL = 2.
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17.7 Control Timing Characteristic Symbol Min Max Unit Internal Operating Frequency(2) fOP — 6 MHz RST Input Pulse Width Low(3) tIRL 50 — ns NOTES: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized.
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17.9 USB DC Electrical Characteristics Characteristic Symbol Conditions Min Hi-Z State Data Line Leakage ILO 0V
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17.10 USB Low Speed Source Electrical Characteristics Characteristic Transition time: Rise Time Fall Time Symbol TR TF Rise/Fall Time Matching TRFM Output Signal Crossover Voltage VCRS Low Speed Data Rate TDRATE Source Differential Driver Jitter To Next Transition For Paired Transitions TUDJ1 TUDJ2 Receiver Data Jitter Tolerance To Next Transition For Paired Transitions TDJR1 TDJR2 Conditions (Notes 1,2,3) Notes 4, 5, 8 CL= 200pF CL = 600pF CL =200pF CL = 600pF TR/TF 1.5Mbs±1.
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17.11 USB High Speed Source Electrical Characteristics Conditions (Notes 1,2,3) Min TR Notes 4,5,8 CL=50pF TF Rise/Fall Time Matching TRFM Output Signal Crossover Voltage VCRS Characteristic Transition time: Rise Time Fall Time Symbol Typ Max Unit 4 20 ns CL=50pF 4 20 ns TR/TF 90 110 % 1.3 2.0 V High Speed Data Rate TDRATE 12Mbs±0.25% 11.97 12.03 Mbs ns Frame Interval TFRAME 1.0ms±0.05% 0.9995 1.0005 ms –3.5 –4.0 3.5 4.
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17.12 HUB Repeater Electrical Characteristics Low Speed HUB Electrical Characteristics (Root port and downstream ports configured as low speed) Symbol Conditions (Notes 1,2,3) HUB Differential Data Delay TLHDD Note 4, 7, 8 HUB Differential Driver Jitter (including cable) Downstream: To Next Transition For Paired Transitions Upstream To Next Transition For Paired Transitions TLDHJ1 TLDHJ2 Note 4, 7, 8 Data bit width distortion after EOP.
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17.
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17.15 Clock Generation Module Characteristics 17.15.1 CGM Component Specifications Characteristic Crystal reference frequency(1) Symbol Min fXCLK Typ Max 6 Unit MHz Crystal load capacitance(2) CL Crystal fixed capacitance(2) C1 20 pF Crystal tuning capacitance(2) C2 20 pF Feedback bias resistor RB 10 MΩ Series resistor RS 0 kΩ — — — pF NOTES: 1. Fundamental mode crystals only 2. Consult crystal manufacturer’s data. 17.15.
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17.15.3 Acquisition/Lock Time Specifications Description Symbol Min Typ Max Filter Capacitor Multiply Factor CFACT — 0.0145 — F/s V Acquisition Mode Time Factor KACQ — 0.117 — V Tracking Mode Time Factor KTRK — 0.
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Advance Information — MC68HC(7)08KH12 Section 18. Mechanical Specifications 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.3 Plastic Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 260 18.2 Introduction This section gives the dimensions for: • 64-pin plastic quad flat pack (case 840C-04) The following figures show the latest package drawings at the time of this publication.
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18.3 Plastic Quad Flat Pack (QFP) B L B –A–, –B–, –D– 33 48 32 D S C A–B 0.20 (0.008) DETAIL A V P DETAIL A M S 0.20 (0.008) M H A–B B L 0.05 (0.002) D –B– –A– D S S 49 J N 17 64 D 16 1 0.20 (0.008) –D– H A–B M S D S S D S 0.05 (0.002) A–B S 0.20 (0.008) M M C A–B S D S SECTION B–B A 0.20 (0.008) C A–B –H– C E H BASE METAL F DATUM PLANE 0.10 (0.004) –C– SEATING PLANE G DETAIL C U M T R Q SEATING PLANE K X M DETAIL C NOTES: 1.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.