DSP56366 24-Bit Digital Signal Processor User Manual Document Number: DSP56366UM Rev.
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Contents 1 DSP56366 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 DSP56300 Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 DSP56366 Audio Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Program ROM Area Reserved for Motorola Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1 Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.2 Host Transmit Data Register (HOTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.3 Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5.3.
.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1.7 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.
.4.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 . . . . . . . . . . . . . . . . . . . . . . 7.4.6.4 HCSR I2C Clock Freeze (HCKFR)—Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.6 HCSR Master Mode (HMST)—Bit 6 . . . . . . . . . . . . . . . . . . .
.2.10 Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.11 High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.12 High Frequency Clock for Receiver (HCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.3 ESAI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.3.
8.3.3.10 8.3.4 8.3.4.1 8.3.4.2 8.3.4.3 8.3.4.4 8.3.4.5 8.3.4.6 8.3.4.7 8.3.4.8 8.3.4.9 8.3.4.10 8.3.4.11 8.3.4.12 8.3.4.13 8.3.4.14 8.3.4.15 8.3.4.16 8.3.5 8.3.5.1 8.3.5.2 8.3.5.3 8.3.5.4 8.3.5.5 8.3.5.6 8.3.5.7 8.3.6 8.3.6.1 8.3.6.2 8.3.6.3 8.3.6.4 8.3.6.5 8.3.6.6 8.3.6.7 8.3.6.8 8.3.6.9 8.3.6.10 8.3.6.11 8.3.6.12 8.3.6.13 8.3.6.14 8.3.7 8.3.8 8.3.9 8.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 . . . . . . . . . . . . ESAI Receive Control Register (RCR) . . . . . . . . . . . . . . .
8.3.11 ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.13 Receive Slot Mask Registers (RSMA, RSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.
9.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23 . . . . . . . . . . . . . . . . . . . . 9-9 9.3.5 ESAI_1 Receive Control Register (RCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.6 ESAI_1 Common Control Register (SAICR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.7 ESAI_1 Status Register (SAISR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.8 ESAI_1 Receive Shift Registers . . .
10.5.7.2 DAX Transmit Underrun Error Flag (XAUR)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.7.3 DAX Block Transfer Flag (XBLK)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.7.4 XSTR Reserved Bits—Bits 3–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.8 DAX Parity Generator (PRTYG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.5.9 DAX Biphase Encoder . . . .
11.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.6 Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.7 Timer Count Register (TCR) . . .
B.4 B.5 B.6 Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 Host Interface—Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 DSP56366 24-Bit Digital Signal Processor, Rev.
List of Figures Figure 1-1 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 4-1 Figure 4-2 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 6-11 Figure 6-12 Figure 6-13 Figure 6-14 Figure 6-15 Figure 6-16 Figure 7-1 Figure 7-2 Figure 7-3 DSP56366 Block Diagram . . . . . . . . . . . . . . .
Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figure 8-17 Figure 8-18 Figure 8-19 Figure 8-20 Figure 8-21 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 Figure 9-8 Figure 9-9 Figure 9-10 SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . .
Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-15 Figure 9-16 Figure 9-17 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure D-1 Figure D-2 Figure D-3 Figure D-4 Figure D-5 Figure D-6 Figure D-7 Figure D-8 Figure D-9 Figure D-10 Figure D-11 Figure D-12 Figure D-13 Figure D-14 Figure D-15 Figure D-16 Figure D-17 Figure D-18 Figure D-19 TSMA_1 Register . . . . . . . . . . . . . . . . . .
Figure D-20 Figure D-21 Figure D-22 Figure D-23 Figure D-24 Figure D-25 Figure D-26 Figure D-27 Figure D-28 Figure D-29 Figure D-30 Figure D-31 Figure D-32 Figure D-33 Figure D-34 Figure D-35 Figure D-36 ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35 ESAI_1 Multiplex Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-36 ESAI_1 Transmit Clock Control Register . . . . . . . . . . . . . .
List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-12 Table 6-13 Table 6-14 Table 6-15 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Table 8-8 Table 8-9 Table 8-10 Table 8-11 Table 8-12 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 11-1 Table 11-2 Table 11-3 Table 11-4 Table D-1 Table D-2 Table D-3 Table D-4 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56366 are also described in this manual. The DSP56366 is targeted to applications that require digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms.
SECTION 6— HOST INTERFACE (HDI08) • Describes the HDI08 parallel host interface. SECTION 7—SERIAL HOST INTERFACE (SHI) • Describes the serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices.
• The word “assert” means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word “deassert” means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC.
NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
1 1.1 DSP56366 Overview Introduction This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56366 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. Changes in core functionality specific to the DSP56366 are also described in this manual.
DSP56300 Core Description 1.2 DSP56300 Core Description The DSP56366 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Freescale's popular DSP56000 core family while retaining code compatibility with it.
DSP56366 Audio Processor Architecture • • 1.3 — Off-chip expansion up to two 16M × 24-bit word of Data memory. — Off-chip expansion up to 16M × 24-bit word of Program memory. — Simultaneous glueless interface to SRAM and DRAM. Peripheral modules — Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. — Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave.
DSP56300 Core Functional Blocks • • • • • Instruction cache controller PLL-based clock oscillator OnCE module JTAG TAP Memory In addition, the DSP56366 provides a set of on-chip peripherals, described in Section 1.5, "Peripheral Overview". 1.4.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.
DSP56300 Core Functional Blocks the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified. 1.4.2 Address Generation Unit (AGU) The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses.
DSP56300 Core Functional Blocks • • Nested hardware DO loops Fast auto-return interrupts The PCU implements its functions using the following registers: • PC—program counter register • SR—Status register • LA—loop address register • LC—loop counter register • VBA—vector base address register • SZ—stack size register • SP—stack pointer • OMR—operating mode register • SC—stack counter register The PCU also includes a hardware system stack (SS). 1.4.
DSP56300 Core Functional Blocks • • 1.4.6 End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals PLL-based Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN), which performs low-power division and clock pulse generation.
Peripheral Overview ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. There is an instruction cache, made using program RAM. The patch mode (which uses instruction cache space) is used to patch program ROM. The memory switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).
Peripheral Overview 1.5.1 Host Interface (HDI08) The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless connection with a number of industry-standard DSPs, microcomputers, microprocessors, and DMA hardware. The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques.
Peripheral Overview 1.5.4 Enhanced Serial Audio Interface (ESAI) The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Freescale SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator.
2 Signal/Connection Descriptions 2.1 Signal Groupings The input and output signals of the DSP56364 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.
Signal Groupings PORT A ADDRESS BUS DSP56366 A0-A17 VCCA (3) OnCE‰ ON-CHIP EMULATION/ JTAG PORT TDI TCK TDO TMS GNDA (4) PORT A DATA BUS PARALLEL HOST PORT (HDI08) D0-D23 VCCD (4) Port B HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] GNDD (4) HA8/HA1 [PB9] PORT A BUS CONTROL HA9/HA2 [PB10] AA0-AA2/RAS0-RAS2 HRW/HRD [PB11] CAS HDS/HWR [PB12] RD HCS/HA10 [PB13] WR HOREQ/HTRQ [PB14] TA HACK/HRRQ [PB15] VCCH GNDH BR BG SERIAL AUDIO INTERFACE (ESAI) BB VCCC (2) SCKT[PC3] GNDC (2) Port C FST [PC4
Power 2.2 Power Table 2-2 Power Inputs Power Name Description VCCP PLL Power — VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. 2.3 VCCQL (4) Quiet Core (Low) Power — VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
Clock and PLL Table 2-3 Grounds (continued) Ground Name Description GNDA (4) Address Bus Ground — GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. GNDD (4) Data Bus Ground — GNDD is an isolated ground for sections of the data bus I/O drivers.
External Memory Expansion Port (Port A) 2.5 External Memory Expansion Port (Port A) When the DSP56364 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0 – A17, D0 – D23, AA0/RAS0 – AA2/RAS2, RD, WR, BB, CAS. 2.5.1 External Address Bus Table 2-5 External Address Bus Signals Signal Name Type State during Reset A0–A17 Output Tri-stated 2.5.
External Memory Expansion Port (Port A) Table 2-7 External Bus Control Signals (continued) Signal Name Type State during Reset WR Output Tri-stated Write Enable — When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated. TA Input Ignored Input Transfer Acknowledge — If the DSP is the bus master and there is no external bus activity, or the DSP is not the bus master, the TA input is ignored.
Interrupt and Mode Control Table 2-7 External Bus Control Signals (continued) Signal Name Type State during Reset BG Input Ignored Input Signal Description Bus Grant — BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56364 becomes the next bus master. When BG is asserted, the DSP56364 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle.
Interrupt and Mode Control Table 2-8 Interrupt and Mode Control Signal Name Type State during Reset MODA/IRQA Input Input Signal Description Mode Select A/External Interrupt Request A — MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing.
PARALLEL HOST INTERFACE (HDI08) 2.7 PARALLEL HOST INTERFACE (HDI08) The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
PARALLEL HOST INTERFACE (HDI08) Table 2-9 Host Interface (continued) State during Reset Signal Name Type Signal Description HA2 Input GPIO Host Address Input 2 — When the HDI08 is programmed to interface a disconnected non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus.
PARALLEL HOST INTERFACE (HDI08) Table 2-9 Host Interface (continued) State during Reset Signal Name Type HCS Input HA10 Input PB13 Input, output, or disconnected Signal Description GPIO Host Chip Select — When HDI08 is programmed to interface a disconnected nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset.
Serial Host Interface Table 2-9 Host Interface (continued) State during Reset Signal Name Type HACK/ HACK Input HRRQ/ HRRQ Output PB15 Input, output, or disconnected Signal Description GPIO Host Acknowledge — When HDI08 is programmed to interface a single disconnected host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset.
Serial Host Interface Table 2-10 Serial Host Interface Signals (continued) Signal Name Signal Type State during Reset MISO Input or output Tri-stated SDA Input or open-drain output Signal Description SPI Master-In-Slave-Out — When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data.
Serial Host Interface Table 2-10 Serial Host Interface Signals (continued) Signal Name Signal Type State during Reset SS Input Tri-stated HA2 Input Signal Description SPI Slave Select — This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high).
Enhanced Serial Audio Interface 2.9 Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals Signal Name Signal Type HCKR Input or output PC2 Input, output, or disconnected State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver — When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock.
Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type FST Input or output PC4 Input, output, or disconnected State during Reset GPIO disconnected Signal Description Frame Sync for Transmitter — This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only.
Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals (continued) State during Reset Signal Description GPIO disconnected Serial Data Output 5 — When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Signal Name Signal Type SDO5 Output SDI0 Input Serial Data Input 0 — When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register.
Enhanced Serial Audio Interface Table 2-11 Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SDO2/ SDO2_1 Output State during Reset Signal Description GPIO disconnected Serial Data Output 2 — When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.
Enhanced Serial Audio Interface_1 2.10 Enhanced Serial Audio Interface_1 Table 2-12 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type FSR_1 Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver_1 — This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers.
Enhanced Serial Audio Interface_1 Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued) Signal Name Signal Type SCKR_1 Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock_1 — SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).
SPDIF Transmitter Digital Audio Interface Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued) Signal Name Signal Type State during Reset Signal Description SDO4_1 Output GPIO disconnected Serial Data Output 4_1 — When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. SDI1_1 Input Serial Data Input 1_1 — When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register.
Timer 2.12 Timer Table 2-14 Timer Signal Signal Name TIO0 Type Input or Output State during Reset Input Signal Description Timer 0 Schmitt-Trigger Input/Output — When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input.
3 Memory Configuration 3.1 Data and Program Memory Maps The on-chip memory configuration of the DSP56366 is affected by the state of the CE (Cache Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by the SC bit in the Status Register. The internal data and program memory configurations are shown in Table 3-1. The address ranges for the internal memory are shown in Table 3-2 and Table 3-3.
Data and Program Memory Maps Table 3-2 On-chip RAM Memory Locations Bit Settings RAM Memory Locations MSW1 MSW0 CE MS SC Prog. RAM Prog. Cache X Data RAM Y Data RAM X X 0 0 X $0000 - $0BFF n.a. $0000 - $33FF $0000-$1BFF X X 1 0 X $0000 - $07FF enabled $0000 - $33FF $0000-$1BFF 0 0 0 1 X $0000 -$27FF n.a. $0000 - $1FFF $0000 - $13FF 0 1 0 1 X $0000 - $1BFF and $2400 - $27FF n.a. $0000 - $1FFF $0000-$1BFF 1 0 0 1 X $0000 - $ 0FFF and $2400 - $27FF n.a.
Data and Program Memory Maps PROGRAM $FFFFFF INTERNAL RESERVED $FFB000 40K INTERNAL X DATA $FFFFFF $FFFF80 $FFF000 INTERNAL RESERVED $FF00C0 $FFFFFF EXTERNAL $FFFFB0 $FF0000 BOOT ROM $FF0000 INTERNAL I/O (128 words) INTERNAL RESERVED ROM $FF1000 Y DATA $FFFF80 EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED $FFF000 $FF0000 EXTERNAL $00C000 EXTERNAL $006000 8K INTERNAL 32K INTERNAL ROM ROM EXTERNAL $004000 $003400 $004000 INT. RESERVED $001C00 INT.
Data and Program Memory Maps PROGRAM $FFFFFF INTERNAL RESERVED $FFB000 40K INTERNAL $FF1000 $FF00C0 $FF0000 X DATA $FFFFFF $FFFF80 $FFF000 INTERNAL RESERVED INTERNAL I/O (128 words) $FFFFFF EXTERNAL $FFFFB0 INTERNAL RESERVED ROM $FF0000 BOOT ROM Y DATA EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FFFF80 EXTERNAL INTERNAL RESERVED $FFF000 $FF0000 EXTERNAL $00C000 EXTERNAL $006000 8K INTERNAL 32K INTERNAL ROM ROM EXTERNAL $004000 $002000 $004000 INT. RESERVED $001400 INT.
Data and Program Memory Maps PROGRAM $FFFFFF INTERNAL RESERVED $FFB000 40K INTERNAL X DATA $FFFFFF $FFFF80 $FFF000 INTERNAL RESERVED $FF00C0 $FFFFFF EXTERNAL $FFFFB0 $FF0000 BOOT ROM $FF0000 INTERNAL I/O (128 words) INTERNAL RESERVED ROM $FF1000 Y DATA $FFFF80 EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED $FFF000 $FF0000 EXTERNAL $00C000 EXTERNAL $006000 32K INTERNAL EXTERNAL 8K INTERNAL ROM ROM $004000 $002800 1K RAM $002C00 $004000 INT.
Data and Program Memory Maps PROGRAM $FFFFFF INTERNAL RESERVED $FFB000 40K INTERNAL $FF1000 $FF00C0 $FF0000 X DATA $FFFFFF $FFFF80 $FFF000 INTERNAL RESERVED INTERNAL I/O (128 words) $FFFFFF EXTERNAL $FFFFB0 INTERNAL RESERVED ROM $FF0000 BOOT ROM Y DATA $FFFF80 EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED $FFF000 $FF0000 EXTERNAL $00C000 EXTERNAL $006000 32K INTERNAL 8K INTERNAL ROM ROM EXTERNAL $004000 $002000 $004000 INT. RESERVED $001C00 INT.
Data and Program Memory Maps PROGRAM $FFFF X DATA $FFFF $FF80 INTERNAL I/O (128 words) Y DATA $FFFF $FFB0 EXTERNAL I/O (82 words) INTERNAL I/O (46 words) $FF80 EXTERNAL EXTERNAL EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL ROM ROM $4000 $4000 $3400 INT. RESERVED $0000 13K INTERNAL RAM $1C00 INT.
Data and Program Memory Maps PROGRAM $FFFF X DATA $FFFF $FF80 INTERNAL I/O (128 words) Y DATA $FFFF $FFB0 EXTERNAL I/O (80 words) INTERNAL I/O (48words) $FF80 EXTERNAL EXTERNAL EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL ROM $4000 $2000 ROM $4000 INT. RESERVED $1400 INT.
Data and Program Memory Maps PROGRAM $FFFF X DATA $FFFF $FF80 INTERNAL I/O (128 words) Y DATA $FFFF $FFB0 EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80 EXTERNAL EXTERNAL EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL ROM $4000 $2800 1K RAM $2400 INT. RESERVED $1000 4K INTERNAL RAM $0000 $2C00 $0000 ROM $4000 INT. RESERVED 11K INTERNAL RAM $1C00 $0000 INT.
Data and Program Memory Maps PROGRAM $FFFF X DATA $FFFF $FF80 INTERNAL I/O (128 words) Y DATA $FFFF $FFB0 EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80 EXTERNAL EXTERNAL EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL ROM $4000 $2000 $2400 $1C00 $0000 INT. RESERVED 7K INTERNAL RAM $0000 ROM $4000 INT. RESERVED 8K INTERNAL RAM $1C00 $0000 INT.
Data and Program Memory Maps 3.1.1 Reserved Memory Spaces The reserved memory spaces should not be accessed by the user. They are reserved for future expansion. 3.1.2 Program ROM Area Reserved for Freescale Use The last 128 words ($FFAF80-$FFAFFF) of the Program ROM are reserved for Freescale use. This memory area is reserved for use as expansion area for the bootstrap ROM as well as for testing purposes. Customer code should not use this area.
Internal I/O Memory Map while the DSP is in Debug mode. As a result, subsequent instructions might be fetched according to the new memory configuration (after the switch), and thus might execute improperly. 3.1.5 External Memory Support The DSP56366 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale publication DSP56300FM.
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral Address DMA1 X:$FFFFEB DMA SOURCE ADDRESS REGISTER (DSR1) X:$FFFFEA DMA DESTINATION ADDRESS REGISTER (DDR1) X:$FFFFE9 DMA COUNTER (DCO1) X:$FFFFE8 DMA CONTROL REGISTER (DCR1) X:$FFFFE7 DMA SOURCE ADDRESS REGISTER (DSR2) X:$FFFFE6 DMA DESTINATION ADDRESS REGISTER (DDR2) X:$FFFFE5 DMA COUNTER (DCO2) X:$FFFFE4 DMA CONTROL REGISTER (DCR2) X:$FFFFE3 DMA SOURCE ADDRESS REGISTER (DSR3) X:$FFFFE2 DMA DESTINATION
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral Address HDI08 X:$FFFFC7 HOST TRANSMIT REGISTER (HOTX) X:$FFFFC6 HOST RECEIVE REGISTER (HORX) X:$FFFFC5 HOST BASE ADDRESS REGISTER (HBAR) X:$FFFFC4 HOST PORT CONTROL REGISTER (HPCR) X:$FFFFC3 HOST STATUS REGISTER (HSR) X:$FFFFC2 HOST CONTROL REGISTER (HCR) X:$FFFFC1 Reserved X:$FFFFC0 Reserved X:$FFFFBF PORT C CONTROL REGISTER (PCRC) X:$FFFFBE PORT C DIRECTION REGISTER (PRRC) X:$FFFFBD PORT C GPIO DATA R
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral Address Register Name ESAI X:$FFFFBC ESAI RECEIVE SLOT MASK REGISTER B (RSMB) X:$FFFFBB ESAI RECEIVE SLOT MASK REGISTER A (RSMA) X:$FFFFBA ESAI TRANSMIT SLOT MASK REGISTER B (TSMB) X:$FFFFB9 ESAI TRANSMIT SLOT MASK REGISTER A (TSMA) X:$FFFFB8 ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR) X:$FFFFB7 ESAI RECEIVE CONTROL REGISTER (RCR) X:$FFFFB6 ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR) X:$FFFFB5 ESAI TRANSMIT C
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral SHI TRIPLE TIMER ESAI MUX PIN CONTROL Address Register Name X:$FFFF97 Reserved X:$FFFF96 Reserved X:$FFFF95 Reserved X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I2C SLAVE ADDRESS REGISTER (HSAR) X:$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR) X:$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR) X:$FFFF8F TIMER 0 CONTROL/STATUS REGISTER (TCSR0) X:$FFFF8E TIMER 0 LOAD REGISTE
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral PORT E Address Register Name Y:$FFFFAC Reserved Y:$FFFFAB Reserved Y:$FFFFAA Reserved Y:$FFFFA9 Reserved Y:$FFFFA8 Reserved Y:$FFFFA7 Reserved Y:$FFFFA6 Reserved Y:$FFFFA5 Reserved Y:$FFFFA4 Reserved Y:$FFFFA3 Reserved Y:$FFFFA2 Reserved Y:$FFFFA1 Reserved Y:$FFFFA0 Reserved Y:$FFFF9F PORT E CONTROL REGISTER (PCRE) Y:$FFFF9E PORT E DIRECTION REGISTER(PPRE) Y:$FFFF9D PORT E GPIO DATA REGISTER(
Internal I/O Memory Map Table 3-4 Internal I/O Memory Map (continued) Peripheral Address Register Name ESAI_1 Y:$FFFF9C ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1) Y:$FFFF9B ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1) Y:$FFFF9A ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1) Y:$FFFF99 ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1) Y:$FFFF98 ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_) Y:$FFFF97 ESAI_1 RECEIVE CONTROL REGISTER (RCR_1) Y:$FFFF96 ESAI_1 TRANSMIT CLOCK CONTROL REGISTER (TCCR_1
4 4.1 Core Configuration Introduction This chapter contains DSP56300 core configuration information details specific to the DSP56366. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA request sources • OMR • PLL control register • AA control registers • JTAG BSR For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM). 4.
Operating Mode Register (OMR) Table 4-1 Operating Mode Register (OMR) SCS EOM 23 22 21 20 19 18 17 16 15 COM 14 13 12 11 PEN MSW 1 : 0 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS 10 9 8 BE CDP1:0 7 6 MS SD 5 4 3 EBD MD 2 1 0 MC MB MA PEN - Patch Enable ATE - Address Tracing Enable MS - Master memory Switch Mode MSW1 - Memory switch mode 1 APD - Address Priority Disable SD - Stop Delay MSW0 - Memory switch mode 0 ABE - Asyn.
Operating Mode Register (OMR) The Instruction Cache should be initialized with the new instructions according to the following procedure: These steps should be executed from external memory or by download via host interface: 1. Set Cache Enable = 1 2. Set Patch Enable = 1 3. Initialize TAGs to different values by unlock eight different external sectors 4. Lock the PATCH sector(s) 5. Move new code to locked sector(s), to the addresses that should be replaced 6.
Operating Modes ; do movem movem nop #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP p:(r1)+,x0 x0,p:(r2)+ ; Do-loop restriction jsr #M_PROMS jmp nop nop nop nop ENDTEST move move move #5,m0 #6,m1 #7,m2 PATCH_LOOP ENDTEST ; start ROM code execution ; ; patch data ; PATCH_DATA_START PATCH_DATA_END ;**************************************************************************** 4.3 Operating Modes The operating modes are defined as shown in Table 4-2.
Operating Modes Table 4-2 DSP56366 Operating Modes (continued) Mode MOD D MOD C MOD B MOD A Reset Vector 6 0 1 1 0 $FF0000 Bootstrap from SHI (slave I2C mode) (HCKFR=1, 100ns filter enabled) 7 0 1 1 1 $FF0000 Bootstrap from SHI (slave I2C mode)(HCKR=0) 8 1 0 0 0 $008000 Expanded mode 9 1 0 0 1 $FF0000 Reserved for Burn-in testing A 1 0 1 0 $FF0000 Reserved B 1 0 1 1 $FF0000 Reserved C 1 1 0 0 $FF0000 HDI08 Bootstrap in ISA Mode D 1 1 0 1 $FF0000
Interrupt Priority Registers Table 4-3 DSP56366 Mode Descriptions Mode 6 Same as Mode 5 except SHI interface operates in the I2C slave mode with HCKFR set to 1 and the 100ns filter enabled. Mode 7 Same as Mode 5 except SHI interface operates in the I2C slave mode with HCKFR set to 0. Mode 8 The DSP starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. Mode 9 Reserved.
Interrupt Priority Registers 11 10 9 8 ESL11 ESL10 TAL1 TAL0 7 DAL1 6 5 4 DAL0 HDL1 HDL0 3 2 1 0 SHL1 SHL0 ESL1 ESL0 ESAI IPL SHI IPL HDI08 IPL DAX IPL TRIPLE TIMER IPL ESAI_1 IPL 22 23 21 20 19 18 17 16 15 14 13 12 reserved Reserved bit. Read as zero, should be written with zero for future compatibility.
Interrupt Priority Registers Table 4-5 Interrupt Sources Priorities Within an IPL Priority Interrupt Source Level 3 (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non-Maskable Interrupt Levels 0, 1, 2 (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DM
Interrupt Priority Registers Table 4-5 Interrupt Sources Priorities Within an IPL (continued) Priority Interrupt Source SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt ESAI_1 Recei
Interrupt Priority Registers Table 4-6 DSP56366 Interrupt Vectors Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA:$00 3 Hardware RESET VBA:$02 3 Stack Error VBA:$04 3 Illegal Instruction VBA:$06 3 Debug Request Interrupt VBA:$08 3 Trap VBA:$0A 3 Non-Maskable Interrupt (NMI) VBA:$0C 3 Reserved For Future Level-3 Interrupt Source VBA:$0E 3 Reserved For Future Level-3 Interrupt Source VBA:$10 0-2 IRQA VBA:$12 0-2 IRQB VBA:$14 0-2 IRQC VBA:$16
Interrupt Priority Registers Table 4-6 DSP56366 Interrupt Vectors (continued) Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA:$44 0-2 SHI Receive FIFO Not Empty VBA:$46 0-2 Reserved VBA:$48 0-2 SHI Receive FIFO Full VBA:$4A 0-2 SHI Receive Overrun Error VBA:$4C 0-2 SHI Bus Error VBA:$4E 0-2 Reserved VBA:$50 0-2 Reserved VBA:$52 0-2 Reserved VBA:$54 0-2 TIMER0 Compare VBA:$56 0-2 TIMER0 Overflow VBA:$58 0-2 TIMER1 Compare VBA:$5A 0-2 TIMER
DMA Request Sources 4.5 DMA Request Sources The DMA Request Source bits (DRS0-DRS4 bits in the DMA Control/Status registers) encode the source of DMA requests used to trigger the DMA transfers. The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins. The DMA Request Sources are shown in Table 4-7. Table 4-7 DMA Request Sources DMA Request Source Bits DRS4...
PLL Initialization 4.6 4.6.1 PLL Initialization PLL Multiplication Factor (MF0-MF11) The DSP56366 PLL multiplication factor is set to 6 during hardware reset, i.e. the Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $005. 4.6.2 PLL Pre-Divider Factor (PD0-PD3) The DSP56366 PLL Pre-Divider factor is set to 1 during hardware reset, i.e. the Pre-Divider Factor Bits PD0-PD3 in the PLL Control Register (PCTL) are set to $0. 4.6.
JTAG Boundary Scan Register (BSR) Table 4-9 JTAG Identification Register Configuration 31 4.9 28 27 22 21 12 11 1 0 Version Information Customer Part Number Sequence Number Manufacturer Identity 1 0000 000111 0001001111 00000001110 1 JTAG Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56366 JTAG implementation contains bits for all device signal and clock pins and associated control signals.
JTAG Boundary Scan Register (BSR) Table 4-10 DSP56366 BSR Bit Definition (continued) Bit # Pin Name Pin Type BSR Cell Type Bit # Pin Name Pin Type 17 D13 Input/Output Data 93 HAD6 — 18 D12 Input/Output Data 94 HAD6 Input/Output 19 D11 Input/Output Data 95 HAD7 — 20 D10 Input/Output Data 96 HAD7 Input/Output 21 D9 Input/Output Data 97 HAS/A0 — 22 D8 Input/Output Data 98 HAS/A0 Input/Output 23 D7 Input/Output Data 99 HA8/A1 — 24 D6 Input/Output Data
JTAG Boundary Scan Register (BSR) Table 4-10 DSP56366 BSR Bit Definition (continued) Bit # Pin Name Pin Type BSR Cell Type Bit # Pin Name Pin Type 43 A7 Output3 Data 119 HSCKR — 44 A6 Output3 Data 120 HSCKR Input/Output 45 A[8:0] — Control 121 HSCKT — 46 A5 Output3 Data 122 HSCKT Input/Output 47 A4 Output3 Data 123 SCKR — 48 A3 Output3 Data 124 SCKR Input/Output 49 A2 Output3 Data 125 SCKT — 50 A1 Output3 Data 126 SCKT Input/Output 51 A0 Output3 Dat
JTAG Boundary Scan Register (BSR) Table 4-10 DSP56366 BSR Bit Definition (continued) Bit # Pin Name Pin Type 69 EXTAL Input 70 SCKT_1 — 71 SCKT_1 Input/Output 72 CAS — 73 CAS Output3 74 AA2 — 75 AA2 Output3 BSR Cell Type Data Bit # Pin Name Pin Type 145 SS Input Control 146 SCK/SCL — Data 147 SCK/SCL Input/Output Control 148 MISO/SDA — Data 149 MISO/SDA Input/Output Control 150 MOSI/HA0 — Data 151 MOSI/HA0 Input/Output BSR Cell Type Data Control Data Control
JTAG Boundary Scan Register (BSR) NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
5 5.1 General Purpose Input/Output Introduction The DSP56362 provides up to 37 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The techniques for register programming for all GPIO functionality is very similar between these interfaces. This section describes how signals may be used as GPIO. 5.
Programming Model 5.2.4 Port E Signals and Registers Port E has 10 signals, shared with the ESAI_1. Six of the ESAI_1 signals have their own pin, so each of the six signals, if not used as an ESAI_1 signal, can be configured individually as a GPIO signal. The other four ESAI_1 signals share pins with the ESAI. For these shared pins, if the pin is not being used by the ESAI, Port C and the ESAI_1, then it may be used as a Port E GPIO signal.
6 Host Interface (HDI08) 6.1 Introduction The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless connection with a number of industry standard microcomputers, microprocessors, DSPs and DMA hardware. The host bus can operate asynchronously to the DSP core clock, therefore the HDI08 registers are divided into 2 banks.
HDI08 Features — Bit addressing instructions (e.g. BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines. 6.2.
HDI08 Host Port Signals • • 6.
HDI08 Block Diagram Table 6-2 Strobe Signals Support signals HDI08 Port Pin Single strobe bus Dual strobe bus GPIO Mode HRW/HRD HRW HRD/HRD PB11 HDS/HWR HDS/HDS HWR/HWR PB12 Table 6-3 Host request support signals 6.4 HDI08 Port Pin Vector required No vector required GPIO Mode HOREQ/HTRQ HOREQ/HOREQ HTRQ/HTRQ PB14 HACK/HRRQ HACK/HACK HRRQ/HRRQ PB15 HDI08 Block Diagram Figure 6-1 shows the HDI08 registers.
HDI08 – DSP-Side Programmer’s Model Core DMA Data Bus DSP Peripheral Data Bus 24 HCR 24 24 HSR HDDR 24 HDR 24 24 24 HBAR HPCR 24 24 HOTX 24 HOR 8 Address Comparator 24 24 5 3 ICR ISR 8 CVR 8 IVR 8 Latch 8 8 RXH RXM RXL 3 8 8 TXH 8 TXM 8 8 RXL 8 HOST Bus ICR Interface Control Register HCR Host Control Register CVR Command Vector Register HSR Host Status Register ISR Interface Status Register HPCR Host Port Control Register IVR Interrupt Vector Registe
HDI08 – DSP-Side Programmer’s Model The eight host processor registers consists of two data registers and six control registers. All registers can be accessed by the DSP core but not by the external processor. Data registers are 24-bit registers used for high-speed data transfer to and from the DSP. They are as follows: • Host Data Receive Register (HORX) • Host Data Transmit Register (HOTX) The control registers are 16-bit registers used to control the HDI08 functions.
HDI08 – DSP-Side Programmer’s Model NOTE When writing data to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by the operation are updated. If the programmer reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 Family Manual , Freescale publication DSP56300FM for further details. 6.5.
HDI08 – DSP-Side Programmer’s Model Table 6-4 HDI08 IRQ Priority Highest Interrupt Source Host Command (HCP=1) Transmit Data (HTDE=1) Lowest 6.5.3.4 Receive Data (HRDF=1) HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 HF2 and HF3 bits are used as a general-purpose flags for DSP to host communication. HF2 and HF3 may be set or cleared by the DSP core.
HDI08 – DSP-Side Programmer’s Model Table 6-5 HDM[2:0] Functionality (continued) HDM Mode 2 1 0 Description 0 0 1 DMA Mode Data Output Transfers Enabled. (24-Bit words) 0 1 0 DMA Mode Data Output Transfers Enabled. (16-Bit words) 0 1 1 DMA Mode Data Output Transfers Enabled. (8-Bit words) 1 0 1 DMA Mode Data Input Transfers Enabled. (24-Bit words) 1 1 0 DMA Mode Data Input Transfers Enabled. (16-Bit words) 1 1 1 DMA Mode Data Input Transfers Enabled.
HDI08 – DSP-Side Programmer’s Model for the DMA controller to supply the HA2, HA1, and HA0 signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. If HDM1 or HDM0 are set, the HM[1:0] bits in the ICR register reflect the value of HDM[1:0].
HDI08 – DSP-Side Programmer’s Model by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC, which also clears HCP. 6.5.4.4 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4 HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0 and HF1 may be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR register on the host side.
HDI08 – DSP-Side Programmer’s Model 6.5.5.2 HBAR Reserved Bits 8-15 These bits are reserved. They read as zero and should be written with zero for future compatibility. HAD[0-7] Latch A[3:7] HAS COMPARATOR HA[8:10] Base DSP Peripheral data bus Address 8 bits register Chip select BA[3:7] Figure 6-5 Self Chip Select logic 6.5.6 Host Port Control Register (HPCR) The HPCR is a 16-bit read/write control register used by the DSP to control the HDI08 operating mode.
HDI08 – DSP-Side Programmer’s Model 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host address line 8 (HA8). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is configured as GPIO pin according to the value of HDDR and HDR registers. HA8EN is ignored when the HDI08 is not in the multiplexed bus mode (HMUX=0). 6.5.6.
HDI08 – DSP-Side Programmer’s Model 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 The HROD bit controls the output drive of the host request signals. In the single host request mode (HDRQ=0 in ICR), if HROD is cleared and host requests are enabled (HREN=1 and HEN=1 in HPCR), the HOREQ signal is always driven. If HROD is set and host requests are enabled, the HOREQ signal is an open drain output.
HDI08 – DSP-Side Programmer’s Model Write data in Data HWR Write cycle Read data out Data HRD Read cycle In the dual strobe bus mode, there are separate HRD and HWR signals that specify the access as being a read or write access, respectively. Figure 6-8 Dual strobes bus 6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 If the HCSP bit is cleared, the chip select (HCS) signal is configured as an active low input and the HDI08 is selected when the HCS signal is low.
HDI08 – DSP-Side Programmer’s Model 15 14 13 12 11 10 DR15 DR14 DR13 DR12 DR11 DR10 9 8 7 6 5 4 3 2 1 0 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8) 6.5.8 Host Data Register (HDR) The HDR register holds the data value of the corresponding bits of the HDI08 pins which are configured as GPIO pins. The functionality of the Dxx bit depends on the corresponding HDDR bit (DRxx). See Table 6-6.
HDI08 – DSP-Side Programmer’s Model Table 6-7 DSP-Side Registers after Reset Reset Type Register Name Register Data HCR HW Reset SW Reset IR Reset ST Reset All bits 0 0 — — HPCR All bits 0 0 — — HSR HF[1:0] 0 0 — — HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 DMA 0 0 — — HBAR BA[10:3] $80 $80 — — HDDR DR[15:0] 0 0 — — HDR D[15:0] — — — — HORX HORX[23:0] empty empty empty empty HOTX HOTX[23:0] empty empty empty empty Note: A long dash (—) de
HDI08 – External Host Programmer’s Model ENABLE 15 0 HF3 X:HCR HF2 HCIE HTIE HRIE HCR DSP CORE INTERRUPTS RECIEVE DATA FULL TRANSMIT DATA EMPTY HOST COMMAND 15 X:HSR 0 HF1 HF0 HCP HTDE HRDF HSR STATUS Figure 6-11 HSR-HCR Operation 6.6 HDI08 – External Host Programmer’s Model The HDI08 has been designed to provide a simple, high speed interface to a host processor. To the host bus, the HDI08 appears to be eight byte-wide registers.
HDI08 – External Host Programmer’s Model One of the most innovative features of the host interface is the host command feature. With this feature, the host processor can issue vectored interrupt requests to the DSP core. The host may select any of 128 DSP interrupt routines to be executed by writing a vector address register in the HDI08. This flexibility allows the host programmer to execute up to 128 pre-programmed functions inside the DSP.
HDI08 – External Host Programmer’s Model 7 6 5 4 3 2 1 0 HLEND HF1 HF0 HDRQ TREQ RREQ For HDM[2:0]=000 INIT For HDM[2:0]=100 INIT HM1 HM0 HF1 HF0 TREQ RREQ For HDM1=1 and/or HDM0=1 INIT HDM1 HDM0 HF1 HF0 TREQ RREQ HDM[1:0] - These read-only bits reflect the value of the HDM[1:0] bits in the HCR. - Reserved bit. Read as 0. Should be written with 0 for future compatibility. Figure 6-12 Interface Control Register (ICR) 6.6.1.
HDI08 – External Host Programmer’s Model Table 6-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00) HDRQ=0 TREQ HDRQ=1 RREQ HOREQ signal HTRQ signal HRRQ signal 0 0 No Interrupts (Polling) No Interrupts (Polling) No Interrupts (Polling) 0 1 RXDF Request (Interrupt) No Interrupts (Polling) RXDF Request (Interrupt) 1 0 TXDE Request (Interrupt) TXDE Request (Interrupt) No Interrupts (Polling) 1 1 RXDF and TXDE Requests (Interrupts) TXDE Request (Interrupt) RXDF Request (Interrupt)
HDI08 – External Host Programmer’s Model 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order. If set, the HDI08 can be accessed by the host in little endian byte order. If the HLEND bit is cleared, the RXH/TXH register is located at address $5, the RXM/TXM register is located at address $6, and the RXL/TXL register is located at address $7.
HDI08 – External Host Programmer’s Model from the host request rate – i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. If either HDM1 or HDM0 in the HCR register are set, bits 6 and 5 become read-only bits that reflect the value of HDM[1:0]. 6.6.1.7 ICR Initialize Bit (INIT) Bit 7 The INIT bit is used by the host processor to force initialization of the HDI08 hardware.
HDI08 – External Host Programmer’s Model The host processor can select the starting address of any of the 128 possible interrupt routines in the DSP by writing the interrupt routine address divided by 2 into the HV bits. The host processor can thus force execution of any of the existing interrupt handlers (IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses provided they have been pre-programmed in the DSP.
HDI08 – External Host Programmer’s Model written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HOREQ signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE indicates whether the TX registers are full and data can be latched in (so that polling techniques may be used by the host processor). 6.6.3.
HDI08 – External Host Programmer’s Model 6.6.4 Interrupt Vector Register (IVR) The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts. Only the host processor can read and write this register. The contents of IVR are placed on the host data bus (H0–H7) when both the HOREQ and HACK signals are asserted.
HDI08 – External Host Programmer’s Model 6.6.7 Host Side Registers After Reset Table 6-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers seen by the host processor. The hardware reset (HW) is caused by asserting the RESET signal. The software reset (SW) is caused by executing the RESET instruction. The individual reset (IR) is caused by clearing the HEN bit in the HPCR register. The stop reset (ST) is caused by executing the STOP instruction.
Servicing The Host Interface 6.7 Servicing The Host Interface The HDI08 can be serviced by using one of the following protocols: • Polling • Interrupts 6.7.1 HDI08 Host Processor Data Transfer To the host processor, the HDI08 appears as a contiguous block of static RAM. To transfer data between itself and the HDI08, the host processor performs the following steps: 1. Asserts the HDI08 address to select the register to be read or written. 2. Selects the direction of the data transfer.
Servicing The Host Interface STATUS 7 $2 0 HREQ 0 0 HF3 HF2 TRDY TXDE ISR RXDF HRRQ Host Request ASSERTED HOREQ HTRQ 7 $0 0 INIT 0 HLEND HF1 HF0 HDRQ TREQ RREQ ICR ENABLE Figure 6-16 HDI08 Host Request Structure 6.7.3 Servicing Interrupts If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor interrupt inputs, the HDI08 can request service from the host processor by asserting one of these signals.
Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
7 Serial Host Interface 7.1 Introduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI supports two well-known and widely used synchronous serial buses: the Freescale Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-Circuit Control (I2C) bus.
Serial Host Interface Internal Architecture 7.2 Serial Host Interface Internal Architecture The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses the SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques and DMA transfers. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes.
Serial Host Interface Programming Model user’s responsibility to select the proper clock rate within the range as defined in the I2C and SPI bus specifications. HMST SHI Clock SCK/SCL FOSC Divide By 2 HMST = 0 Divide By 1 To Divide By 256 Divide By 1 or 8 HDM0–HDM7 HRS Clock Logic SHI Controller CPHA, CPOL, HI2C AA0417 HMST = 1 Figure 7-2 SHI Clock Generator 7.
7-4 HA5 HA6 HA4 21 HA3 20 22 21 20 21 HBER 22 HBUSY HROE 20 HRFF 19 19 19 18 18 HA1 18 HRNE 17 17 17 16 16 16 HTDE 15 15 15 HTUE 14 14 14 Reserved bit, read as 0, should be written with 0 for future compatibility.
Serial Host Interface Programming Model The SHI interrupt vector table is shown in Table 7-1 and the exception priorities generated by the SHI are shown in Table 7-2.
Serial Host Interface Programming Model 23 Mode of Operation 15 16 8-Bit Data Mode 8 7 16-Bit Data Mode 0 24-Bit Data Mode Stops Data When Data Mode is Selected Passes Data When Data Mode is Selected AA0420 Figure 7-5 SHI I/O Shift Register (IOSR) 7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side The host transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits wide.
Serial Host Interface Programming Model 7.4.4.1 HSAR Reserved Bits—Bits 19, 17–0 These bits are reserved. They read as zero and should be written with zero for future compatibility. 7.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18 Part of the I2C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain the HA[6:0] slave device address.
Serial Host Interface Programming Model SS SCK (CPOL = 0, CPHA = 0) SCK (CPOL = 0, CPHA = 1) SCK (CPOL = 1, CPHA = 0) SCK (CPOL = 1, CPHA = 1) MISO/ MOSI MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture AA0421 Figure 7-6 SPI Data-To-Clock Timing Diagram If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data is not being transferred.
Serial Host Interface Programming Model When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register. 7.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 The HRS bit controls a prescaler in series with the clock generator divider.
Serial Host Interface Programming Model Table 7-3 SHI Noise Reduction Filter Mode HFM1 HFM0 Description 0 0 Bypassed (Disabled) 0 1 Reserved 1 0 Narrow Spike Tolerance 1 1 Wide Spike Tolerance When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment. When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected.
Serial Host Interface Programming Model 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The individual reset state is entered following a one-instruction-cycle delay after clearing HEN. 7.4.6.
Serial Host Interface Programming Model It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardware reset and software reset. 7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the FIFO has one level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HFIFO.
Serial Host Interface Programming Model 7.4.6.8 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bit HIDLE is used only in the I2C master mode; it is ignored otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is empty (HTDE = 1).
Serial Host Interface Programming Model transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset and software reset. NOTE Clearing HTIE masks a pending transmit interrupt only after a one instruction cycle delay. If HTIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HTIE and the RTI instruction at the end of the interrupt service routine. 7.4.6.
Serial Host Interface Programming Model If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector is generated. HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware reset, software reset, SHI individual reset, and during the stop state. 7.4.6.
Characteristics Of The SPI Bus 7.4.6.18 Host Bus Error (HBER)—Bit 21 The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a master (HMST set). In I2C mode, HBER is set if the transmitter does not receive an acknowledge after a byte is transferred; then a stop event is generated and transmission is suspended. In SPI mode, HBER is set if SS is asserted; then transmission is suspended at the end of transmission of the current word.
Characteristics Of The I2C Bus 7.6.1 Overview The I2C bus protocol must conform to the following rules: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line when the clock line is high are interpreted as control signals (see Figure 7-7).
Characteristics Of The I2C Bus Start Event Clock Pulse For Acknowledgment SCL From Master Device 1 2 8 9 Data Output by Transmitter Data Output by Receiver S AA0424 Figure 7-9 Acknowledgment on the I2C Bus A device generating a signal is called a transmitter, and a device receiving a signal is called a receiver. A device controlling a signal is called a master and devices controlled by the master are called slaves.
SHI Programming Considerations ACK from Slave Device S Slave Address Start Bit 1 R/W A ACK from Master Device Data Byte A No ACK from Master Device Last Data Byte N = 0 to M Data Bytes AA0426 1 P Stop Bit Figure 7-11 I2C Bus Protocol For Host Read Cycle NOTE The first data byte in a write-bus cycle can be used as a user-predefined control byte (e.g., to determine the location to which the forthcoming data bytes should be transferred). 7.
SHI Programming Considerations If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX with either DSP instructions or DMA transfers if the HTDE status bit is set. If no writes to HTX occur, the contents of HTX are not transferred to IOSR, so the data shifted out when receiving is the data present in the IOSR at the time.
SHI Programming Considerations It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state (e.g., when switching from transmit to receive data). The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared, and considered if any of them is set. When asserted by the slave device, HREQ indicates that the external slave device is ready for the next data transfer.
SHI Programming Considerations In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited. The HRX FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers (if the HRNE status bit is set). If HCKFR is cleared, when the HRX FIFO is full and IOSR is filled, an overrun error occurs and the HROE status bit is set.
SHI Programming Considerations may be used to interrupt the external I2C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking. 7.7.4 I2C Master Mode The I2C master mode is entered by enabling the SHI (HEN=1), selecting the I2C mode (HI2C=1) and selecting the master mode of operation (HMST=1).
SHI Programming Considerations the HREQ line between two SHI-equipped DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking. 7.7.4.1 Receive Data in I2C Master Mode A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first.
SHI Programming Considerations 7.7.5 SHI Operation During DSP Stop The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active. While the DSP is in the stop state, the SHI remains in the individual reset state. While in the individual reset state the following is true: • If the SHI was operating in the I2C mode, the SHI signals are disabled (high impedance state). • If the SHI was operating in the SPI mode, the SHI signals are not affected.
SHI Programming Considerations NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
8 8.1 Enhanced Serial AUDIO Interface (ESAI) Introduction The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Freescale SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator.
Introduction GDB DDB TX0 RSMA SDO0 [PC11] RSMB Shift Register TSMA TX1 TSMB SDO1 [PC10] Shift Register RCCR TX2 RCR SDO2/SDI3 [PC9] Shift Register TCCR RX3 TCR TX3 SDO3/SDI2 [PC8] SAICR Shift Register SAISR RX2 TX4 TSR SDO4/SDI1 [PC7] Shift Register RX1 Clock / Frame Sync Generators and Control Logic TX5 RCLK SDO5/SDI0 [PC6] Shift Register [PC2] HCKR [PC1] FSR [PC0] SCKR [PC5] HCKT [PC4] FST [PC3] SCKT TCLK RX0 Figure 8-1 ESAI Block Diagram DSP56366 24-Bit Digital Signal Pr
ESAI Data and Control Pins 8.2 ESAI Data and Control Pins Three to twelve pins are required for operation, depending on the operating mode selected and the number of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The SDO2/SDI3, SDO3/SDI2, SDO4/SDI1, and SDO5/SDI0 pins are shared by transmitters 2 to 5 with receivers 0 to 3. The actual mode of operation is selected under software control.
ESAI Data and Control Pins 8.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3 shift register.
ESAI Data and Control Pins When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections.
ESAI Data and Control Pins Table 8-2 Transmitter Clock Sources THCKD TFSD TCKD Transmitter Bit Clock Source 0 0 0 SCKT 0 0 1 HCKT 0 1 0 SCKT FST 0 1 1 HCKT FST 1 0 0 SCKT HCKT 1 0 1 INT HCKT 1 1 0 SCKT HCKT FST 1 1 1 INT HCKT FST OUTPUTS SCKT SCKT SCKT SCKT SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT function is not being used.
ESAI Programming Model 8.2.10 Frame Sync for Transmitter (FST) FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see Table 8-2). The direction of this pin is determined by the TFSD bit in the TCR register. When configured as an output, this pin is the internally generated frame sync signal.
ESAI Programming Model special-purpose time slot register. The following paragraphs give detailed descriptions and operations of each bit in the ESAI registers. The ESAI pins can also function as GPIO pins (Port C), described in Section 8.5, "GPIO - Pins and Registers". 8.3.
ESAI Programming Model RHCKD=1 FOSC DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDER DIVIDE BY 1 TO DIVIDE DIVIDER DIVIDE BY 1 TO DIVIDE RPM0 - RPM7 RFP0 - RFP3 RHCKD=0 RPSR HCKR RHCKD FLAG0 OUT (SYNC MODE) FLAG0 IN (SYNC MODE) INTERNAL BIT CLOCK RSWS4-RSWS0 RX WORD LENGTH DIVIDER SYN=1 RX WORD CLOCK SYN=0 SCKR RX SHIFT REGISTER RCLOCK SYN=0 TSWS4-TSWS0 SYN=1 RCKD TCLOCK INTERNAL BIT CLOCK SCKT TX WORD LENGTH DIVIDER TX WORD CLOCK TCKD TX SHIFT REGISTER THCKD HCKT TPSR TPM0 - TPM7 TF
ESAI Programming Model operational (see Figure 8-3). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. NOTE Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes synchronization problems when using the internal DSP clock as source (TCKD=1 or THCKD=1). 8.3.1.
ESAI Programming Model RX WORD CLOCK RDC0 - RDC4 RFSL RECEIVER FRAME RATE DIVIDER SYNC TYPE INTERNAL RX FRAME CLOCK RFSD SYN=0 RFSD=1 SYN=0 RECEIVE CONTROL LOGIC FSR RECEIVE FRAME SYNC RFSD=0 SYN=1 SYN=1 TDC0 - TDC4 TFSL FLAG1 IN (SYNC MODE) FLAG1OUT (SYNC MODE) TFSD TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC SYNC TYPE INTERNAL TX FRAME CLOCK FST TRANSMIT FRAME SYNC Figure 8-4 ESAI Frame Sync Generator Functional Block Diagram 8.3.1.
ESAI Programming Model 8.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock.
ESAI Programming Model . 11 X:$FFFFB5 10 9 8 TSWS1 TSWS0 TMOD1 TMOD0 7 6 5 4 3 2 1 0 TWA TSHFD TE5 TE4 TE3 TE2 TE1 TE0 18 17 16 15 14 13 12 PADC TFSR TFSL 23 22 21 20 19 TLIE TIE TEDIE TEIE TPR TSWS4 TSWS3 TSWS2 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-5 TCR Register Hardware and software reset clear all the bits in the TCR register. The TCR bits are described in the following paragraphs. 8.3.2.
ESAI Programming Model 8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2 TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set and a frame sync is detected, the transmit #2 portion of the ESAI is enabled for that frame. When TE2 is cleared, the transmitter #2 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX2 when TE2 is cleared but the data is not transferred to the transmit shift register #2.
ESAI Programming Model The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cleared and RE1 in the RCR register is set. If both RE1 and TE4 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE1 and TE4 should not be set at the same time. The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
ESAI Programming Model 2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are transmitted before the transmission of the data word. 8.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9 The TMOD1 and TMOD0 bits are used to define the network mode of ESAI transmitters according to Table 8-4.
Freescale Semiconductor DATA SLOT 0 SLOT 1 SLOT 0 DATA RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET SLOT 2 TRANSMITTER INTERRUPTS (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and a word may be transferred at every time slot. SERIAL DATA FRAME SYNC SERIAL CLOCK Network Mode RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET TRANSMITTER INTERRUPT (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and data is transferred once per frame sync.
ESAI Programming Model 8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table 8-5. See also the ESAI data path programming model in Figure 8-13 and Figure 8-14.
ESAI Programming Model Table 8-5 ESAI Transmit Slot and Word Length Selection (continued) 8.3.2.11 TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 SLOT LENGTH WORD LENGTH Reserved TCR Transmit Frame Sync Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized.
ESAI Programming Model WORD LENGTH: TFSL=0, RFSL=0 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA NOTE: Frame sync occurs while data is valid. ONE BIT LENGTH: TFSL=1, RFSL=1 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA NOTE: Frame sync occurs for one bit time preceding the data.
ESAI Programming Model 8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync starts one serial clock cycle earlier (i.e together with the last bit of the previous data word). 8.3.2.
ESAI Programming Model 8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data interrupts. If TEDIE is set, the transmit even slot data interrupts are enabled. If TEDIE is cleared, the transmit even slot data interrupts are disabled. A transmit even slot data interrupt request is generated if TEDIE is set and the TEDE status flag in the SAISR status register is set.
ESAI Programming Model Hardware and software reset clear all the bits of the RCCR register. 8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0 The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator. A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the receiver serial bit clock (SCKR) pin of the DSP.
ESAI Programming Model Table 8-6 Receiver High Frequency Clock Divider 8.3.3.5 RFP3-RFP0 Divide Ratio $0 1 $1 2 $2 3 $3 4 ... ... $F 16 RCCR Receiver Clock Polarity (RCKP) - Bit 18 The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock.
ESAI Programming Model In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is cleared, then the SCKR pin becomes the IF0 input flag. See Table 8-1 and Table 8-7 . Table 8-7 SCKR Pin Definition Table Control Bits SCKR PIN 8.3.3.
ESAI Programming Model 8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag direction in the synchronous mode (SYN=1). In the asynchronous mode when RHCKD is set, the internal clock generator becomes the source of the receiver high frequency clock, and is the output on the HCKR pin.
ESAI Programming Model 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled and samples data at the SDO5/SDI0 pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1). When RE0 is cleared, receiver 0 is disabled by inhibiting data transfer into RX0. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX0 data register.
ESAI Programming Model 8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7 The Receiver Word Alignment Control (RWA) bit defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is shorter than the slot length. If RWA is cleared, the data word is assumed to be left-aligned in the slot frame. If RWA is set, the data word is assumed to be right-aligned in the slot frame.
ESAI Programming Model Table 8-11 ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH 0 0 0 0 0 8 8 0 0 1 0 0 12 8 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 12 0 0 0 1 0 16 0 1 1 0 0 0 1 0 0 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 0 0 0 1 1 0 1 12 0 1 0 1 0 16 0 0 1 1 1 20 1 1 1 1 0 24 1 1 0 0 0 1 0 1 0 1 12 1 0 0 1 0 16 0 1 1 1 1 20 1 1 1 1 1 24 12 16
ESAI Programming Model Table 8-11 ESAI Receive Slot and Word Length Selection (continued) 8.3.4.10 RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 SLOT LENGTH WORD LENGTH Reserved RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the length of the receive frame sync to be generated or recognized.
ESAI Programming Model 8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set. When REIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by reading the enabled receivers data registers clears ROE, thus clearing the pending interrupt. 8.3.4.
ESAI Programming Model 11 10 9 X:$FFFFB4 23 22 21 8 7 6 ALC TEBE SYN 20 19 18 5 17 4 16 3 15 2 1 0 OF2 OF1 OF0 14 13 12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-10 SAICR Register Hardware and software reset clear all the bits in the SAICR register. 8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin.
ESAI Programming Model the transmit and receive sections. When SYN is set, the synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins SCKR, FSR and HCKR now operate as I/O flags.
ESAI Programming Model ASYNCHRONOUS (SYN=0) TRANSMITTER SDO FRAME SYNC CLOCK EXTERNAL TRANSMIT CLOCK EXTERNAL TRANSMIT FRAME SYNC SCKT ESAI BIT CLOCK FST INTERNAL CLOCK INTERNAL FRAME SYNC EXTERNAL RECEIVE CLOCK EXTERNAL RECEIVE FRAME SYNC SCKR FSR CLOCK FRAME SYNC SDI RECEIVER NOTE: Transmitter and receiver may have different clocks and frame syncs.
ESAI Programming Model 11 X:$FFFFB3 23 10 9 8 7 6 RODF REDF RDF ROE RFS 22 21 20 19 18 5 4 3 2 1 0 IF2 IF1 IF0 12 17 16 15 14 13 TODE TEDE TDE TUE TFS Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-12 SAISR Register 8.3.6.
ESAI Programming Model a word is received, it indicates (only in the network mode) that the frame sync did not occur during reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid only if at least one of the receivers is enabled (REx=1). NOTE In normal mode, RFS always reads as a one when reading data because there is only one time slot per frame – the “frame sync” time slot. 8.3.6.
ESAI Programming Model during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is cleared by hardware, software, ESAI individual, or STOP reset. TFS is valid only if at least one transmitter is enabled (i.e. one or more of TE0, TE1, TE2, TE3, TE4 and TE5 are set). NOTE In normal mode, TFS always reads as a one when transmitting data because there is only one time slot per frame – the “frame sync” time slot. 8.3.6.
ESAI Programming Model TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TODE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot.
ESAI Programming Model 23 16 15870 ESAI RECEIVE DATA REGISTER (READ ONLY) RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE 7 0 7070 23 16 15870 RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE SDI 7 ESAI RECEIVE SHIFT REGISTER 0 7070 MSB LSB 8-BIT DATA 0 MSB 0 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 12-BIT DATA LSB MSB 16-BIT DATA MSB LSB 20-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received LSB first if RSHFD=1. 2. 24-bit fractional format (ALC=0). 3.
ESAI Programming Model 8.3.7 ESAI Receive Shift Registers The receive shift registers (see Figure 8-13 and Figure 8-14) receive the incoming data from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1.
ESAI Programming Model transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See Figure 8-15 and Figure 8-16. Bit number N in TSM (TS**) is the enable/disable control bit for transmission in slot number N.
ESAI Programming Model NOTE When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is generated. 8.3.13 Receive Slot Mask Registers (RSMA, RSMB) The Receive Slot Mask Registers (RSMA and RSMB) are two read/write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition (RDF=1), or to ignore the received data.
Operating Modes NOTE When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input is received. 8.4 Operating Modes ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR and SAICR). The main operating mode are described in the following paragraphs. 8.4.1 ESAI After Reset Hardware or software reset clears the port control register bits and the port direction control register bits, which configure all ESAI I/O pins as disconnected.
Operating Modes 8.4.3 ESAI Interrupt Requests The ESAI can generate eight different interrupt requests (ordered from the highest to the lowest priority): 1. ESAI Receive Data with Exception Status. Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register), at least one of the enabled receive data registers is full (RDF=1), and a receiver overrun error has occurred (ROE=1 in the SAISR register).
Operating Modes 8. ESAI Transmit Data Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled transmit data registers is empty (TDE=1), no exception has occurred (TUE=0 or TEIE=0), and no even slot interrupt has occurred (TEDE=0 or TEDIE=0). Writing to all the TX registers of the enabled transmitters, or to the TSR clears this interrupt request. 8.4.4 Operating Modes – Normal, Network, and On-Demand The ESAI has three basic operating modes and many data/operation formats. 8.
Operating Modes Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources. If internally generated, the ESAI clock generator is used to derive high frequency clock, bit clock and frame sync signals from the DSP internal system clock. 8.4.4.3 Frame Sync Selection The frame sync can be either a bit-long or word-long signal. The transmitter frame format is defined by the TFSL bit in the TCR register.
GPIO - Pins and Registers RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and IF0) are double buffered to/from the HCKR, FSR and SCKR pins. Double buffering the flags keeps them in sync with the TX and RX data lines. Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD, RCKD=1 for output and RCKD=0 for input.
GPIO - Pins and Registers Table 8-12 PCRC and PRRC Bits Functionality X:$FFFFBF PDC[i] PC[i] Port Pin[i] Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit - read as zero; should be written with zero for future compatibility.
ESAI Initialization Examples X:$FFFFBD 11 10 9 8 7 6 5 4 3 2 1 0 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 8-21 PDRC Register 8.6 8.6.1 • • • • • • ESAI Initialization Examples Initializing the ESAI Using Individual Reset The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000).
ESAI Initialization Examples • • • • • • 8.6.3 • • • • • • Configure the control registers TCCR and TCR according to the operating mode, making sure to clear the transmitter enable bits (TE0 - TE5). TPR must remain set. Take the transmitter section out of the personal reset state by clearing TPR. Write first data to the transmitters which will be used during operation. This step is needed even if DMA is used to service the transmitters. Enable the transmitters by setting their TE bits.
9 9.1 Enhanced Serial Audio Interface 1 (ESAI_1) Introduction The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI peripheral in the DSP56366. It is functionally identical to the ESAI peripheral described in Section 8, "Enhanced Serial AUDIO Interface (ESAI)" except for minor differences described in this section. Refer to the ESAI section for functional information about the ESAI_1, in addition to using the information in this section. The ESAI_1 block diagram is shown in Figure 9-1.
Introduction GDB DDB TX0_1 RSMA_1 RSMB_1 Shift Register TSMA_1 TX1_1 TSMB_1 SDO0_1 [PE11] (shared with SDO0 [PC11]) SDO1_1 [PE10] (shared with SDO1 [PC10]) Shift Register RCCR_1 TX2_1 RCR_1 SDO2_1/SDI3_1 [PE9] (shared with SDO2/SDI3 [PC9]) Shift Register TCCR_1 RX3_1 TCR_1 TX3_1 SAICR_1 Shift Register SAISR_1 RX2_1 SDO3_1/SDI2_1 [PE8] (shared with SDO3/SDI2 [PC8]) TX4_1 SDO4_1/SDI1_1 [PE7] TSR_1 Shift Register Clock / Frame Sync Generators and Control Logic RX1_1 TX5_1 RCLK SDO5_1/S
ESAI_1 Data and Control Pins 9.2 ESAI_1 Data and Control Pins The ESAI_1 has 6 dedicated pins and shares 4 pins with the ESAI. The pins are described in the following sections. 9.2.1 Serial Transmit 0 Data Pin (SDO0_1) SDO0_1 transmits data from the TX0_1 serial transmit shift register. It is shared with the ESAI SDO0 signal. The pin may be used as SDO0_1 if it is not defined as ESAI SDO0. The pin may be used as GPIO PE11 if not used by the ESAI or ESAI_1.
ESAI_1 Programming Model 9.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1) SDO5_1/SDI0_1 transmits data from the TX5_1 serial transmit shift register when programmed as transmitter pin, or receives serial data to the RX0_1 serial shift register when programmed as a receiver pin. SDO5_1/SDI0_1 may be programmed as a general-purpose pin (PE6) when the ESAI_1 SDO5_1 and SDI0_1 functions are not being used. 9.2.
ESAI_1 Programming Model The ESAI_1 also contains the GPIO Port E functionality, described in Section 9.5, "GPIO - Pins and Registers". The following paragraphs give detailed descriptions of bits in the ESAI_1 registers that differ in functionality from their descriptions in the ESAI Programming Model. 9.3.1 ESAI_1 Multiplex Control Register (EMUXR) The read/write ESAI_1 Multiplex Control Register (EMUXR) controls which peripheral (ESAI or ESAI_1) is using the shared pins.
ESAI_1 Programming Model Y:$FFFF96 11 10 9 8 7 6 5 4 3 2 1 0 TDC2 TDC1 TDC0 TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPM0 23 22 21 20 19 18 17 16 15 14 13 12 TFSP TCKP TFP3 TFP2 TFP1 TFP0 TDC4 TDC3 THCKD TFSD TCKD THCKP Figure 9-3 TCCR_1 Register 9.3.2.1 TCCR_1 Tx High Freq.
ESAI_1 Programming Model RHCKD=1 FOSC DIVIDE BY 2 FLAG0 OUT (SYNC MODE) PRESCALE DIVIDE BY 1 OR DIVIDER DIVIDE BY 1 TO DIVIDE DIVIDER DIVIDE BY 1 TO DIVIDE RPSR RPM0 - RPM7 RFP0 - RFP3 FLAG0 IN (SYNC MODE) INTERNAL BIT CLOCK RSWS4-RSWS0 RX WORD LENGTH DIVIDER SYN=1 RX WORD CLOCK SYN=0 SCKR_1 RX SHIFT REGISTER RCLOCK SYN=0 TSWS4-TSWS0 SYN=1 RCKD TCLOCK INTERNAL BIT CLOCK SCKT_1 TX WORD LENGTH DIVIDER TX WORD CLOCK TCKD TX SHIFT REGISTER TPSR DIVIDE BY 2 FOSC PRESCALE DIVIDE BY 1 O
ESAI_1 Programming Model RX WORD CLOCK RDC0 - RDC4 RFSL RECEIVER FRAME RATE DIVIDER SYNC TYPE INTERNAL RX FRAME CLOCK RFSD SYN=0 RFSD=1 SYN=0 RECEIVE CONTROL LOGIC FSR_1 RECEIVE FRAME SYNC RFSD=0 SYN=1 SYN=1 TDC0 - TDC4 FLAG1 IN (SYNC MODE) TFSL FLAG1OUT (SYNC MODE) TFSD TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC INTERNAL TX FRAME CLOCK SYNC TYPE FST_1 TRANSMIT FRAME SYNC Figure 9-5 ESAI_1 Frame Sync Generator Functional Block Diagram 9.3.
ESAI_1 Programming Model 9.3.4 ESAI_1 Receive Clock Control Register (RCCR_1) The read/write Receive Clock Control Register (RCCR_1) controls the ESAI_1 receiver clock generator bit and frame sync rates, word length, and number of words per frame for the serial data.
ESAI_1 Programming Model 9.3.5 ESAI_1 Receive Control Register (RCR_1) The read/write Receive Control Register (RCR_1) controls the ESAI_1 receiver section. 11 Y:$FFFF97 10 9 8 RSWS1 RSWS0 RMOD RMOD 7 6 RWA RSHFD 18 23 22 21 20 19 RLIE RIE REDIE REIE RPR 5 17 4 16 RFSR 3 2 1 0 RE3 RE2 RE1 RE0 15 14 13 12 RFSL RSWS4 RSWS3 RSWS2 Reserved bit - read as zero; should be written with zero for future compatibility.
ESAI_1 Programming Model 11 Y:$FFFF93 23 10 9 8 7 6 RODF REDF RDF ROE RFS 22 21 20 19 18 5 4 3 2 1 0 IF2 IF1 IF0 12 17 16 15 14 13 TODE TEDE TDE TUE TFS Reserved bit - read as zero; should be written with zero for future compatibility. Figure 9-10 SAISR_1 Register 9.3.8 ESAI_1 Receive Shift Registers The receive shift registers receive the incoming data from the serial receive data pins.
ESAI_1 Programming Model 9.3.12 ESAI_1 Time Slot Register (TSR_1) The write-only Time Slot Register (TSR_1) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. The transmit data pins of all the enabled transmitters are in the high-impedance state for the respective time slot where TSR_1 has been written.
Operating Modes Y:$FFFF9B 11 10 9 8 7 6 5 4 3 2 1 0 RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 Reserved bit - read as zero; should be written with zero for future compatibility.
GPIO - Pins and Registers 9.5.2 Port E Direction Register (PRRE) The read/write 24-bit Port E Direction Register (PRRE) in conjunction with the Port E Control Register (PCRE) controls the functionality of the ESAI_1 GPIO pins. Table 9-4 describes the port pin configurations. Hardware and software reset clear all PRRE bits.
GPIO - Pins and Registers Y:$FFFF9D 11 10 9 8 7 6 PD11 PD10 PD9 PD8 PD7 PD6 23 22 21 20 19 18 5 17 4 3 PD4 PD3 16 15 2 14 1 0 PD1 PD0 13 12 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 9-17 PDRE Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
GPIO - Pins and Registers NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
10 Digital Audio Transmitter 10.1 Introduction The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below. • Operates on a frame basis—The DAX can handle one frame (consisting of two subframes) of audio and non-audio data at a time.
DAX Signals Global Data Bus 23 XSTR 0 23 0 XNADR 26 XNADBUF MUX 0 XADBUFB 23 C-U-V 23 XCTR XADR XADBUFA Upload DMA Bus 0 XADSR PRTYG Biphase Encoder Preamble Generator MUX 0 MUX 23 ADO ACI DAX State Machine Control Signals DAX Clocks DAX Clock MUX DSP Core Clock Figure 10-1 Digital Audio Transmitter (DAX) Block Diagram 10.
DAX Programming Model • • • • • Parity generator (PRTYG) Preamble generator Biphase encoder Clock multiplexer Control state machine XADR, XADBUFA, XADBUFB and XADSR creates a FIFO-like data path. Channel A is written to XADR and moves to XADBUFA. Then channel B is written to XADR, and when XADBUFB empties XADR moves into it. XADBUFA moves to the shift register XADSR when XADSR has shifted out its last bit.
DAX Internal Architecture Table 10-1 DAX Interrupt Vectors Condition Address Description XAUR VBA:$28 DAX transmit underrun error XADE & XBLK VBA:$2A DAX block transferred XADE VBA:$2E DAX audio data register empty Table 10-2 DAX Interrupt Priority Priority Interrupt highest DAX transmit underrun error DAX block transferred lowest 10.5 DAX audio data register empty DAX Internal Architecture Hardware components shown in Figure 10-1 are described in the following sections.
DAX Internal Architecture 10.5.1 DAX Audio Data Register (XADR) XADR is a 24-bit write-only register. One frame of audio data, which is to be transmitted in the next frame slot, is transferred to this register. Successive write accesses to this register will store channel A and channel B alternately in XADBUFA and in XADBUFB respectively.
DAX Internal Architecture 10.5.4.2 DAX Channel A User Data (XUA)—Bit 11 The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the channel A subframe in the next frame. 10.5.4.3 DAX Channel A Channel Status (XCA)—Bit 12 The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the channel A subframe in the next frame. 10.5.4.
DAX Internal Architecture 10.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0 When the XDIE bit is set, the audio data register empty interrupt is enabled and sends an interrupt request signal to the DSP if the XADE status bit is set. When XDIE bit is cleared, this interrupt is disabled. 10.5.6.2 Underrun Error Interrupt Enable (XUIE)—Bit 1 When the XUIE bit is set, the underrun error interrupt is enabled and sends an interrupt request signal to the DSP if the XAUR status bit is set.
DAX Internal Architecture 10.5.7.1 DAX Audio Data Register Empty (XADE)—Bit 0 The XADE status flag indicates that the DAX audio data register XADR and the audio data buffer XADBUFA are empty (and ready to receive the next frame’s audio data). This bit is set at the beginning of every frame transmission (more precisely, when channel A audio data is transferred from XADBUFA to XADSR).
DAX Internal Architecture 10.5.8 DAX Parity Generator (PRTYG) The PRTYG generates the parity bit for the subframe being transmitted. The generated parity bit ensures that subframe bits four to thirty-one will carry an even number of ones and zeroes. 10.5.9 DAX Biphase Encoder The DAX biphase encoder encodes each audio and non-audio bit into its biphase mark format and shifts this encoded data out to the ADO output pin synchronously to the biphase clock. 10.5.
DAX Programming Considerations • • • • The internal DSP core clock—assumes 1024 × Fs DAX clock input pin (ACI)—512 × Fs DAX clock input pin (ACI)—384 × Fs DAX clock input pin (ACI)—256 × Fs Figure 10-5 shows how each clock is divided to generate the biphase and bit shift clocks DSP Core Clock (1024 × Fs) 1/2 1 0 1 MUX 0 MUX ACI Pin {256,384,512} × Fs MUX 1/4 1 0 (XCS1 or XCS0) 2/3 XCS1 Biphase Clock (128 × Fs) 1/2 1/2 Bit Shift Clock (64 × Fs) XCS0 AA0610 Figure 10-5 Clock Multiplexer
DAX Programming Considerations non-audio data bits of the next frame are stored in XNADR and one frame of audio data to be transmitted in the next frame is stored in the FIFO by two consecutive MOVEP instructions to XADR. If the non-audio bits are not changed from frame to frame, this procedure can be handled within a fast interrupt routine. Storing the next frame’s audio data in the FIFO clears the XADE bit in the XSTR. 10.6.
GPIO (PORT D) - Pins and Registers Channel B $00000B Channel B $00000B Channel A $00000A Channel A $00000A Non-Audio Data $00009 Channel B $000009 Channel B $000008 Channel A $000008 Channel A $000007 Channel B $000007 Non-Audio Data $000006 Channel A $000006 Channel B $000005 Channel B $000005 Channel A $000004 Channel A $000004 Non-Audio Data $000003 Channel B $000003 Channel A $000002 $000001 Channel B $000001 $000000 Channel A $000000 $000002 Channel B Chann
GPIO (PORT D) - Pins and Registers PCRD -Port D Control Register - X:$FFFFD7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC1 PC0 read as zero, should be written with zero for future compatibility 10.7.2 Port D Direction Register (PRRD) The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins. When port pin[i] is configured as GPIO, PDC[i] controls the port pin direction.
GPIO (PORT D) - Pins and Registers Table 10-6 DAX Port GPIO Control Register Functionality 10.7.3 PDC1 PC1 ADO/PD1 pin PDC0 PC0 ACI/PD0 pin DAX state 1 1 ADO 1 0 PD0 Output Enabled 1 1 ADO 1 1 ACI Enabled Port D Data Register (PDRD) The read/write 24-bit Port D Data Register is used to read or write data to/from the DAX GPIO pins. Bits PD[1:0] are used to read or write data from/to the corresponding port pins if they are configured as GPIO.
11 Timer/ Event Counter 11.1 Introduction This section describes the internal timer/event counter in the DSP56366. Each of the three timers (timer 0, 1 and 2) can use internal clocking to interrupt the DSP56366 or trigger DMA transfers after a specified number of events (clocks). In addition, timer 0 provides external access via the bidirectional signal TIO0. When the TIO0 pin is configured as an input, timer 0 can count or capture events, or measure the width or period of an external signal.
Timer/Event Counter Architecture GDB 24 24 24 TPLR TPCR Timer Prescaler Load Register Timer Prescaler Count Register 24 Timer 0 21-bit Prescaler Counter Timer 1 Timer 2 CLK/2 TIO0 AA0673 Figure 11-1 Timer/Event Counter Block Diagram 11.2.2 Individual Timer Block Diagram Figure 11-2 shows the structure of an individual timer module. The three timers are identical in structure, but only timer 0 is externally accessible.
Timer/Event Counter Programming Model GDB 24 24 24 TCSR 24 Load Register 9 TCPR TCR TLR Control/Status Register 24 Count Register Compare Register 24 24 24 2 24 Timer Control Logic Counter = Timer interrupt/ DMA request TIO CLK/2 prescaler CLK (Timer 0 only) AA0676 Figure 11-2 Timer Block Diagram 11.3 Timer/Event Counter Programming Model The DSP56366 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space.
Timer/Event Counter Programming Model 23 0 Timer Prescaler Load Register (TPLR) TPLR = $FFFF83 23 0 Timer Prescaler Count Register (TPCR) TPLR = $FFFF82 7 6 5 4 TC3 TC2 TC1 TC0 15 14 PCE 23 22 3 2 1 TCIE TOIE 13 12 11 DO DI DIR 21 20 19 10 9 0 TE 8 TRM INV 18 17 Timer Control/Status Register (TCSR) TCSR0 = $FFFF8F TCSR1 = $FFFF8B TCSR2 = $FFFF87 16 TCF TOF 23 0 Timer Load Register (TLR) TLR0 = $FFFF8E TLR1 = $FFFF8A TLR2 = $FFFF86 23 0 Timer Compare Register (TCPR) TCP
Timer/Event Counter Programming Model 11.3.1 Prescaler Counter The prescaler counter is a 21-bit counter that is decremented on the rising edge of the prescaler input clock. The counter is enabled when at least one of the three timers is enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler output as its source (i.e., one or more of the PCE bits are set). 11.3.
Timer/Event Counter Programming Model Table 11-1 Prescaler Source Selection 11.3.2.3 PS1 PS0 PRESCALER CLOCK SOURCE 0 0 Internal CLK/2 0 1 TIO0 1 0 Reserved 1 1 Reserved TPLR Reserved Bit 23 This reserved bit is read as zero and should be written with zero for future compatibility. 11.3.3 Timer Prescaler Count Register (TPCR) The TPCR is a 24-bit read-only register that reflects the current value in the prescaler counter. See Figure 11-5.
Timer/Event Counter Programming Model Clearing the TE bit disables the timer. The TE bit is cleared by the hardware RESET signal or the software RESET instruction. NOTE When timer 0 is disabled and TIO0 is not in GPIO mode, the pin is tri-stated. To prevent undesired spikes on TIO0 when Timer 0 is switched from tri-state to an active state, TIO0 should be tied to the power supply with a pullup or pulldown resistor. 11.3.4.
Timer/Event Counter Programming Model Table 11-2 Timer Control Bits for Timer 0 Bit Settings 1 Mode Characteristics TC3 TC2 TC1 TC0 Mode Number Mode Function TIO0 Clock 0 0 0 0 0 Timer and GPIO GPIO1 Internal 0 0 0 1 1 Timer pulse Output Internal 0 0 1 0 2 Timer toggle Output Internal 0 0 1 1 3 Event counter Input External 0 1 0 0 4 Input width measurement Input Internal 0 1 0 1 5 Input period measurement Input Internal 0 1 1 0 6 Capture event
Timer/Event Counter Programming Model 11.3.4.5 TCSR Inverter (INV) Bit 8 The INV bit affects the polarity of the incoming signal on the TIO0 input signal and the polarity of the output pulse generated on the TIO0 output signal. The effects of the INV bit are summarized in Table 11-4. This bit is not in use for timers 1 and 2. It should be left cleared.
Timer/Event Counter Programming Model NOTE The INV bit affects both the timer and GPIO modes of operation. To ensure correct operation, this bit should be changed only when one or both of the following conditions is true: • • The timer has been disabled by clearing the TE bit in the TCSR. The timer is in GPIO mode. The INV bit does not affect the polarity of the prescaler source when TIO0 is used as input to the prescaler. 11.3.4.
Timer/Event Counter Programming Model The DO bit is cleared by the hardware RESET signal or the software RESET instruction. This bit is not in use for timers 1 and 2. It should be left cleared. 11.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15 The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE bit is cleared, the timer uses either an internal (CLK/2) signal or an external signal (TIO0) as its source clock.
Timer Modes of Operation 11.3.5 Timer Load Register (TLR) The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs. The programmer must initialize the TLR to ensure correct operation in the appropriate timer operating modes.
Timer Modes of Operation • • • — Event counter, mode 3: Internal timer interrupt generated by an external clock Measurement — Input width, mode 4: Input pulse width measurement — Input pulse, mode 5: Input signal period measurement — Capture, mode 6: Capture external signal PWM, mode 7: Pulse Width Modulation Watchdog — Pulse, mode 9: Output pulse, internal clock — Toggle, mode 10: Output toggle, internal clock These modes are described in detail below.
Timer Modes of Operation 11.4.1.2 Timer Pulse (Mode 1) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 TIO0 Clock # KIND NAME 0 0 0 1 Output Internal 1 Timer Pulse In this mode, the timer generates a compare interrupt when the timer count reaches a preset value. In addition, timer 0 provides an external pulse on its TIO0 signal. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TCPR.
Timer Modes of Operation When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock.
Timer Modes of Operation 11.4.2 Signal Measurement Modes The following signal measurement modes are provided: • Measurement input width • Measurement input period • Measurement capture These functions are available only on timer 0. 11.4.2.1 Measurement Accuracy The external signal is synchronized with the internal clock used to increment the counter.
Timer Modes of Operation 11.4.2.3 Measurement Input Period (Mode 5) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Kind TIO0 Clock 0 1 0 1 5 Input Period Measurement Input Internal In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO0 signal. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TLR.
Timer Modes of Operation clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. At the first appropriate transition of the external clock detected on the TIO0 signal, the TCF bit in the TCSR is set and, if the TCIE bit is set, a compare interrupt is generated. The counter halts. The contents of the counter are loaded into the TCR.
Timer Modes of Operation The duty cycle of the TIO0 signal is determined by the value in the TCPR. When the value in the TLR is incremented to a value equal to the value in the TCPR, the TIO0 signal is toggled. The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For a 50% duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2. NOTE The value in TCPR must be greater than the value in TLR. 11.4.4 Watchdog Modes 11.4.4.
Timer Modes of Operation 11.4.4.2 Watchdog Toggle (Mode 10) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode NAME Kind TIO0 Clock 1 0 1 0 10 Toggle Watchdog Output Internal In this mode, the timer generates an interrupt at a preset rate. Timer 0 also toggles the output on TIO0. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TPCR.
Timer Modes of Operation 11.4.6.2 Timer Behavior during Stop During the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and the TIO0 signal is disconnected. Any external changes that happen to the TIO0 signal is ignored when the DSP56366 is the stop state. To ensure correct operation, the timers should be disabled before the DSP56366 is placed into the stop state. 11.4.7 DMA Trigger Each timer can also be used to trigger DMA transfers.
Timer Modes of Operation NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Appendix A Bootstrap ROM Contents A.1 DSP56366 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56366 Rev. 0 silicon - (C) Copyright 1999 Motorola Inc. ; ; ; Revision 0.0 1999/JAN/26 - Modified from 56362_RevA_regular_boot_rev01.asm: ; - Change the length of xram and the length of yram ; in burn-in code ; - Change the address of the reserved area in the ; Program ROM to $FFAF80 - $FFAFFF ; ; Revision 0.1 1999/MAR/29 - Enabled 100ns I2C filter in bootstrap ; mode 0110.
DSP56366 Bootstrap Program ; Program ROM, without loading the Program RAM. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=0011 is reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=01xx, then the Program RAM is loaded from the SHI. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=1001 is used for burn-in testing.
DSP56366 Bootstrap Program ; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address.
DSP56366 Bootstrap Program ;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_OGDB EQU $FFFFFC ; OnCE GDB Register M_HPCR M_HSR M_HORX HRDF HF0 HEN EQU EQU EQU EQU EQU EQU $FFFFC4 $FFFFC3 $FFFFC6 $0 $3 $6 ; ; ; ; ; ; Host Host Host Host Host Host M_HRX M_HCSR M_HCKR HRNE HI2C HCKFR HFM0 HFM1 EQU EQU EQU EQU EQU EQU EQU EQU $FFFF94 $FFFF91 $FFFF90 17 1 4 12 13 ; ; ; ; ; ; ; ; SHI SHI SHI SHI SHI SHI SHI SHI ORG PL:$ff00
DSP56366 Bootstrap Program SHILD ; ; ; ; ; ; ; ; ; ; ; ; ; ; This is the routine which loads a program through the SHI port. The SHI operates in the slave mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for receive operation. The word size for transfer is 24 bits. The SHI operates in the SPI or in the I2C mode, according to the bootstrap mode. The program is downloaded according to the following rules: 1) 3 bytes - Define the program length.
DSP56366 Bootstrap Program ; MD:MC:MB:MA=0001 EPROMLD move #BOOT,r2 movep #AARV,X:M_AAR1 do #6,_LOOP9 movem p:(r2)+,a2 asr #8,a,a _LOOP9 move a1,r0 move a1,r1 do a0,_LOOP10 do #3,_LOOP11 movem p:(r2)+,a2 asr #8,a,a _LOOP11 movem a1,p:(r0)+ nop _LOOP10 bra ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; r2 = address of external EPROM aar1 configured for SRAM types of access read number of words and starting address Get the 8 LSB from ext. P mem.
DSP56366 Bootstrap Program ; E - i8051 - Dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; F - MC68302 - Single strobe non-multiplexed bus with negative strobe ; pulse single negative request.
DSP56366 Bootstrap Program ; ; ; ; ; ; ; ; ; ; ; bra future compatability = 0 When the HPCR register is modified HEN should be cleared HAEN = 0 Host acknowledge is disabled HREN = 1 Host requests are enabled HCSEN = 1 Host chip select input enabled HA9EN = 0 (address 9 enable bit has no meaning in non-multiplexed bus) HA8EN = 0 (address 8 enable bit has no meaning non-multiplexed bus) HGEN = 0 Host GPIO pins are disabled HEN
DSP56366 Bootstrap Program ; ; ; ; ; ; ; ; ; ; ; HROD = 0 Host request is active when enabled spare = 0 This bit should be set to 0 for future compatability HEN = 0 When the HPCR register is modified HEN should be cleared HAEN = 0 Host acknowledge is disabled HREN = 1 Host requests are enabled HCSEN = 1 Host chip select input enabled HA9EN = 1 Enable address 9 input HA8EN = 1 Enable address 8 input HGEN = 0 Host GPIO pins are disabled HDI08CONT bset #HEN,x:M_HPCR ; ; ; ; jclr #HRDF,x:M_HSR,* movep
DSP56366 Bootstrap Program ;======================================================================== ; MD:MC:MB:MA=1001 is used for Burn-in code BURN_RESER jclr #MB,omr,BURN ; IF MD:MC:MB:MA=1001, go to BURN ;======================================================================== ; The following modes are reserved, some of which are used for internal testing ; MD:MC:MB:MA=0011 is reserved ; MD:MC:MB:MA=1010 is reserved ; MD:MC:MB:MA=1011 is reserved RESERVED bra <* ;===================================
DSP56366 Bootstrap Program lua (r5)-,r7 ;; r5 = test fail flag = $000000 ;; r7 = test pass flag = $FFFFFF burnin_loop do #9,burn1 ;;---------------------------;; test RAM ;; each pass checks 1 pattern ;;---------------------------move p:(r6)+,x1 move p:(r6)+,x0 move p:(r6)+,y0 ;; pattern for x memory ;; pattern for y memory ;; pattern for p memory ;; write pattern to all memory locations if (EQUALDATA) ;; write x and y memory clr a #start_dram,r0 move #>length_dram,n0 rep n0 mac x0,x1,a x,l:(r0)+ el
DSP56366 Bootstrap Program move eor add y:(r0)+,a1 x0,a a,b ;; a0=a2=0 ;; accumulate error in b _loopd else ;; x/y ram not symmetrical ;; check xram clr a #start_xram,r0 do n0,_loopx move x:(r0)+,a1 eor x1,a add a,b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 do n1,_loopy move y:(r1)+,a1 eor x0,a add a,b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b _loopy endif ;; check pram clr a #start_pram,r2 do n2,_loopp move p:(r2
DSP56366 Bootstrap Program BURN_END PATTERNS ORG PL:,PL: dsm 4 ORG PL:BURN_END,PL:BURN_END dup PATTERNS-* dc * endm NUM_PATTERNS ;; align for correct modulo addressing ; write address in unused Boot ROM location ORG PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories dc dc dc dc $555555 $AAAAAA $333333 $F0F0F0 equ *-PATTERNS ;======================================================================== ; This code fills the unused bootstrap rom locations with their address dup $FF00C0
DSP56366 Bootstrap Program move move move move move move move move move move move move move move move move move x0,x:(r0)+ #$1,x0 x0,x:(r0)+ #$2,x0 x0,x:(r0)+ #$3,x0 x0,x:(r0)+ #$4,x0 x0,x:(r0)+ #$5,x0 x0,x:(r0)+ #$6,x0 x0,x:(r0)+ #$7,x0 x0,x:(r0)+ #$8,x0 x0,x:(r0)+ end DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Appendix B Equates ;********************************************************************************* ; EQUATES for DSP56366 interrupts ; Last update: April 24, 2000 ; ;********************************************************************************* page 132,55,0,0,0 opt intequ mex ident if 1,0 @DEF(I_VEC) ;leave user definition as is.
Equates ;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DM
Equates I_ESAIRLS EQU I_VEC+$36 ; ESAI Receive Last Slot I_ESAITD EQU I_VEC+$38 ; ESAI Transmit Data I_ESAITED EQU I_VEC+$3A ; ESAI Transmit Even Data I_ESAITDE EQU I_VEC+$3C ; ESAI Transmit Data With Exception Status I_ESAITLS EQU I_VEC+$3E ; ESAI Transmit Last Slot ;-----------------------------------------------------------------------; SHI Interrupts ;-----------------------------------------------------------------------I_SHITD EQU I_VEC+$40 ; SHI Transmit Data I_SHITUE EQU I
Equates I_HI08TX EQU I_VEC+$62 ; Host Transmit Data Empty I_HI08CM EQU I_VEC+$64 ; Host Command (Default) ;-----------------------------------------------------------------------; ESAI_1 Interrupts ;-----------------------------------------------------------------------I_ESAI1RD EQU I_VEC+$70 ; ESAI_1 Receive Data I_ESAI1RED EQU I_VEC+$72 ; ESAI_1 Receive Even Data I_ESAI1RDE EQU I_VEC+$74 ; ESAI_1 Receive Data With Exception Status I_ESAI1RLS EQU I_VEC+$76 ; ESAI_1 Receive Last Slot
Equates ; ; EQUATES for I/O Port Programming ; ;-----------------------------------------------------------------------; Register Addresses M_HDR EQU $FFFFC9 ; Host port GPIO data Register M_HDDR EQU $FFFFC8 ; Host port GPIO direction Register M_PCRC EQU $FFFFBF ; Port C Control Register M_PRRC EQU $FFFFBE ; Port C Direction Register M_PDRC EQU $FFFFBD ; Port C GPIO Data Register M_PCRD EQU $FFFFD7 ; Port D Control register M_PRRD EQU $FFFFD6 ; Port D Direction Data Register
Equates M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL EQU $38 ; IRQB Mode Mask M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low) M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high) M_IBL2 EQU 5 ; IRQB Mode Trigger Mode M_ICL EQU $1C0 ; IRQC Mode Mask M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low) M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high) M_ICL2 EQU 8 ; IRQC Mode Trigger Mode M_I
Equates M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low) M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high) ; Interrupt Priority Register Peripheral (IPRP) M_ESL EQU $3 ; ESAI Interrupt Priority Level Mask M_ESL0 EQU 0 ; ESAI Interrupt Priority Level (low) M_ESL1 EQU 1 ; ESAI Interrupt Priority Level (high) M_S
Equates ;-----------------------------------------------------------------------; Register Addresses Of DMA M_DSTR EQU $FFFFF4 ; DMA Status Register M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0 M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1 M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2 M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3 ; Register Addresses Of DMA0 M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register M_DCO0 EQU $FFFFED ;
Equates M_DCR3 ; EQU $FFFFE0 ; DMA3 Control Register Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Register ; Register Addresses Of DMA5 M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register M_DCO5 EQU $FFFFD9 ; DMA5 Counter M_DCR5 EQU $FFFFD8 ; DMA5 Control Register
Equates M_DRS1 EQU 12 ;DMA Request Source bit 1 M_DRS2 EQU 13 ;DMA Request Source bit 2 M_DRS3 EQU 14 ;DMA Request Source bit 3 M_DRS4 EQU 15 ;DMA Request Source bit 4 M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000 ; DMA Channel Priority M_DPR0 EQU 17 ; DMA Channel Priority Level (low) M_DPR1 EQU 18 ; DMA Channel Priority Level (high) M_DTM EQU $380000 ; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 EQU 19 ; DMA Transfer Mode 0 M_DTM1 EQU 20 ; DMA Transfer Mode
Equates ;-----------------------------------------------------------------------; ; EQUATES for Phase Locked Loop (PLL) ; ;-----------------------------------------------------------------------; M_PCTL ; Register Addresses Of PLL EQU $FFFFFD ; PLL Control Register PLL Control Register M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11) M_MF0 EQU 0 ;Multiplication Factor bit 0 M_MF1 EQU 1 ;Multiplication Factor bit 1 M_MF2 EQU 2 ;Multiplication Factor bit 2 M_MF3 EQU 3 ;Mul
Equates M_PEN M_COD EQU EQU 18 ; PLL Enable Bit 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3) M_PD0 EQU 20 ;PreDivider Factor bit 0 M_PD1 EQU 21 ;PreDivider Factor bit 1 M_PD2 EQU 22 ;PreDivider Factor bit 2 M_PD3 EQU 23 ;PreDivider Factor bit 3 ;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;-----------------------------------------------------------------------; Register Addresses Of B
Equates M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA1W0 EQU 5 M_BA1W1 EQU 6 M_BA1W2 EQU 7 ;Area 1 Wait Control Bit 2 M_BA1W3 EQU 8 ;Area 1 Wait Control Bit 3 M_BA1W4 EQU 9 ;Area 1 Wait Control Bit 4 M_BA2W EQU ;Area 1 Wait Control Bit 0 ;Area 1 Wait Control Bit 1 $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA2W0 EQU 10 ;Area 2 Wait Control Bit 0 M_BA2W1 EQU 11 ;Area 2 Wait Control Bit 1 M_BA2W2 EQU 12 ;Area 2 Wait Control Bit 2 M_BA3W EQU $E000
Equates M_BRW0 EQU 2 ;Out of Page Wait States bit 0 M_BRW1 EQU 3 ; Out of Page Wait States bit 1 M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPS0 EQU 4 ; DRAM Page Size Bits 0 M_BPS1 EQU 5 ; DRAM Page Size Bits 1 M_BPLE EQU 11 ; Page Logic Enable M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7) M_BRF0 EQU 15 ; Refresh Rate Bit 0 M_BRF1 EQU
Equates M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BNC0 EQU 8 ; Number of Address Bits to Compare 0 M_BNC1 EQU 9 ; Number of Address Bits to Compare 1 M_BNC2 EQU 10 ; Number of Address Bits to Compare 2 M_BNC3 EQU 11 ; Number of Address Bits to Compare 3 M_BAC EQU $FFF000 ; Address to Compare Bits Mask (BAC0-BAC11) M_BAC0 EQU 12 ; Address to Compare Bits 0 M_BAC1 EQU 13 ; Address to
Equates M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ; DO-Loop Flag M_FV EQU 16 ; DO-Forever Flag M_SA EQU 17 ; Sixteen-Bit Arithmetic M_CE EQU 19 ; Instruction Cache Enable M_SM EQU 20 ; Arithmetic Saturation M_RM EQU 21 ; Rounding Mode M_CP EQU $c00000
Equates M_BE EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ABE EQU 13 ;Async. Bus Arbitration Enable M_APD EQU 14 ;Addess Priority Disable M_ATE EQU 15 ;Address Tracing Enable M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. M_WRP EQU 19 ; Extended WRaP flag in OMR.
Equates M_XBLK ; EQU 2 ; DAX Block Transferred (XBLK) non-audio bits in XNADR M_XVA EQU 10 ; DAX Channel A Validity (XVA) M_XUA EQU 11 ; DAX Channel A User Data (XUA) M_XCA EQU 12 ; DAX Channel A Channel Status (XCA) M_XVB EQU 13 ; DAX Channel B Validity (XVB) M_XUB EQU 14 ; DAX Channel B User Data (XUB) M_XCB EQU 15 ; DAX Channel B Channel Status (XCB) ; control bits in XCTR M_XDIE EQU 0 ; DAX Audio Data Register Empty Interrupt Enable (XDIE) M_XUIE EQU 1 ; DAX Underr
Equates ; HSAR bits M_HA6 EQU 23 ; SHI I2C Slave Address (HA6) M_HA5 EQU 22 ; SHI I2C Slave Address (HA5) M_HA4 EQU 21 ; SHI I2C Slave Address (HA4) M_HA3 EQU 20 ; SHI I2C Slave Address (HA3) M_HA1 EQU 18 ; SHI I2C Slave Address (HA1) ; control and status bits in HCSR M_HBUSY EQU 22 ; SHI Host Busy (HBUSY) M_HBER EQU 21 ; SHI Bus Error (HBER) M_HROE EQU 20 ; SHI Receive Overrun Error (HROE) M_HRFF EQU 19 ; SHI Receivr FIFO Full (HRFF) M_HRNE EQU 17 ; SHI Receive F
Equates ; control bits in HCKR M_HFM1 EQU 13 ; SHI Filter Model (HFM1) M_HFM0 EQU 12 ; SHI Filter Model (HFM0) M_HDM7 EQU 10 M_HDM6 EQU 9 ; SHI Divider Modulus Select (HDM6) M_HDM5 EQU 8 ; SHI Divider Modulus Select (HDM5) M_HDM4 EQU 7 ; SHI Divider Modulus Select (HDM4) M_HDM3 EQU 6 ; SHI Divider Modulus Select (HDM3) M_HDM2 EQU 5 ; SHI Divider Modulus Select (HDM2) M_HDM1 EQU 4 ; SHI Divider Modulus Select (HDM1) M_HDM0 EQU 3 ; SHI Divider Modulus Select (HDM0) M_
Equates M_RCR_1 EQU $FFFF97 ; ESAI_1 Receive Control Register (RCR_1) M_TCCR_1 EQU $FFFF96 ; ESAI_1 Transmit Clock Control Register (TCCR_1) M_TCR_1 $FFFF95 ; ESAI_1 Transmit Control Register (TCR_1) $FFFF94 ; ESAI_1 Control Register (SAICR_1) EQU M_SAICR_1 EQU M_SAISR_1 EQU $FFFF93 ; ESAI_1 Status Register (SAISR_1) M_RX3_1 EQU $FFFF8B ; ESAI_1 Receive Data Register 3 (RX3_1) M_RX2_1 EQU $FFFF8A ; ESAI_1 Receive Data Register 2 (RX2_1) M_RX1_1 EQU $FFFF89 ; ESAI_1 Receive Data Regi
Equates M_RCR EQU $FFFFB7 ; ESAI Receive Control Register (RCR) M_TCCR EQU $FFFFB6 ; ESAI Transmit Clock Control Register (TCCR) M_TCR EQU $FFFFB5 ; ESAI Transmit Control Register (TCR) M_SAICR EQU $FFFFB4 ; ESAI Control Register (SAICR) M_SAISR EQU $FFFFB3 ; ESAI Status Register (SAISR) M_RX3 EQU $FFFFAB ; ESAI Receive Data Register 3 (RX3) M_RX2 EQU $FFFFAA ; ESAI Receive Data Register 2 (RX2) M_RX1 EQU $FFFFA9 ; ESAI Receive Data Register 1 (RX1) M_RX0 EQU $FFFFA8 ; ES
Equates M_RS21 EQU 5 ; ESAI M_RS20 EQU 4 ; ESAI M_RS19 EQU 3 ; ESAI M_RS18 EQU 2 ; ESAI M_RS17 EQU 1 ; ESAI M_RS16 EQU 0 ; ESAI ; RSMA Register bits M_RS15 EQU 15 ; ESAI M_RS14 EQU 14 ; ESAI M_RS13 EQU 13 ; ESAI M_RS12 EQU 12 ; ESAI M_RS11 EQU 11 ; ESAI M_RS10 EQU 10 ; ESAI M_RS9 EQU 9 ; ESAI M_RS8 EQU 8 ; ESAI M_RS7 EQU 7 ; ESAI M_RS6 EQU 6 ; ESAI M_RS5 EQU 5 ; ESAI M_RS4 EQU 4 ; ESAI M_RS3 EQU 3 ; ESAI M_RS2 EQU 2 ; ESAI M_
Equates M_TS27 EQU 11 ; ESAI M_TS26 EQU 10 ; ESAI M_TS25 EQU 9 ; ESAI M_TS24 EQU 8 ; ESAI M_TS23 EQU 7 ; ESAI M_TS22 EQU 6 ; ESAI M_TS21 EQU 5 ; ESAI M_TS20 EQU 4 ; ESAI M_TS19 EQU 3 ; ESAI M_TS18 EQU 2 ; ESAI M_TS17 EQU 1 ; ESAI M_TS16 EQU 0 ; ESAI ; TSMA Register bits M_TS15 EQU 15 ; ESAI M_TS14 EQU 14 ; ESAI M_TS13 EQU 13 ; ESAI M_TS12 EQU 12 ; ESAI M_TS11 EQU 11 ; ESAI M_TS10 EQU 10 ; ESAI M_TS9 EQU 9 ; ESAI M_TS8 EQU 8 ;
Equates M_TS1 EQU 1 ; ESAI M_TS0 EQU 0 ; ESAI ; RCCR Register bits M_RHCKD EQU 23 ; ESAI M_RFSD EQU 22 ; ESAI M_RCKD EQU 21 ; ESAI M_RHCKP EQU 20 ;ESAI M_RFSP EQU 19 ; ESAI M_RCKP EQU 18 ;ESAI M_RFP EQU $3C000 ;ESAI MASK M_RFP3 EQU 17 ; ESAI M_RFP2 EQU 16 ; ESAI M_RFP1 EQU 15 ; ESAI M_RFP0 EQU 14 ; ESAI M_RDC EQU $3E00 ;ESAI MASK M_RDC4 EQU 13 ; ESAI M_RDC3 EQU 12 ; ESAI M_RDC2 EQU 11 ; ESAI M_RDC1 EQU 10 ; ESAI M_RDC0 EQU 9 M_RPS
Equates M_RPM1 EQU 1 ; ESAI M_RPM0 EQU 0 ; ESAI ; RCR Register bits M_RLIE EQU 23 ; ESAI M_RIE EQU 22 ; ESAI M_REDIE EQU 21 ; ESAI M_REIE EQU 20 ; ESAI M_RPR EQU 19 ; ESAI M_RFSR EQU 16 ; ESAI M_RFSL EQU 15 ; ESAI M_RSWS EQU M_RSWS4 EQU 14 ; ESAI M_RSWS3 EQU 13 ; ESAI M_RSWS2 EQU 12 ; ESAI M_RSWS1 EQU 11 ; ESAI M_RSWS0 EQU 10 ; ESAI M_RMOD $7C00 EQU ;ESAI MASK $300 M_RMOD1 EQU 9 ; ESAI M_RMOD0 EQU 8 ; ESAI M_RWA M_RSHFD M_RE EQU EQU
Equates M_THCKD EQU 23 ; ESAI M_TFSD EQU 22 ; ESAI M_TCKD EQU 21 ; ESAI M_THCKP EQU 20 ;ESAI M_TFSP EQU 19 ; ESAI M_TCKP EQU 18 ; ESAI M_TFP EQU M_TFP3 EQU 17 ; ESAI M_TFP2 EQU 16 ; ESAI M_TFP1 EQU 15 ; ESAI M_TFP0 EQU 14 ; ESAI M_TDC EQU $3C000 $3E00 ; M_TDC4 EQU 13 ; ESAI M_TDC3 EQU 12 ; ESAI M_TDC2 EQU 11 ; ESAI M_TDC1 EQU 10 ; ESAI M_TDC0 EQU 9 M_TPSR EQU 8 M_TPM EQU ; ESAI ; ESAI $FF ; M_TPM7 EQU 7 ; ESAI M_TPM6 EQU 6 ; E
Equates M_TLIE EQU 23 ; ESAI M_TIE EQU 22 ; ESAI M_TEDIE EQU 21 ; ESAI M_TEIE EQU 20 ; ESAI M_TPR EQU 19 ; ESAI M_PADC EQU 17 ; ESAI M_TFSR EQU 16 ; ESAI M_TFSL EQU 15 ; ESAI M_TSWS EQU $7C00 M_TSWS4 EQU 14 ; ESAI M_TSWS3 EQU 13 ; ESAI M_TSWS2 EQU 12 ; ESAI M_TSWS1 EQU 11 ; ESAI M_TSWS0 EQU 10 ; ESAI M_TMOD EQU $300 M_TMOD1 EQU 9 ; ESAI M_TMOD0 EQU 8 ; ESAI M_TWA M_TSHFD M_TEM EQU 7 EQU ; ESAI 6 EQU ; ESAI $3F M_TE5 EQU 5 ; ESAI
Equates M_ALC EQU 8 ;ESAI M_TEBE EQU 7 ; ESAI M_SYN EQU 6 ; ESAI M_OF2 EQU 2 ; ESAI M_OF1 EQU 1 ; ESAI M_OF0 EQU 0 ; ESAI ; status bits of SAISR M_TODE EQU 17 ; ESAI M_TEDE EQU 16 ; ESAI M_TDE EQU 15 ; ESAI M_TUE EQU 14 ; ESAI M_TFS EQU 13 ; ESAI M_RODF EQU 10 ; ESAI M_REDF EQU 9 ; ESAI M_RDF EQU 8 ; ESAI M_ROE EQU 7 ; ESAI M_RFS EQU 6 ; ESAI M_IF2 EQU 2 ; ESAI M_IF1 EQU 1 ; ESAI M_IF0 EQU 0 ; ESAI ;------------------------------
Equates M_HORX EQU $FFFFC6 ; HOST Receive Register (HORX) M_HBAR EQU $FFFFC5 ; HOST Base Address Register (HBAR) M_HPCR EQU $FFFFC4 ; HOST Port Control Register (HPCR) M_HSR EQU $FFFFC3 ; HOST Status Register (HSR) M_HCR EQU $FFFFC2 ; HOST Control Register (HCR) $0 ; HOST Receive interrupts Enable ; M_HRIE M_HOTIE HCR bits EQU EQU $1 ; HOST Transmit Interrupt Enable M_HCIE EQU $2 ; HOST Command Interrupt Enable M_HF2 EQU $3 ; HOST Flag 2 M_HF3 EQU $4 ; HOST Flag 3 M_HO
Equates M_HCSEN EQU $3 ; HOST Chip Select Enable M_HREN EQU $4 ; HOST Request Enable M_HAEN EQU $5 ; HOST Acknowledge Enable M_HOEN EQU $6 ; HOST Enable M_HROD EQU $8 ; HOST Request Open Dranin mode M_HDSP EQU $9 ; HOST Data Strobe Polarity M_HASP EQU $a ; HOST Address Strobe Polarity M_HMUX EQU $b ; HOST Multiplexed bus select M_HDDS EQU $c ; HOST Double/Single Strobe select M_HCSP EQU $d ; HOST Chip Select Polarity M_HRP EQU $e ; HOST Request Polarity M_HAP EQ
Equates M_TCSR0 EQU $FFFF8F M_TLR0 EQU $FFFF8E M_TCPR0 EQU $FFFF8D M_TCR0 EQU $FFFF8C ; ; TIMER0 Load Reg ; TIMER0 Compare Register ; TIMER0 Count Register Register Addresses Of TIMER1 M_TCSR1 EQU $FFFF8B M_TLR1 EQU $FFFF8A M_TCPR1 EQU $FFFF89 M_TCR1 EQU $FFFF88 ; ; TIMER0 Control/Status Register ; TIMER1 Control/Status Register ; TIMER1 Load Reg ; TIMER1 Compare Register ; TIMER1 Count Register Register Addresses Of TIMER2 M_TCSR2 EQU $FFFF87 M_TLR2 EQU $FFFF86 M_TCPR2
Equates M_TOF EQU 20 ; Timer Overflow Flag M_TCF EQU 21 ; Timer Compare Flag ; Timer Prescaler Register Bit Flags M_PS EQU $600000 M_PS0 EQU 21 M_PS1 EQU 22 ; ; Prescaler Source Mask Timer Control Bits M_TC0 EQU 4 ; Timer Control 0 M_TC1 EQU 5 ; Timer Control 1 M_TC2 EQU 6 ; Timer Control 2 M_TC3 EQU 7 ; Timer Control 3 ;------------------ end of ioequ.asm ------------------------ DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Equates NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Appendix C JTAG BSDL -------- FILENAME : 56366TQFP_revA.
JTAG BSDL CAS_:out EXTAL:in CVCC:linkage CGND:linkage TA_:in BR_:buffer BB_:inout WR_:out RD_:out BG_:in A:out AVCC:linkage AGND:linkage D:inout DVCC:linkage DGND:linkage MODD:in MODC:in MODB:in MODA:in MOSI:inout SDA:inout SDO41_1:inout SDO50_1:inout FST_1:inout FSR_1:inout SCKR_1:inout SCKT_1:inout bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit); to
JTAG BSDL "QVCCH: (20, 49, 95), " & "HP: (43, 42, 41, 40, 37, 36, 35, 34, 33, 32, 31, 22, 21, 30, 24, 23), " & "ADO: 27, " & "ACI: 28, " & "TIO: 29, " & "HVCC: 38, " & "HGND: 39, " & "RESET_: 44, " & "PVCC: 45, " & "PCAP: 46, " & "PGND: 47, " & "SDO50_1: 48, " & "FST_1: 50, " & "AA: (70, 69, 51), " & "CAS_: 52, " & "SCKT_1: 53, " & "EXTAL: 55, " & "CVCC: (57, 65), " & "CGND: (58, 66), " & "FSR_1: 59, " & "SCKR_1: 60, " & "PINIT: 61, " & "TA_: 62, " & "BR_: 63, " & "BB_: 64, " & "WR_: 67, " & "RD_: 68, " &
JTAG BSDL attribute INSTRUCTION_OPCODE of DSP56366 : entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "CLAMP (0101)," & "HIGHZ (0100)," & "ENABLE_ONCE (0110)," & "DEBUG_REQUEST(0111)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of DSP56366 : entity is "0001"; attribute IDCODE_REGISTER of DSP56366 : entity is "0000" & -- version "000111" & -- manufacturer's use "0001001111" & -- sequence number "00000001110" & -- manufacturer identity "1"; -- 1149.
JTAG BSDL "28 "29 "30 "31 "32 "33 "34 "35 "36 "37 "38 "39 -- num "40 "41 "42 "43 "44 "45 "46 "47 "48 "49 "50 "51 "52 "53 "54 "55 "56 "57 "58 "59 -- num "60 "61 "62 "63 "64 "65 "66 "67 "68 "69 "70 "71 "72 "73 "74 "75 "76 "77 "78 "79 -- num (BC_1, (BC_6, (BC_6, (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (B
JTAG BSDL "80 "81 "82 "83 "84 "85 "86 "87 "88 "89 "90 "91 "92 "93 "94 "95 "96 "97 "98 "99 -- num "100 "101 "102 "103 "104 "105 "106 "107 "108 "109 "110 "111 "112 "113 "114 "115 "116 "117 "118 "119 -- num "120 "121 "122 "123 "124 "125 "126 "127 "128 "129 "130 "131 "132 (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1
JTAG BSDL "133 "134 "135 "136 "137 "138 "139 -- num "140 "141 "142 "143 "144 "145 "146 "147 "148 "149 "150 "151 (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, *, control, SDOI41, bidir, *, control, SDOI32, bidir, *, control, SDOI23, bidir, *, control, port func SDO1, bidir, *, control, SDO0, bidir, *, control, HREQ_, bidir, SS_, input, *, control, SCK, bidir, *, control, SDA, bidir, *, control, MOSI, bidir, 1)," &
JTAG BSDL NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Appendix D Programmer’s Reference D.1 Introduction This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPs memory-mapped peripherals, an interrupt address table, an interrupt exception priority table, a quick reference to the host interface, and programming sheets for the major programmable registers on the DSP. D.1.1 Peripheral Addresses Table D-1 lists the memory addresses of all on-chip peripherals. D.1.
Internal I/O Memory Map Table D-1.
Internal I/O Memory Map Table D-1.
Internal I/O Memory Map Table D-1.
Internal I/O Memory Map Table D-1.
Internal I/O Memory Map Table D-1. Internal I/O Memory Map (continued) Peripheral PORT E Address Register Name Y:$FFFFA7 Reserved Y:$FFFFA6 Reserved Y:$FFFFA5 Reserved Y:$FFFFA4 Reserved Y:$FFFFA3 Reserved Y:$FFFFA2 Reserved Y:$FFFFA1 Reserved Y:$FFFFA0 Reserved Y:$FFFF9F PORT E CONTROL REGISTER (PCRE) Y:$FFFF9E PORT E DIRECTION REGISTER(PRRE) Y:$FFFF9D PORT E GPIO DATA REGISTER(PDRE) DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Internal I/O Memory Map Table D-1.
Interrupt Vector Addresses D.3 Interrupt Vector Addresses Table D-2.
Interrupt Vector Addresses Table D-2.
Interrupt Source Priorities (within an IPL) D.4 Interrupt Source Priorities (within an IPL) Table D-3.
Interrupt Source Priorities (within an IPL) Table D-3.
Host Interface—Quick Reference D.5 Host Interface—Quick Reference Table D-4.
Host Interface—Quick Reference Table D-4.
Host Interface—Quick Reference Table D-4. HDI08 Programming Model (continued) Bit Reg HSR Num Mnemonic 0 HRDF 1 2 HTDE HCP Name Host Receive Data Full Host Transmit Data Empty Host Command Pending Reset Type Val Function 0 no receive data to be read 1 receive data register is full 1 0 transmit data register empty 0 no host command pending 1 host command pending Comments HW / SW IR ST 0 0 0 1 1 1 0 0 0 transmit data reg.
Programming Sheets Table D-4.
Programming Sheets Date: Programmer: Application: Sheet 1 of 5 Carry Overfow Zero Negative Central Processor Unnormalized ( U = Acc(47) xnor Acc(46) ) Extension Limit FFT Scaling ( S = Acc(46) xor Acc(45) ) I(1:0) 00 01 10 11 Scaling Mode S(1:0) Scaling Mode 00 No scaling 01 Scale down 10 Scale up 11 Reserved Interrupt Mask Exceptions Masked None IPL 0 IPL 0, 1 IPL 0, 1, 2 Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved I
Programming Sheets Date: Application: Programmer: Sheet 2 of 5 Central Processor Chip Operating Modes MOD(D:A) Reset Vector Description See Core Configuration Section.
D-18 IDL1 0 0 1 1 IDL0 0 1 0 1 Enabled No Yes Yes Yes ICL0 0 1 0 1 IPL — 0 1 2 Enabled No Yes Yes Yes IPL — 0 1 2 IBL2 0 1 IAL1 0 0 1 1 8 7 6 IBL0 0 1 0 1 5 4 Enabled No Yes Yes Yes 3 2 IPL — 0 1 2 Enabled No Yes Yes Yes 1 IPL — 0 1 2 0 D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1D0L0 IDL2 IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 9 IBL1 0 0 1 1 IAL0 0 1 0 1 IRQA Mode IRQB Mode Trigger Level Neg. Edge Trigger Level Neg.
Freescale Semiconductor IPL — 0 1 2 DAL1 0 0 1 1 Enabled No Yes Yes Yes DAX IPL DAL0 0 1 0 1 IPL — 0 1 2 IPL — 0 1 2 $0 * = Reserved, Program as 0 $0 $0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 9 8 ESAI IPL 7 6 5 4 3 SHL1 SHL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes SHI IPL 2 IPL — 0 1 2 ESL1 ESL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes 1 IPL — 0 1 2 0 ESL11 ESL10 TAL1 TAL0 DAL1 DAL0 HDL1 HDL0 SHL1 SHL0 ESL1 ESL0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Enabled No Yes Yes Yes TEC IPL
D-20 0 1 1 PLL Control Register (PCTL) X:$FFFFFD Read/Write Reset = $010005 PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 9 8 DF0 MF11 MF10 MF9 MF8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 on DSP56366 operation 6 5 4 3 2 MF7 MF6 MF5 MF4 MF3 MF2 7 Division Factor Bits (DF0 – DF2) DF2 – DF0 Division Factor DF 20 $0 $1 21 $2 22 • • • • • • $7 27 1 = External Xtal Freq <200KHz 0 MF1 MF0 1 Multiplication Factor Bits MF0 – MF11 MF11 – MF0 Multiplication Factor MF 1 $000 2 $001 3 $002 • • • •
Programming Sheets Date: Application: Programmer: Sheet 1 of 6 HOST (HDI08) DSP Side Host Receive Data (usually read by program) 23 22 21 20 19 18 17 16 15 14 13 12 Receive High Byte 11 10 9 8 7 6 Receive Middle Byte 5 4 3 2 1 0 1 0 Receive Low Byte Host Receive Register (HORX) X:$FFFEC6 Read Only Reset = empty Host Transmit Data (usually loaded by program) 23 22 21 20 19 18 17 16 15 14 13 12 Transmit High Byte 11 10 Transmit Middle Byte 9 8 7 6 5 4 3 2 Transmit Low Byte
Programming Sheets Date: Application: Programmer: Sheet 2 of 6 HOST (HDI08) Host Receive Interrupt Enable 0 = Disable 1 = Enable if HRDF = 1 Host Transmit Interrupt Enable 0 = Disable 1 = Enable if HTDE = 1 Host Command Interrupt Enable 0 = Disable 1 = Enable if HCP = 1 Host Flag 2 Host Flag 3 Host DMA Control Bits See Table 6-5 in Section 6 Host Control Register (HCR) X:$FFFFC2 Read /Write Reset = $0 15 8 *0 *0 DSP Side 7 6 5 4 HDM2 HDM1 HDM0 HF3 3 HF2 2 1 0 HCIE HTIE HRIE * = Reserved,
Programming Sheets Date: Application: Programmer: Sheet 3 of 6 DSP Side HOST (HDI08) 15 8 7 *0 *0 Host Base Address Register (HBAR) X:$FFFFC5 Reset = $80 BA9 5 4 3 2 1 0 BA8 BA7 BA6 BA5 BA4 BA3 Host GPIO Port Enable 0 = GPIO Pins Disconnected 1 = GPIO Pin Enable Host Request Open Drain HDRQ HROD HREN/HEW 1 0 0 1 1 0 1 0 1 1 1 1 Host Address Line 8 Enable 0 Æ HA8 = GPIO, 1 Æ HA8 = HA8 Host Address Line 9 Enable 0 Æ HA9 = GPIO, 1 Æ HA9 = HA9 Host Data Strobe Polarity 0 = Strobe Acti
Programming Sheets Date: Application: Programmer: Sheet 4 of 6 HOST (HDI08) Processor Side Receive Request Enable DMA Off 0 = Interrupts Disabled DMA On 0 = Host -> DSP 1 = Interrupts Enabled 1 = DSP -> Host Transmit Request Enable DMA Off 0 = Interrupts Disabled DMA On 0 = DSP -> Host 1 = Interrupts Enabled 1 = Host -> DSP HDRQ 0 1 HOREQ/HTRQ HOREQ HTRQ HACK/HRRQ HACK HRRQ Host Flags Write Only Host Little Endian Initialize (Write Only) 0 = No Action 1 = Initialize DMA HDM[2:0] = 000 For HM[1:
Programming Sheets Date: Application: Programmer: Sheet 5 of 6 Processor Side HOST (HDI08) 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 Interrupt Vector Register (IVR) $3 R/W Reset = $0F Contains the interrupt vector or number Host Vector Contains Host Command Interrupt Address ÷ 2 Host Command Handshakes Executing Host Command Interrupts 7 6 5 4 3 2 1 0 HC HV6 HV5 HV4 HV3 HV2 HV1 HV0 Command Vector Register (CVR) $1 R/W Reset = $32 Contains the host command inter
Programming Sheets Date: Application: Programmer: Sheet 6 of 6 HOST (HDI08) Processor Side Host Receive Data (HLEND = 0) 7 0 7 Receive Low Byte 0 7 Receive Middle Byte 0 7 Not Used 0 $7 0 Receive High Byte $6 0 0 0 $5 0 0 0 0 $4 Host Receive Data (HLEND = 1) 7 0 7 Receive Low Byte 0 7 Receive Middle Byte 0 7 Not Used 0 $5 $6 Receive Byte Registers $7, $6, $5, $4 Read Only Reset = Empty 0 Receive High Byte 0 0 0 $7 0 0 0 0 $4 Receive Byte Registers Host Transmit Dat
Freescale Semiconductor HA6 HA5 HA4 HA3 0 9 8 7 6 5 4 3 2 1 0 0 *0 11 HDM7 10 0 8 7 6 5 4 3 2 1 0 HDM6HDM5HDM4HDM3HDM2HDM1HDM0 HRS CPOLCPHA 9 HCKR Divider Modulus as 0 *= Reserved, writeSHI Clock Control Register (HCKR) 0 0 CPOL CPHA Result 0 0 SCK active low, strobe on rising edge 0 1 SCK active low, strobe on falling edge 1 0 SCK active high, strobe on falling edge 1 1 SCK active high, strobe on rising edge HRS Result 0 Prescaler operational 1 Prescaler bypassed HFM1HFM0
D-28 SHI Host Receive 23 Data Register (HRX) X:$FFFF94 Read Only Reset = $xxxxxx SHI Host Transmit 23 Data Register (HTX) X:$FFFF93 Write Only Reset = $xxxxxx SHI 15 14 13 12 11 10 8 15 14 13 12 11 10 9 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Application: SHI Host Receive Data Register (HRX) (FIFO) 10 words deep 22 21 20 19 18 17 16 9 Host Receive Data Register Contents SHI Host Transmit Data Register (HTX) 22 21 20 19 18 17 16 Host Transmit Data Register Contents Programming Shee
Freescale Semiconductor ** = Reserved, write as 0 *0 21 20 19 HBUSY HBER HROE HRFF 23 22 SPI Mode Not Busy SS detected (Slave) -ORHTX/IOSR not empty (master) *0 18 17 HRNE *0 16 14 13 12 11 10 9 8 7 6 5 Slave mode Master mode 4 3 2 1 HI2C Result 0 SPI mode 1 I2C mode 0 HEN Description 0 SHI disabled 1 SHI enabled Description I2C Slave Clock Freeze Disabled I2C Slave Clock Freeze Enabled HTDE HTUEHRIE1HRIE0 HTIE HBIE HIDLE HRQE1 HRQE0 HMSTHFIF0HCKFR HM1 HM0 HI2C HEN 15 0 1 H
D-30 0 22 TFSD THCKD TCKD 21 20 Description TFSP 19 TCKP 18 TFP3 17 15 TFP2 TFP1 16 TFP0 14 TDC4 13 TDC3 12 TDC2 11 TDC1 10 Transmitter Clock Polarity set to clockout on rising edge of transmit clock, latch in on falling edge of transmit clock.
Description Freescale Semiconductor 22 TIE 23 0 1 Description 21 0 1 Transmitter Normal Operation 0 1 0 1 20 Zero Padding disabled 18 * 19 0 Description 16 15 14 13 12 11 10 9 0 1 8 Data shifted out MSB first 0 1 7 TE5 TE4 4 TE3 3 TE2 2 1 5 Transmitter disabled Transmitter enabled Description 0 6 TE [0:5] Data shifted out LSB first Description Data right aligned Data left aligned Description AC97 Reserved Network mode TSHFD 0 1 TWA 1 0 1 0 0 Networ
D-32 23 21 20 RHCKP 1 0 RFSP 19 RFSP 1 0 Description RCKP 18 16 15 RFP3 RFP2 RFP1 17 RFP0 14 RDC4 13 RDC3 12 11 RDC2 Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock Description Frame sync polarity negative Frame sync polarity positive RCKP 0 1 Description Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling ed
Freescale Semiconductor 22 21 20 19 18 16 RFSL 15 RSWS4 14 12 RSWS3 RSWS2 13 10 9 8 0 1 1 1 7 1 0 1 0 Network Mode Description 6 Rsvd Rsvd 4 RE3 3 0 RE0 1 RE1 2 RE2 Receiver enabled 1 5 Receiver disabled 0 Description Data shifted in LSB first 1 RE [0:3] Description Data shifted in MSB first 0 Data right aligned Data left aligned AC97 Reserved Network mode Normal mode RSHFD RWA 0 0 RMOD1 RMOD0 RSWS1 RSWS0 RMOD1 RMOD0 RWA RSHFD 11 1 17 Word-length fr
D-34 23 22 20 19 18 17 16 15 14 13 12 11 10 9 Description 7 TEBE ALC OF(2:0) SYN 6 Description 5 4 3 0 OF0 1 OF1 2 OF2 Holds data to send to OFn pin. See 8.3.5.1 to .3 Reserved Description Synchronous mode Asynchronous mode 8 0 1 Description Controls FSR pin. See 8.3.5.
Freescale Semiconductor Description 23 22 Reserved 21 20 Description 19 18 16 TEDE 17 TODE Transmit odd-data register empty Transmit odd-data register not empty Description 15 TDE 14 TUE 13 TFS 11 10 9 RODF REDF 8 Description 7 6 RFS 5 2 1 0 Description 4 3 0 IF0 1 IF1 2 IF2 Holds data sent from SCKR pin. See 8.3.6.1 Holds data sent from FSR pin. See 8.3.6.2 Holds data sent from HCKR pin. See 8.3.6.
D-36 23 22 21 20 18 17 16 15 14 13 1 0 1 0 1 EMUX1 EMUX2 EMUX2 EMUX3 EMUX3 10 0 EMUX1 11 1 EMUX0 12 0 EMUX0 EMUXR bit 9 8 7 6 disconnected 5 SDO3/SDI2 [PC8] disconnected SDO2/SDI3 [PC9] disconnected SDO1[PC10] disconnected SDO0 [PC11] ESAI pin 4 2 1 0 EMUX3 EMUX2 EMUX1 EMUX0 3 SDO3_1/SDI2_1 [PE8] disconnected SDO2_1/SDI3_1 [PE9] disconnected SDO1_1 [PE10] disconnected SDO0_1 [PE11] disconnected ESAI_1 pin Application: 19 Reserved Description ESAI_1 EMUX
0 Freescale Semiconductor 22 TFSD THCKD 20 THCKP 1 0 TFSP 19 TCKP 18 TFP3 17 15 TFP2 TFP1 16 TFP0 14 TDC4 13 TDC3 12 TDC2 11 TDC1 10 Transmitter Clock Polarity set to clockout on rising edge of transmit clock, latch in on falling edge of transmit clock.
D-38 Description 22 TIE 23 0 1 Description 21 0 1 Transmitter Normal Operation 0 1 20 Zero Padding disabled 0 1 18 * 19 0 Description 16 15 14 13 12 11 10 9 8 7 TE5 TE4 4 TE3 3 TE2 2 Transmitter enabled 1 5 Transmitter disabled Description 0 6 TE [0:5] Data shifted out LSB first Description Data shifted out MSB first 0 1 Data right aligned Data left aligned Description AC97 Reserved Network mode TSHFD 0 1 TWA 0 1 1 0 1 0 0 Network Mode Normal mode
Freescale Semiconductor 23 RFSD RCKD 20 RHCKP 1 0 19 RFSP 1 RCKP 18 16 15 RFP3 RFP2 RFP1 17 RFP0 14 RDC4 13 RDC3 12 11 RDC2 Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock Description Frame sync polarity negative RCKP 0 Description Frame sync polarity positive Reserved RFSP 0 1 Description Keep cleared for proper operation Internal clock source RHCKP 0 1 10
D-40 22 21 20 19 18 17 16 RFSL 15 RSWS4 14 12 RSWS3 RSWS2 13 10 9 8 1 1 7 0 1 1 0 Description 6 Rsvd Rsvd 4 RE3 3 0 RE0 1 RE1 2 RE2 1 5 Receiver disabled Receiver enabled 0 Description Data shifted in LSB first 1 RE [0:3] Description Data shifted in MSB first 0 Data right aligned Data left aligned AC97 Reserved Network mode Normal mode Network Mode RSHFD RSWS1 RSWS0 RMOD1 RMOD0 RWA RSHFD 11 Word-length frame sync 1 clock before beginning of data word firs
Freescale Semiconductor 23 22 20 19 18 17 16 15 14 13 12 11 10 9 Description 7 TEBE ALC OF(2:0) SYN 6 Description 5 4 3 0 OF0 1 OF1 2 OF2 Holds data to send to OFn pin. Reserved Description Synchronous mode Asynchronous mode 8 0 1 Description Controls FSR_1 pin.
D-42 Description 23 22 Reserved 21 20 Description 19 18 16 TEDE 17 TODE Transmit odd-data register empty Transmit odd-data register not empty Description 15 TDE 14 TUE 13 TFS 11 10 9 RODF REDF Description No receiver overrun error 6 RFS 7 ROE 5 3 0 IF0 1 IF1 2 IF2 Holds data sent from HCKR_1 pin. 2 4 Holds data sent from FSR_1 pin. Holds data sent from SCKR_1 pin.
Freescale Semiconductor *0 *0 *0 *0 *0 *0 *0 *0 XCB XUB XVB XCA XUA XVA 8 7 6 5 4 3 2 1 0 * 0 * *0 *0 *0 *0 *0 0 *0 *0 *0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Channel B Validity (XVB) Channel B User Data (XUB) Channel A Validity (XVA) Channel A User Data (XUA) DAX Non-Audio Data Register (XNADR) X:$FFFFD1 Reset = $00XX00 DAX Programming Sheets Application: Date: Programmer: Sheet 1 of 2 Figure D-28.
D-44 1 0 1 1 1 6 8 5 4 3 * = Reserved; write as 0 2 7 1 5 4 3 2 0 XBLK XAURXADE 1 XADE DAX Audio Data Empty 0 Register(s) full 1 Register(s) empty 6 0 XSB XCS1 XCS0 XBIE XUIE XDIE XAUR DAX Underrun error 0 No error 1 Underrun error 7 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 XBLK DAX Block transfer 0 not last frame 1 191st frame transmission 8 ACI Pin, f = 512 x fs ACI Pin, f = 384 x fs ACI Pin, f = 256 x fs DSP Co
Programming Sheets Date: Application: Programmer: Sheet 1 of 3 TEC PS (1:0) 00 01 10 11 Prescaler Clock Source Internal CLK/2 TIO0 Reserved Reserved 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 PS1 PS0 8 7 6 5 4 3 2 1 0 Prescaler Preload Value (PL [0:20]) * = Reserved, Program as 0 Timer Prescaler Load Register TPLR:$FFFF83 Read/Write Reset = $000000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 *0 *0 8 7 6 5 4 3 2 1 0 Current Value of Prescaler Counter (PC [0:20]) Time
Programming Sheets Date: Application: Programmer: Sheet 2 of 3 TEC Inverter Bit 8 0 = 0- to-1 transitions on TIO input increment the counter, or high pulse width measured, or high pulse output on TIO 1 = 1-to-0 transitions on TIO input increment the counter, or low pulse width measured, or low pulse output on TIO Timer Reload Mode Bit 9 0 = Timer operates as a free running counter TC (3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 = Timer is reloaded when selec
Programming Sheets Date: Application: Programmer: Sheet 3 of 3 TEC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Timer Reload Value Timer Load Register TLR0:$FFFF8E Write Only TLR1:$FFFF8A Write Only TLR2:$FFFF86 Write Only Reset = $XXXXXX 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Value Compared to Counter Value Timer Compare Register TCPR0:$FFFF8D Read/Write TCPR1:$FFFF89 Read/Write TCPR2:$FFFF85 Read/Write Reset = $XXXXX
Programming Sheets Date: Application: Programmer: Sheet 1 of 4 GPIO Host Data Direction Register (HDDR) Port B (HDI08) 15 DR15 14 13 12 11 10 DR14 DR13 DR12 DR11 DR10 9 8 7 6 5 4 3 2 1 0 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 X:$FFFFC8 Read/Write Reset = $0 DRx = 1 → PBx is Output Host Data Register (HDR) DRx = 0 → PBx is Input 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X:$FFFFC9 Read/Wri
Programming Sheets Date: Application: Programmer: Sheet 2 of 4 GPIO Port C (ESAI) Port C Control Register (PCRC) X:$FFFFBF Read/Write Reset = $0 Port C Direction Register (PRRC) X:$FFFFBE Read/Write Reset = $0 23 *0 3 11 10 9 8 7 6 5 4 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 2 1 PC3 PC2 PC1 0 PC0 * = Reserved, Program as 0 23 *0 11 10 9 PDC11 PDC10 PDC9 8 7 6 5 PDC8 PDC7 PDC6 PDC5 4 3 2 1 0 PDC4 PDC3 PDC2 PDC1 PDC0 * = Reserved, Program as 0 PCn = 0 & PDCn = 0 -> Po
Programming Sheets Date: Application: Programmer: Sheet 3 of 4 GPIO Port D (DAX) Port D Control Register (PCRD) X:$FFFFD7 Read/Write Reset = $0 23 6 5 4 3 2 *0 *0 *0 *0 *0 *0 1 0 PC1 PC0 1 0 * = Reserved, Program as 0 Port D Direction Register (PRRD) X:$FFFFD6 Read/Write Reset = $0 23 6 5 4 3 2 *0 *0 *0 *0 *0 *0 PDC1 PDC0 * = Reserved, Program as 0 PCn = 0 & PDCn = 0 -> Port pin PDn disconnected PCn = 1 & PDCn = 0 -> Port pin PDn configured as input PCn = 0 & PDCn = 1 -> Port p
Programming Sheets Date: Application: Programmer: Sheet 4 of 4 GPIO Port E (ESAI_1) Port E Control Register (PCRE) Y:$FFFF9F Read/Write Reset = $0 Port E Direction Register (PRRE) Y:$FFFF9E Read/Write Reset = $0 23 *0 11 10 9 8 7 6 PC11 PC10 PC9 PC8 PC7 PC6 5 3 4 *0 PC4 2 *0 PC3 1 PC1 0 PC0 * = Reserved, Program as 0 23 *0 11 PDC11 10 PDC10 9 8 PDC9 PDC8 7 PDC7 6 5 4 *0 PDC6 3 PDC4 PDC3 2 1 *0 0 PDC1 PDC0 * = Reserved, Program as 0 PCn = 0 & PDCn = 0 -> Port
Programming Sheets NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev.
Index Numerics 5 V tolerance 1 A adder modulo 5 offset 5 reverse-carry 5 address bus 1 Address Generation Unit 5 addressing modes 5 AES/EBU 10, 1 AGU 5 B barrel shifter 4 bus external address 5 external data 5 bus control 1 buses internal 6 C Central Processing Unit (CPU) i CLKGEN 7 Clock 4 clock 1 Clock divider 11 Clock Generator (CLKGEN) 7 CP-340 10, 1 CPHA and CPOL (HCKR Clock Phase and Polarity Controls) 7 D data ALU 4 registers 4 data bus 1 Data Output bit (DO) 10 DAX 1, 21 Block Transferred Inter
triggered by timer 21 DO bit 10 DO loop 6 DRAM 8 DSP56300 core 2 DSP56300 Family Manual i, 2 DSP56303 Technical Data i E Enhanced Serial Audio Interface 15, 19 Enhanced Synchronous Audio Interface 1 ESAI 1, 15, 19 ESAI block diagram 1 ESSI0 (GPIO) 1, 2 ESSI1 (GPIO) 1 external address bus 5 external bus control 5, 6, 7 external data bus 5 External Memory Expansion Port 5 F functional signal groups 1 G Global Data Bus 6 GPIO 9, 22 GPIO (ESSI0, Port C) 1, 2 GPIO (ESSI1, Port D) 1 GPIO (HI08, Port B) 1 GPIO
Transmit Data In Master Mode 24 Transmit Data In Slave Mode 22 I2C Bus Acknowledgment 18 I2C Mode 1 IEC958 10, 1 Inter Integrated Circuit Bus 10, 1 internal buses 6 Internal Exception Priorities SHI 5 interrupt 6 interrupt and mode control 1, 7, 8 interrupt control 7, 8 Interrupt Vectors SHI 5 INV 9 J JTAG 7, 22 JTAG/OnCE port 1 L LA register 6 LC register 6 Loop Address register (LA) 6 Loop Counter register (LC) 6 M MAC 4 Manual Conventions ii memory expansion 8 external expansion port 8 off-chip 8 on-c
R reserved bits in TCSR register bits 3, 10, 14, 16–19, 22, 23 11 in TPCR 6 in TPLR 6 RESET 8 reverse-carry adder 5 S SC register 6 Serial Host Interface 1, 12 Serial Host Interface (SHI) 10, 1 Serial Peripheral Interface Bus 10, 1 SHI 10, 1, 12, 1 Block Diagram 2 Clock Control Register—DSP Side 7 Clock Generator 2, 3 Control/Status Register—DSP Side 10 Data Size 11 Exception Priorities 5 HCKR Clock Phase and Polarity Controls 7 Divider Modulus Select 9 Prescaler Rate Select 9 HCKR Filter Mode 9 HCSR Bus E
TC0–TC3 bits 7 TCF 11 TCIE bit 7 TCPR 12 TCR 12 TCSR register 6 bit 0—Timer Enable bit (TE) 6 bit 2—Timer Compare Interrupt Enable bit (TCIE) 7 bits 4–7—Timer Control bits (TC0–TC3) 7 bit 13—Data Output bit (DO) 10 reserved bits—bits 3, 10, 14, 16–19, 22, 23 11 TE bit 6 Test Access Port (TAP) 7 Timer 1, 22 timer special cases 20 Timer (GPIO) 2 Timer Compare Interrupt Enable bit (TCIE) 7 Timer Control bits (TC0–TC3) 7 Timer Control/Status Register (TCSR) 6 Timer Enable bit (TE) 6 timer mode mode 0—GPIO 13 mo
DSP56366 24-Bit Digital Signal Processor, Rev.
