Stereo System - Digital Audio Signal Processor User Manual

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor Index-3
P
PAB 1-7
PAG 1-6
PC register 1-6
PCU 1-6
PDB 1-7
PDC 1-6
Peripheral I/O Expansion Bus 1-6
Peripheral modules 1-3
Peripherals (IPR-P) C-12
Phase Lock Loop Control Register (PCTL) C-13
PIC 1-6
PLL 1-7, 2-4
PLL Pre-Divider Factor (PD0-PD3) 4-8
Port A 2-4
Port B Registers (PCRB, PRRB, PDRB) C-23
Port C 2-10
Port C Registers (PCRC, PRRC, PDRC) C-24
Power 2-2
Priority 4-2
priority mechanism 4-2
Processor Architecture 1-3
Program Address Bus (PAB) 1-7
Program Address Generator (PAG) 1-6
Program Control Unit (PCU) 1-6
Program Counter register (PC) 1-6
Program Data Bus (PDB) 1-7
Program Decode Controller (PDC) 1-6
Program Interrupt Controller (PIC) 1-6
Program Memory Expansion Bus 1-6
program RAM 3-1
Program ROM 1-8
Programming Model
SHI—DSP Side
7-4
SHI—Host Side 7-3
R
Related publications 1-1
RESET 2-7
reverse-carry adder
1-5
ROM
bootstrap
3-2
S
SC register 1-6
Serial Audio Interface (ESAI) 1-3
Serial Host Interface 2-7
Serial Host Interface (SHI) 1-3, 7-1
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus
7-1
SHI 2-7, 7-1
Block Diagram 7-2
Clock Control Register—DSP Side 7-7
Clock Generator 7-3
Control/Status Register—DSP Side 7-10
Data Size 7-11
Exception Priorities 7-5
HCKR
Clock Phase and Polarity Controls
7-7
Divider Modulus Select 7-9
Prescaler Rate Select 7-9
HCKR Filter Mode 7-9
HCSR
Bus Error Interrupt Enable
7-13
FIFO Enable Control 7-12
Host Request Enable 7-12
Idle 7-13
Master Mode 7-12
Serial Host Interface I
2
C/SPI Selection 7-11
Serial Host Interface Mode 7-11
SHI Enable 7-10
Host Receive Data FIFO—DSP Side 7-6
Host Transmit Data Register—DSP Side 7-6
HREQ
Function In SHI Slave Modes
7-12
HSAR
I
2
C Slave Address 7-7
Slave Address Register 7-6
I/O Shift Register 7-6
Input/Output Shift Register—Host Side 7-5
Internal Architecture 7-2
Internal Interrupt Priorities 7-5
Interrupt Vectors 7-5
Introduction 7-1
Operation During Stop 7-25
Programming Considerations 7-20
Programming Model 7-3
Programming Model—DSP Side 7-4
Programming Model—Host Side 7-3
Slave Address Register—DSP Side 7-6
SHI Host Control/Status Register (HCSR) C-16
SHI Host Transmit Data Register (HTX) C-15
SHI Noise Reduction Filter Mode 7-10
SHI Slave Address (HSAR) C-14
signal groupings 2-1
signals 2-1