DSP56364 24-Bit Digital Signal Processor Users Manual Document Number: DSP56364UM Rev.
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.
Contents Manual Conventions 1 Overview 1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Audio Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 Core Description . . . . .
3 Memory Configuration 3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1.1 Program RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1.2 Program ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Input/Output Port (GPIO) 5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 GPIO Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Port B Control Register (PCRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 PCRB Control Bits (PC[3:0]) - Bits 3-0 . . . . . . . .
.3.2.4 6.3.2.5 6.3.2.6 6.3.2.7 6.3.2.8 6.3.2.9 6.3.2.10 6.3.2.11 6.3.2.12 6.3.2.13 6.3.2.14 6.3.2.15 6.3.2.16 6.3.2.17 6.3.2.18 6.3.2.19 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.4 6.3.3.5 6.3.3.6 6.3.3.7 6.3.3.8 6.3.3.9 6.3.3.10 6.3.4 6.3.4.1 6.3.4.2 6.3.4.3 6.3.4.4 6.3.4.5 6.3.4.6 6.3.4.7 6.3.4.8 6.3.4.9 6.3.4.10 6.3.4.11 6.3.4.12 6.3.4.13 6.3.4.14 6.3.4.15 6.3.4.16 6.3.5 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.
6.6.2 6.6.3 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 7 Serial Host Interface 7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Serial Host Interface Internal Architecture . . . . . . . . . . . . . . . . . .
7.6.2 I2C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BookTitle, Rev.
List of Figures Figure 1-1 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 4-1 Figure 4-2 Figure 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 6-11 Figure 6-12 Figure 6-13 Figure 6-14 Figure 6-15 Figure 6-16 Figure 6-17 Figure 6-18 Figure 6-19 Figure 6-20 Figure 6-21 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-1
Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure C-6 Figure C-7 C-15 Figure C-8 Figure C-9 Figure C-10 Figure C-11 Figure C-12 Figure C-13 Figure C-14 Figure C-15 Figure C-16 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 Interrupt Priority Register-Core (IPR-C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 Interrupt Priority Register- Peripherals (IPR-P) . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 5-1 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table C-1 Table C-2 Table C-3 DSP56364 Functional Signal Groupings . . . . . . .
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
Preface This manual contains the following sections and appendices. SECTION 1—DSP56364 OVERVIEW • Provides a brief description of the DSP56364, including a features list and block diagram. Lists related documentation needed to use this chip and describes the organization of this manual. SECTION 2—SIGNAL/CONNECTION DESCRIPTIONS • Describes the signals on the DSP56364 pins and how these signals are grouped into interfaces.
Manual Conventions The following conventions are used in this manual: • Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). • When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case.
— the reset instruction, written as “RESET,” — the reset operating state, written as “Reset,” and — the reset function, written as “reset.” DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
1 1.1 Overview Introduction The DSP56364 24-Bit Digital Signal Processor, a new audio digital signal processor based on the 24-bit DSP56300 architecture, is targeted to applications that require digital audio signal processing such as sound field processing, acoustic equalization and other digital audio algorithms. The DSP56364 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms.
Features ESAI GPIO 5 SHI PM_EB ADDRESS GENERATION UNIT 0.5K x 24 PROGRAM ROM 8K x 24 BootstrapROM 192x24 PIO_EB PERIPHERAL EXPANSION AREA PROGRAM RAM YAB XAB PAB DAB SIX CHANNELS DMA UNIT X MEMORY RAM 1KX24 YMEMORY RAM 1.
Audio Processor Architecture • • • • 1.3 — Very low-power CMOS design, fully static design with operating frequencies down to DC. — STOP and WAIT low-power standby modes. On-chip Memory Configuration — 1.5K × 24 Bit Y-Data RAM. — 1K × 24 Bit X-Data RAM. — 8K × 24 Bit Program ROM. — 0.5K × 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM. — 0.75K × 24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25K × 24 Bit of Program RAM.
Core Description 1.4 Core Description The DSP56364 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Freescale's popular DSP56000 core family while retaining code compatibility with it.
DSP56300 Core Functional Blocks 1.5.1.1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator.
DSP56300 Core Functional Blocks 1.5.3 Program Control Unit (PCU) The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core.
DSP56300 Core Functional Blocks • • • • • • • • • • Y memory expansion bus (YM_EB) to Y memory Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and PCU as well as the memory-mapped registers in the peripherals DMA data bus (DDB) for carrying DMA data between memories and/or peripherals DMA address bus (DAB) for carrying DMA addresses to memories and peripherals Program Data Bus (PDB) for carrying program data throughout the core X memory Data Bus (XDB) for carrying X data throughou
Data and Program memory 1.5.7 JTAG TAP and OnCE Module The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards led to developing this standard under the sponsorship of the Test Technology Committee of IEEE and JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this standard.
Internal I/O Memory Map memory switch can be accomplished provided that the affected address ranges are not being accessed during the instruction cycle in which the switch operation takes place. Accordingly, the following condition must be observed for trouble-free dynamic switching: NOTE No accesses (including instruction fetches) to or from the affected address ranges in program and data memories are allowed during the switch cycle.
Status Register (SR) 1.8 Status Register (SR) Refer to the DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale publication DSP56300FM/AD for a description of the Status Register bits. The Cache Enable bit (Bit 19) in the Status Register must be kept cleared since the DSP56364 does not have an on-chip instruction cache. DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
2 Signal/Connection Descriptions 2.1 Signal Groupings The input and output signals of the DSP56364 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.
Signal Groupings OnCE ON-CHIP EMULATION/ JTAG PORT PORT A ADDRESS BUS TDI TCK TDO TMS A0-A17 VCCA (4) GNDA (4) DSP56364 PORT A DATA BUS D0-D7 VCCD (1) Port B GPIO PB0-PB3 GNDD (1) PORT A BUS CONTROL AA0-AA1/RAS0-RAS1 CAS RD WR TA VCCC (1) GNDC (1) RESERVED (4) SERIAL AUDIO INTERFACE (ESAI) Port C INTERRUPT AND MODE CONTROL MODA/IRQA MODB/IRQB MODD/IRQD RESET PLL AND CLOCK PINIT/NMI PCAP VCCP GNDP EXTAL SCKT [PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0 [PC11] SDO1 [PC10] SDO2
Power 2.2 Power Table 2-2 Power Inputs Power Name Description VCCP PLL Power—VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. VCCQL (4) Quiet Core (Low) Power—VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
Clock and PLL Table 2-3 Grounds (continued) Ground Name Description GNDC (1) Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDC connections. GNDS (3) SHI and ESAI —GNDS is an isolated ground for the SHI and ESAI. This connection must be tied externally to all other chip ground connections.
External Memory Expansion Port (Port A) 2.5.2 External Data Bus Table 2-6 External Data Bus Signals Signal Name Signal Type State during Reset D0–D7 Input/Output Tri-stated 2.5.3 Signal Description Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. D0–D7 are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode.
Interrupt and Mode Control Table 2-7 External Bus Control Signals (continued) Signal Name Signal Type State during Reset RD Output Tri-stated Read Enable—RD is an active-low output that is asserted to read external memory on the data bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. WR Output Tri-stated Write Enable— WR is an active-low output that is asserted to write external memory on the data bus.
Serial Host Interface Table 2-8 Interrupt and Mode Control Signal Name Signal Type State during Reset MODA/IRQA Input Input Signal Description Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing.
Serial Host Interface . Table 2-9 Serial Host Interface Signals Signal Name Signal Type SCK Input or output SCL Input or output State during Reset Tri-stated Signal Description SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator.
Serial Host Interface Table 2-9 Serial Host Interface Signals (continued) Signal Name Signal Type MOSI Input or output HA0 Input State during Reset Tri-stated Signal Description SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave.
Enhanced Serial Audio Interface 2.8 Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals Signal Name Signal Type HCKR Input or output PC2 Input, output, or disconnected State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver—When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock.
Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type FST Input or output PC4 Input, output, or disconnected State during Reset GPIO disconnected Signal Description Frame Sync for Transmitter—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only.
Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SDO5 Output SDI0 Input PC6 Input, output, or disconnected State during Reset Signal Description GPIO disconnected Serial Data Output 5—When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register.
JTAG/OnCE Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SDO1 Output PC10 Input, output, or disconnected State during Reset Signal Description GPIO disconnected Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C 10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected.
GPIO Signals 2.10 GPIO Signals Table 2-12 GPIO Signals Signal Name Signal Type GPIO0GPIO3 Input, output or disconnected State during Reset disconnected Signal Description GPIO0-3- The General Purpose I/O pins are used for control and handshake functions between the DSP and external circuitry. Each Port B GPIO pin may be individually programmed as an input, output or disconnected DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
3 Memory Configuration 3.1 Memory Spaces The DSP56364 provides the following three independent memory spaces: • Program • X data • Y data Each memory space uses (by default) 18 external address lines for addressing, allowing access to 256K of external memory when using the SRAM operating mode, and 16 M when using the DRAM operating mode. Program and data word length is 24 bits, and internal memory uses 24-bit addressing.
Memory Spaces Customer code should not use this area. The contents of this program ROM segment is defined by the bootstrap ROM source code in Appendix A, "Bootstrap ROM". 3.1.1.3 Bootstrap ROM The bootstrap code is accessed at addresses $FF0000 to $FFF0BF (192 words) in program memory space. The bootstrap ROM is factory-programmed to perform the bootstrap operation following hardware reset. The bootstrap ROM can not be accessed in 16-bit address compatibility mode.
Memory Space Configuration 3.1.2.2 X Data RAM The on-chip X data RAM consists of 24-bit wide, high-speed, internal static RAM occupying 1K locations in the X memory space. The X data RAM organization is 4 banks of 256 24-bit words. 3.1.2.
Internal Memory Configuration Table 3-2 Internal Memory Configurations Bit Settings Memory Sizes (24-bit words) MS SC Prog. RAM Prog. ROM Boot ROM X Data RAM Y Data RAM 0 0 0.5K 8K 192 1K 1.5K 1 0 1.25K 8K 192 1K 0.75K 0 1 0.5K n.a. n.a. 1K 1.5K 1 1 1.25K n.a. n.a. 1K 0.75K Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-4. 3.3.
Internal Memory Configuration 3.3.3 Dynamic Memory Configuration Switching The internal memory configuration is altered by remapping RAM modules from Y data memory into program memory space and vice-versa. The contents of the switched RAM modules are preserved. The memory can be dynamically switched from one configuration to another by changing the MS bit in OMR. The address ranges that are directly affected by the switch operation are specified in Table 3-3.
Memory Maps 3.4 Memory Maps PROGRAM $FFFFFF X DATA $FFFFFF INTERNAL RESERVED $FFFF80 $FF3000 8K INTERNAL $FF1000 $FF00C0 $FF0000 $FFF000 Y DATA $FFFFFF INTERNAL I/O (128 words) $FFFF80 EXTERNAL EXTERNAL $FFF000 INTERNAL RESERVED ROM INTERNAL RESERVED INTERNAL RESERVED $FF0000 BOOT ROM EXTERNAL I/O (128 words) $FF0000 EXTERNAL EXTERNAL EXTERNAL $000600 $000400 $000200 1K INTERNAL 0.5K INTERNAL $000000 RAM $000000 1.
Memory Maps PROGRAM $FFFF X DATA $FFFF $FF80 Y DATA $FFFF INTERNAL I/O (128 words) EXTERNAL I/O (128 words) $FF80 EXTERNAL EXTERNAL EXTERNAL $0600 $0400 $0200 $0000 0.5K INTERNAL 1K INTERNAL RAM RAM $0000 1.5K INTERNAL RAM $0000 Figure 3-3 Memory Maps for MS=0, SC=1 PROGRAM $FFFF X DATA $FFFF $FF80 INTERNAL I/O (128 words) Y DATA $FFFF $FF80 EXTERNAL EXTERNAL I/O (128 words) EXTERNAL EXTERNAL $0500 $0400 $0300 1.25K INTERNAL 1K INTERNAL RAM RAM $0000 $0000 0.
External Memory Support 3.5 External Memory Support The DSP56364 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale publication DSP56300FM/AD. Note that the DSP56364 has only an 8-bit data bus. This means that no instruction fetches from external memory are possible, and care should be taken to ensure that no program memory instruction fetch access occurs in the external memory space.
4 4.1 Core Configuration Introduction This chapter contains DSP56300 core configuration information details specific to the DSP56364. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA request sources • OMR • PLL control register • AA control registers • JTAG BSR For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM). 4.
Operating Mode Register (OMR) APD 11 10 9 8 7 6 5 4 3 2 1 0 MA ATE 12 MB XYS 13 MC 14 MD 15 EBD 16 SD 17 MS 18 COM CDP1:0 19 TAS 20 EUN 21 EOV 22 WRP 23 EOM SEN SCS ATE - Address Tracing Enable MS - Memory Switch Mode APD - Address Priority Disable SD - Stop Delay EBD - External Bus Disable MD - Operating Mode D MC - Operating Mode C - Always set.
Operating Modes 4.3 Operating Modes The operating modes are as shown in Table 4-1 The operating modes are latched from MODA, MODB and MODD pins during reset. Each operating mode is briefly described below. The operation of all bootstrap modes is defined by the Bootstrap ROM source code in Appendix A, "Bootstrap ROM".
Bootstrap Program address to start loading the program words and then a 24-bit word for each program word to be loaded. The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started. Mode E Same as mode 5, except the SHI interface operates in the I2C slave mode with clock freeze enabled.
Interrupt Priority Registers The interrupt vectors are shown in Table C-2 and the interrupt priorities are shown in Table C-3 in Appendix C, "Programmer’s Reference". Table 4-2 Interrupt Priority Level Bits IPL bits Interrupts Enabled Interrupt Priority Level xxL1 xxL0 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
Interrupt Priority Registers 11 10 9 8 7 6 5 4 3 2 1 0 SHL1 SHL0 ESL1 ESL0 ESAI IPL SHI IPL reserved reserved reserved reserved 22 23 21 20 19 18 17 16 15 14 13 12 reserved Reserved bit. Read as zero, should be written with zero for future compatibility.
DMA Request Sources 4.6 DMA Request Sources The DMA Request Source bits (DRS0-DRS4 bits in the DMA Control/Status registers) encode the source of DMA requests used to trigger the DMA transfers. The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA, IRQB and IRQD pins. The DMA Request Sources are shown in Table 4-3. Table 4-3 DMA Request Sources DMA Request Source Bits DRS4...
Device Identification (ID) Register 4.7.2 Crystal Range Bit (XTLR) - Bit 15 The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip crystal oscillator is not used on the DSP56364 since no XTAL pin is available. The XTLR bit is set to zero during hardware reset in the DSP56364. 4.7.3 XTAL Disable Bit (XTLD) - Bit 16 The XTAL Disable Bit (XTLD) is set to 1 (XTAL disabled) during hardware reset in the DSP56364. 4.7.
JTAG Boundary Scan Register (BSR) 4.10 JTAG Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56364 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register.
JTAG Boundary Scan Register (BSR) Table 4-6 DSP56364 BSR Bit Definition (continued) Bit # Pin Name Pin Type BSR Cell Type A12 Output3 A[17:9] Bit # Pin Name Pin Type BSR Cell Type Data SDO2/SDI3 - Control - Control SDO2/SDI3 Input/Output Data A11 Output3 Data SDO1 - Control A10 Output3 Data SDO1 Input/Output Data A9 Output3 Data SDO0 - Control A8 Output3 Data SDO0 Input/Output Data A7 Output3 Data HCKR - Control A[8:0] - Control HCKR Input/Output Data
5 5.1 General Purpose Input/Output Port (GPIO) Introduction The General Purpose Input/Output (GPIO) pins are used for control and handshake functions between the DSP and external circuitry. The GPIO port has 4 I/O pins (GPIO0-GPIO3) that are controlled through a set of memory-mapped registers. Each GPIO pin may be individually programmed as an output or as an input. 5.
GPIO Programming Model 7 6 5 4 3 2 1 0 PDC3 PDC2 PDC1 PDC0 PRRB X:$FFFFCE 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved, read as zero, should be written with zero for future compatibility Figure 5-2 GPIO Port B Direction Register (PRRB) 7 6 5 4 3 2 1 0 PD3 PD2 PD1 PD0 PDRB X:$FFFFCD 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved, read as zero, should be written with zero for future compatibility Figure 5-3 GPIO Port B Data Registe
GPIO Programming Model Port B Direction Register (PRRB) The read/write Port B Direction Register controls the direction of data transfer for each GPIO pin. 5.2.1.3 PRRB Direction Bits (PDC[3:0]) - Bits 3-0 When PDC[i] is set, the GPIO port pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input. See Table 5-1. Hardware and software reset clear the PDC[3:0] bits. 5.2.1.4 PRRB Reserved Bits - Bits 23-4 These bits are reserved and unused.
GPIO Programming Model NOTES DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
6 6.1 Enhanced Serial AUDIO Interface (ESAI) Introduction The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Freescale SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator.
Introduction GDB DDB TX0 RSMA SDO0 [PC11] RSMB Shift Register TSMA TX1 TSMB SDO1 [PC10] Shift Register RCCR TX2 RCR SDO2/SDI3 [PC9] Shift Register TCCR RX3 TCR TX3 SDO3/SDI2 [PC8] SAICR Shift Register SAISR RX2 TX4 TSR SDO4/SDI1 [PC7] Shift Register RX1 Clock / Frame Sync Generators and Control Logic SDO5/SDI0 [PC6] Shift Register [PC2] HCKR [PC1] FSR [PC0] SCKR [PC5] HCKT [PC4] FST TCLK [PC3] SCKT TX5 RCLK RX0 Figure 6-1 ESAI Block Diagram DSP56364 24-Bit Digital Signal P
ESAI Data and Control Pins 6.2 ESAI Data and Control Pins Three to twelve pins are required for operation, depending on the operating mode selected and the number of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The SDO2/SDI3, SDO3/SDI2, SDO4/SDI1, and SDO5/SDI0 pins are shared by transmitters 2 to 5 with receivers 0 to 3. The actual mode of operation is selected under software control.
ESAI Data and Control Pins 6.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3 shift register.
ESAI Data and Control Pins When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections.
ESAI Data and Control Pins Table 6-2 Transmitter Clock Sources THCKD TFSD TCKD Transmitter Bit Clock Source 0 0 0 SCKT 0 0 1 HCKT 0 1 0 SCKT FST 0 1 1 HCKT FST 1 0 0 SCKT HCKT 1 0 1 INT HCKT 1 1 0 SCKT HCKT FST 1 1 1 INT HCKT FST OUTPUTS SCKT SCKT SCKT SCKT SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT function is not being used.
ESAI Programming Model 6.2.10 Frame Sync for Transmitter (FST) FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see Table 6-2). The direction of this pin is determined by the TFSD bit in the TCR register. When configured as an output, this pin is the internally generated frame sync signal.
ESAI Programming Model special-purpose time slot register. The following paragraphs give detailed descriptions and operations of each bit in the ESAI registers. The ESAI pins can also function as GPIO pins (Port C), described in Section 6.5, "GPIO - Pins and Registers". 6.3.
ESAI Programming Model RHCKD=1 FOSC DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 DIVIDER DIVIDE BY 1 TO DIVIDE BY 16 RPM0 - RPM7 RFP0 - RFP3 RHCKD=0 RPSR HCKR RHCKD FLAG0 OUT (SYNC MODE) FLAG0 IN (SYNC MODE) INTERNAL BIT CLOCK RSWS4-RSWS0 RX WORD LENGTH DIVIDER SYN=1 RX WORD CLOCK SYN=0 SCKR RX SHIFT REGISTER RCLOCK SYN=0 RCKD TSWS4-TSWS0 SYN=1 TCLOCK INTERNAL BIT CLOCK SCKT TX WORD LENGTH DIVIDER TX WORD CLOCK TCKD TX SHIFT REGISTER THCKD HC
ESAI Programming Model operational (see Figure 6-3). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. NOTE Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes synchronization problems when using the internal DSP clock as source (TCKD=1 or THCKD=1). 6.3.1.
ESAI Programming Model RX WORD CLOCK RDC0 - RDC4 RFSL RECEIVER FRAME RATE DIVIDER SYNC TYPE INTERNAL RX FRAME CLOCK RFSD SYN=0 RFSD=1 SYN=0 RECEIVE CONTROL LOGIC FSR RECEIVE FRAME SYNC RFSD=0 SYN=1 SYN=1 TDC0 - TDC4 TFSL FLAG1 IN (SYNC MODE) FLAG1OUT (SYNC MODE) TFSD TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC SYNC TYPE INTERNAL TX FRAME CLOCK FST TRANSMIT FRAME SYNC Figure 6-4 ESAI Frame Sync Generator Functional Block Diagram 6.3.1.
ESAI Programming Model 6.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock.
ESAI Programming Model 6.3.2 ESAI Transmit Control Register (TCR) The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register. See Figure 6-5.
ESAI Programming Model In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE1 can be left enabled. 6.3.2.
ESAI Programming Model transmitter #4 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift register #4. The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cleared and RE1 in the RCR register is set. If both RE1 and TE4 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE1 and TE4 should not be set at the same time.
ESAI Programming Model Since the data word is shorter than the slot length, the data word is extended until achieving the slot length, according to the following rule: 1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted. 2.
Freescale Semiconductor DATA SLOT 0 SLOT 1 SLOT 0 DATA RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET SLOT 2 TRANSMITTER INTERRUPTS (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and a word may be transferred at every time slot. SERIAL DATA FRAME SYNC SERIAL Network Mode RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET TRANSMITTER INTERRUPT (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and data is transferred once per frame sync.
ESAI Programming Model 6.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table 6-5. See also the ESAI data path programming model in Figure 6-13 and Figure 6-14.
ESAI Programming Model Table 6-5 ESAI Transmit Slot and Word Length Selection (continued) 6.3.2.11 TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 SLOT LENGTH WORD LENGTH Reserved TCR Transmit Frame Sync Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized.
ESAI Programming Model WORD LENGTH: TFSL=0, RFSL=0 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA NOTE: Frame sync occurs while data is valid. ONE BIT LENGTH: TFSL=1, RFSL=1 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA NOTE: Frame sync occurs for one bit time preceding the data.
ESAI Programming Model 6.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync starts one serial clock cycle earlier (i.e together with the last bit of the previous data word). 6.3.2.
ESAI Programming Model 6.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data interrupts. If TEDIE is set, the transmit even slot data interrupts are enabled. If TEDIE is cleared, the transmit even slot data interrupts are disabled. A transmit even slot data interrupt request is generated if TEDIE is set and the TEDE status flag in the SAISR status register is set.
ESAI Programming Model X:$FFFFB8 11 10 9 8 7 6 5 4 3 2 1 0 RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0 23 22 21 20 19 18 17 16 15 14 13 12 RCKP RFP3 RFP2 RFP1 RFP0 RDC4 RDC3 RHCKD RFSD RCKD RHCKP RFSP Figure 6-8 RCCR Register Hardware and software reset clear all the bits of the RCCR register. 6.3.3.
ESAI Programming Model The ESAI frame sync generator functional diagram is shown in Figure 6-4. 6.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17 The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock.
ESAI Programming Model 6.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the synchronous mode (SYN=1). In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the receive shift registers and word length divider, and is the output on the SCKR pin.
ESAI Programming Model Table 6-8 FSR Pin Definition Table Control Bits FSR Pin 6.3.3.10 SYN TEBE RFSD 0 X 0 FSR input 0 X 1 FSR output 1 0 0 IF1 1 0 1 OF1 1 1 0 reserved 1 1 1 Transmitter Buffer Enable RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag direction in the synchronous mode (SYN=1).
ESAI Programming Model receivers can be enabled) if the input data pin is not used by a transmitter. Operating modes are also selected in this register. 11 X:$FFFFB7 10 9 8 RSWS1 RSWS0 RMOD RMOD 7 6 RWA RSHFD 18 23 22 21 20 19 RLIE RIE REDIE REIE RPR 5 17 4 16 RFSR 3 2 1 0 RE3 RE2 RE1 RE0 15 14 13 12 RFSL RSWS4 RSWS3 RSWS2 Reserved bit - read as zero; should be written with zero for future compatibility.
ESAI Programming Model 6.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled and samples data at the SDO2/SDI3 pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1). When RE3 is cleared, receiver 3 is disabled by inhibiting data transfer into RX3. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX3 data register.
ESAI Programming Model Table 6-10 ESAI Receive Network Mode Selection 6.3.4.9 RMOD1 RMOD0 RDC4-RDC0 Receiver Network Mode 0 0 $0-$1F Normal Mode 0 1 $0 On-Demand Mode 0 1 $1-$1F Network Mode 1 0 X Reserved 1 1 $0C AC97 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14 The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI. The word length must be equal to or shorter than the slot length.
ESAI Programming Model Table 6-11 ESAI Receive Slot and Word Length Selection (continued) 6.3.4.
ESAI Programming Model 6.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 The RPR control bit is used to put the receiver section of the ESAI in the personal reset state. The transmitter section is not affected. When RPR is cleared, the receiver section may operate normally. When RPR is set, the receiver section enters the personal reset state immediately. When in the personal reset state, the status bits are reset to the same state as after hardware reset.
ESAI Programming Model 6.3.5 ESAI Common Control Register (SAICR) The read/write Common Control Register (SAICR) contains control bits for functions that affect both the receive and transmit sections of the ESAI.See Figure 6-10. 11 10 9 X:$FFFFB4 23 22 21 8 7 6 ALC TEBE SYN 20 19 18 5 17 4 16 3 15 2 1 0 OF2 OF1 OF0 14 13 12 Reserved bit - read as zero; should be written with zero for future compatibility.
ESAI Programming Model 6.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the ESAI operate synchronously or asynchronously with respect to each other (see Figure 6-11). When SYN is cleared, the asynchronous mode is chosen and independent clock and frame sync signals are used for the transmit and receive sections.
ESAI Programming Model ASYNCHRONOUS (SYN=0) TRANSMITTER SDO FRAME SYNC CLOCK SCKT ESAI BIT CLOCK SCKR EXTERNAL TRANSMIT CLOCK EXTERNAL TRANSMIT FRAME SYNC INTERNAL CLOCK INTERNAL FRAME SYNC EXTERNAL RECEIVE CLOCK EXTERNAL RECEIVE FRAME SYNC CLOCK FST FSR FRAME SYNC SDI RECEIVER NOTE: Transmitter and receiver may have different clocks and frame syncs.
ESAI Programming Model 11 X:$FFFFB3 23 10 9 8 7 6 RODF REDF RDF ROE RFS 22 21 20 19 18 5 4 3 2 1 0 IF2 IF1 IF0 12 17 16 15 14 13 TODE TEDE TDE TUE TFS Reserved bit - read as zero; should be written with zero for future compatibility. Figure 6-12 SAISR Register 6.3.6.
ESAI Programming Model 6.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 When set, RFS indicates that a receive frame sync occurred during reception of the words in the receiver data registers. This indicates that the data words are from the first slot in the frame. When RFS is clear and a word is received, it indicates (only in the network mode) that the frame sync did not occur during reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset.
ESAI Programming Model 6.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled, during the second time slot in the frame.
ESAI Programming Model 6.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17 When set, TODE indicates that the enabled transmitter data registers became empty at the beginning of an odd time slot. Odd time slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame.
ESAI Programming Model 23 16 15 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE 7 0 23 SERIAL RECEIVE SHIFT REGISTER 8 7 0 7 16 15 0 8 7 RECEIVE MIDDLE BYTE 0 ESAI RECEIVE DATA REGISTER (READ ONLY) RECEIVE LOW BYTE 7 RECEIVE HIGH BYTE 7 0 0 RECEIVE LOW BYTE 7 0 7 0 24 BIT 20 BIT 16 BIT SDI 12 BIT 8 BIT MSB 8-BIT DATA MSB LSB 0 LSB 20-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received MSB first if RSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown.
ESAI Programming Model 23 16 15 RECEIVE HIGH BYTE 8 7 RECEIVE MIDDLE BYTE 7 0 23 7 SDI 0 MSB MSB 8-BIT DATA 7 0 RECEIVE LOW BYTE 0 7 LSB 0 0 0 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 16-BIT DATA MSB LSB 20-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received LSB first if RSHFD=1. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown.
ESAI Programming Model 6.3.7 ESAI Receive Shift Registers The receive shift registers (see Figure 6-13 and Figure 6-14) receive the incoming data from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1.
ESAI Programming Model transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See Figure 6-15 and Figure 6-16. Bit number N in TSM (TS**) is the enable/disable control bit for transmission in slot number N.
ESAI Programming Model After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data transmission. NOTE When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is generated. 6.3.
Operating Modes When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set. Data written to the RSM affects the next received frame. The frame being received is not affected by this data and would comply to the last RSM setting. Data read from RSM returns the last written data.
Operating Modes NOTE If the ESAI receiver section is already operating with some of the receivers, enabling additional receivers on the fly (i.e. without first putting the ESAI receiver in the personal reset state) by setting their REx control bits will result in erroneous data being received as the first data word for the newly enabled receivers. 6.4.3 ESAI Interrupt Requests The ESAI can generate eight different interrupt requests (ordered from the highest to the lowest priority): 1.
Operating Modes the previous setting and the new frame is serviced with the new setting without synchronization problems. Note that the maximum transmit last slot interrupt service time should not exceed N-1 ESAI bits service time (where N is the number of bits in a slot). 7.
Operating Modes or they may have their own separate clock and sync signals (asynchronous operating mode). The SYN bit in the SAICR register selects synchronous or asynchronous operation. Since the ESAI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent.
GPIO - Pins and Registers programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD bit in the TCR register for the transmitter section. 6.4.5 Serial I/O Flags Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR, RCCR and SAICR registers.
GPIO - Pins and Registers 6.5.2 Port C Direction Register (PRRC) The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of the ESAI GPIO pins. Table 6-12 describes the port pin configurations. Hardware and software reset clear all PRRC bits.
ESAI Initialization Examples configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data.
ESAI Initialization Examples 6.6.2 • • • • • • • • 6.6.3 • • • • • • Initializing Just the ESAI Transmitter Section It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. The transmitter section should be in its personal reset state (TPR = 1). Configure the control registers TCCR and TCR according to the operating mode, making sure to clear the transmitter enable bits (TE0 - TE5). TPR must remain set.
ESAI Initialization Examples NOTES DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
7 Serial Host Interface 7.1 Introduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Freescale Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-circuit Control (I2C) bus.
Serial Host Interface Internal Architecture 7.2 Serial Host Interface Internal Architecture The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP may access the SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques and DMA transfers. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes.
SHI Clock Generator 7.3 SHI Clock Generator The SHI clock generator generates the serial clock to the SHI if the interface operates in the Master mode. The clock generator is disabled if the interface operates in the Slave mode, except in I2C mode when the HCKFR bit is set in the HCKR register. When the SHI operates in the Slave mode, the clock is external and is input to the SHI (HMST = 0). Figure 7-2 illustrates the internal clock path connections.
7-4 HA5 HA6 HA4 21 HA3 20 22 21 20 21 HBER 22 HBUSY 20 HROE HRFF 19 19 19 18 18 HA1 18 HRNE 17 17 17 16 16 16 HTDE 15 15 15 Reserved bit, read as 0, should be written with 0 for future compatibility.
Serial Host Interface Programming Model The interrupt vector table for the Serial Host Interface is shown in Table 7-1 and the exceptions generated by the SHI are prioritized as shown in Table 7-2.
Serial Host Interface Programming Model 23 Mode of Operation 15 16 8-Bit Data Mode 8 7 16-Bit Data Mode 0 24-Bit Data Mode Stops Data When Data Mode is Selected Passes Data When Data Mode is Selected AA0420k Figure 7-5 SHI I/O Shift Register (IOSR) 7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side The Host Transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits wide.
Serial Host Interface Programming Model 7.4.4.1 HSAR Reserved Bits—Bits 17–0,19 These bits are reserved and unused. They read as 0s and should be written with 0s for future compatibility. 7.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18 Part of the I2C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain the HA[6:0] slave device address.
Serial Host Interface Programming Model SS SCK (CPOL = 0, CPHA = 0) SCK (CPOL = 0, CPHA = 1) SCK (CPOL = 1, CPHA = 0) SCK (CPOL = 1, CPHA = 1) MISO/ MOSI MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture AA0421 Figure 7-6 SPI Data-To-Clock Timing Diagram The Clock Phase (CPHA) bit controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin.
Serial Host Interface Programming Model When in Master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register. The clock phase and polarity should be identical for both the master and slave SPI devices.
Serial Host Interface Programming Model Table 7-3 SHI Noise Reduction Filter Mode HFM1 HFM0 Description 0 0 Bypassed (Disabled) 0 1 Reserved 1 0 Narrow Spike Tolerance 1 1 Wide Spike Tolerance When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment. When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected.
Serial Host Interface Programming Model 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The individual reset state is entered following a one-instruction-cycle delay after clearing HEN. 7.4.6.
Serial Host Interface Programming Model It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardware reset and software reset. 7.4.6.5 HCSR Reserved Bits—Bits 23, 18 and 16 These bits in HCSR are reserved and unused. They are read as 0s and should be written with 0s for future compatibility. 7.4.6.
Serial Host Interface Programming Model Table 7-5 HREQ Function In SHI Slave Modes (continued) HRQE1 HRQE0 HREQ Pin Operation 1 0 Asserted if IOSR is ready to transmit a new word 1 1 I2C: Asserted if IOSR is ready to transmit or receive SPI: Asserted if IOSR is ready to transmit and receive 7.4.6.9 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bit Host Idle (HIDLE) is used only in the I2C Master mode; it is ignored otherwise.
Serial Host Interface Programming Model NOTE Clearing HBIE will mask a pending bus-error interrupt only after a one-instruction-cycle delay. If HBIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HBIE and the RTI instruction at the end of the interrupt service routine. 7.4.6.
Serial Host Interface Programming Model NOTE Clearing HRIE[1:0] will mask a pending receive interrupt only after a one-instruction-cycle delay. If HRIE[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HRIE[1:0] and the RTI instruction at the end of the interrupt service routine. 7.4.6.
SPI Bus Characteristics 7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 The read-only status bit Host Receive FIFO Full (HRFF) indicates that the Host Receive FIFO (HRX) is full. HRFF is set when the HRX FIFO is full. HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset, and during the Stop state. 7.4.6.
I2C Bus Characteristics the master data input line, and MOSI is the master data output line. When the SPI is configured as a slave device, these pins reverse roles. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.
I2C Bus Characteristics • • Stop data transfer—The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 7-8). Data valid—The state of the data line represents valid data when, after a Start event, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.
I2C Bus Characteristics the slave device is ready for the next byte transfer. The SHI supports this feature when operating as a master device and will wait until the slave device releases the SCL line before proceeding with the data transfer. 7.6.2 I2C Data Transfer Formats I2C bus data transfers follow the following format: after the start event, a slave device address is sent.
SHI Programming Considerations 7.7 SHI Programming Considerations The SHI implements both SPI and I2C bus protocols and can be programmed to operate as a slave device or a single-master device. Once the operating mode is selected, the SHI may communicate with an external device by receiving and/or transmitting data. Before changing the SHI operational mode, an SHI individual reset should be generated by clearing the HEN bit.
SHI Programming Considerations 7.7.2 SPI Master Mode The SPI Master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI2C = 0), and selecting the Master mode of operation (HMST = 1). Before enabling the SHI as an SPI master device, the programmer should program the proper clock rate, phase, and polarity in HCKR. When configured in the SPI Master mode, the SHI external pins operate as follows: • • • • • SCK/SCL is the SCK serial clock output.
SHI Programming Considerations • • • • • SCK/SCL is the SCL serial clock input. MISO/SDA is the SDA open drain serial data line. MOSI/HA0 is the HA0 slave device address input. SS/HA2 is the HA2 slave device address input. HREQ is the Host Request output. When the SHI is enabled and configured in the I2C Slave mode, the SHI controller inspects the SDA and SCL lines to detect a start event.
SHI Programming Considerations 7.7.3.2 Transmit Data In I2C Slave Mode A transmit session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the SDA line.
SHI Programming Considerations In the I2C Master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set. This condition ensures that the data byte written to HTX will be interpreted as being a slave address byte. This data byte must specify the slave device address to be selected and the requested data transfer direction. NOTE The slave address byte should be located in the high portion of the data word, whereas the middle and low portions are ignored.
SHI Programming Considerations In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP using either DSP instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before acknowledge. In this case, the clock will be reactivated when the FIFO is read (the SHI gives an ACK = 0 and proceeds receiving). 7.7.4.
SHI Programming Considerations NOTES DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
Appendix A A.1 Bootstrap ROM DSP56364 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56364 - (C) Copyright 1998 Freescale Inc. ; Revised August 11, 1998. ; ; ; This is the Bootstrap program contained in the DSP56364 192-word Boot ; ROM. This program can load any program RAM segment from an external ; EPROM or from the SHI serial interface.
Bootstrap ROM opt cex,mex,mu ;; ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; ;; BOOT equ $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located AARV equ $D00409 ; AAR1 selects the EPROM as CE~ ; mapped as P from $D00000 to ; $DFFFFF, active low PROMADDR equ $FF1000 ; Starting PROM address MA MB MC MD EQU EQU EQU EQU 0 1 2 3 ;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_AAR1 EQU $FFFFF8
Bootstrap ROM ; MD:MC:MB:MA=1110 - Bootstrap from SHI (I2C slave, HCKFR=1) ; MD:MC:MB:MA=1111 - Bootstrap from SHI (I2C slave, HCKFR=0) SHILD ; ; ; ; ; ; ; ; ; ; ; ; ; ; This is the routine which loads a program through the SHI port. The SHI operates in the slave mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for receive operation. The word size for transfer is 24 bits. The SHI operates in the SPI or in the I2C mode, according to the bootstrap mode.
Bootstrap ROM ;======================================================================== ; This is the routine that loads from external EPROM.
Bootstrap ROM bra <* ;======================================================================== ; Code for burn-in ;======================================================================== M_OGDB M_PCRC M_PDRC M_PRRC SCKT EQU EQU EQU EQU EQU $FFFFFC $FFFFBF $FFFFBD $FFFFBE $3 ;; ;; ;; ;; ;; 0 OnCE Port Port Port SCKT GDB Register C GPIO Control Register C GPIO Data Register C Direction Register is GPIO bit #3 in ESAI (Port C) EQUALDATA equ ;; 1 if xram and yram are of equal ;; size and addresses,
Bootstrap ROM ;; write pattern to all memory locations if (EQUALDATA) ;; write x and y memory clr a #start_dram,r0 move #>length_dram,n0 rep n0 mac x0,x1,a x,l:(r0)+ else ;; x/y ram symmetrical ;; start of x/y ram ;; length of x/y ram ;; exercise mac, write x/y ram ;; x/y ram not symmetrical ;; write x memory clr a #start_xram,r0 move #>length_xram,n0 rep n0 mac x0,y0,a x1,x:(r0)+ ;; write y memory clr a #start_yram,r1 move #>length_yram,n1 rep n1 mac x1,y0,a x0,y:(r1)+ ;; start of xram ;; length of x
Bootstrap ROM eor add x1,a a,b ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 do n1,_loopy move y:(r1)+,a1 eor x0,a add a,b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b _loopy endif ;; check pram clr a #start_pram,r2 do n2,_loopp move p:(r2)+,a1 eor y0,a add a,b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b _loopp label1 ;;--------------------------------------------------;; toggle pin if no errors, stop execution otherwise.
Bootstrap ROM dc * endm ORG NUM_PATTERNS PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories dc dc dc dc $555555 $AAAAAA $333333 $F0F0F0 equ *-PATTERNS ;======================================================================== ; This code fills the unused bootstrap rom locations with their address dup $FF00C0-* dc * endm ;======================================================================== ; Reserved Area in the Program ROM: upper 128 words.
Appendix B B.
BDSL File EXTAL: TA_N: CAS_N: WR_N: RD_N: CVCC: CGND: AA1: AA0: A: AGND: AVCC: DVCC: DGND: GPIO: R: D: in bit; in bit; out bit; out bit; out bit; linkage bit; linkage bit; out bit; out bit; out bit_vector(0 to 17); linkage bit_vector(0 to 3); linkage bit_vector(0 to 3); linkage bit; linkage bit; inout bit_vector(0 to 3); linkage bit_vector(1 to 4); inout bit_vector(0 to 7)); use STD_1149_1_1994.
BDSL File "PVCC: "PCAP: "PGND: "EXTAL: "TA_N: "CAS_N: "WR_N: "RD_N: "CVCC: "CGND: "AA1: "AA0: "A: 73, 74), " & "AVCC: "AGND: "D: "DVCC: "DGND: "GPIO: "TDO: "TDI: "TCK: "TMS: attribute attribute attribute attribute 31, " & 32, " & 33, " & 34, " & 38, " & 39, " & 40, " & 41, " & 42, " & 43, " & 44, " & 45, " & (46, 47, 50, 51, 52, 53, 54, 57, 58, 59, 60, 62, 67, 68, 69, 70, (48, (49, (75, 79, 80, (91, 97, 98, 99, 100 TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_CLOCK 55, 56, 76, " & " & 94, " & " & " &
BDSL File attribute BOUNDARY_LENGTH of DSP56364 : entity is 86; attribute -- num "0 "1 "2 "3 "4 "5 "6 "7 "8 "9 "10 "11 "12 "13 "14 "15 "16 "17 "18 "19 -- num "20 "21 "22 "23 "24 "25 "26 "27 "28 "29 "30 "31 "32 "33 "34 "35 "36 "37 "38 "39 -- num "40 "41 "42 "43 "44 "45 BOUNDARY_REGISTER of DSP56364 : entity is cell port func safe [ccell dis rslt] (BC_1, *, control, 1)," & (BC_6, GPIO(3), bidir, X, 0, 1, Z)," (BC_1, *, control, 1)," & (BC_6, GPIO(2), bidir, X, 2, 1, Z)," (BC_1, *, control, 1)," & (BC_6, GPI
BDSL File "46 "47 "48 "49 "50 "51 "52 "53 "54 "55 "56 "57 "58 "59 -- num "60 "61 "62 "63 "64 "65 "66 "67 "68 "69 "70 "71 "72 "73 "74 "75 "76 "77 "78 "79 -- num "80 "81 "82 "83 "84 "85 (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, (BC_1, TA_N, input, EXTAL, input, RESET_N,
BDSL File DSP56364 24-Bit Digital Signal Processor Users Manual, Rev.
Appendix C C.1 Programmer’s Reference Introduction This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPs memory-mapped peripherals, an interrupt address table, an interrupt exception priority table, a quick reference to the host interface, and programming sheets for the major programmable registers on the DSP. C.1.1 Peripheral Addresses Table C-1 lists the memory addresses of all on-chip peripherals. C.1.
Programmer’s Reference Table C-1.
Programmer’s Reference Table C-1.
Programmer’s Reference Table C-1.
Programmer’s Reference Table C-1. Internal I/O Memory Map (continued) Peripheral Address Reserved $FFFF9F thru $FFFF95 SHI $FFFF94 SHI RECEIVE FIFO (HRX) $FFFF93 SHI TRANSMIT REGISTER (HTX) $FFFF92 SHI I2C SLAVE ADDRESS REGISTER (HSAR) $FFFF91 SHI CONTROL/STATUS REGISTER (HCSR) $FFFF90 SHI CLOCK CONTROL REGISTER (HCKR) Reserved Register Name $FFFF8F thru $FFFF80 RESERVED RESERVED Table C-2.
Programmer’s Reference Table C-2.
Programmer’s Reference Table C-3.
Programmer’s Reference C.2 Programming Sheets The following worksheets list the major programmable registers for the DSP56364. The programming sheets are grouped in the following order: • Central processor, • Phase Lock Loop, (PLL), • Enhanced Serial Audio Interface (ESAI), • Serial Host Interface (SHI), • GPIO (Ports B-C). Each sheet provides a space to write in the value of each bit and the hexadecimal value for each register.
Programmer’s Reference Date: Application: Programmer: Sheet 1 of 5 Carry Over Zero Negative Central Processor Unnormalized ( U = Acc(47) xnor Acc(46) ) Extension Limit FFT Scaling ( S = Acc(46) xor Acc(45) ) Scaling Mode S(1:0) Scaling Mode 00 No scaling 01 Scale down 10 Scale up 11 Reserved I(1:0) 00 01 10 11 Interrupt Mask Exceptions Masked None IPL 0 IPL 0, 1 IPL 0, 1, 2 Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved
Programmer’s Reference Date: Application: Programmer: Sheet 2 of 5 Central Processor Chip Operating Modes MOD(D:A) Reset Vector (Table Description 4-1 in Section 4.
Programmer’s Reference Date: Application: Programmer: Sheet 3 of 5 CENTRAL PROCESSOR IRQA Mode IAL2 0 1 Trigger Level Neg. Edge IAL1 0 0 1 1 IAL0 0 1 0 1 Enabled No Yes Yes Yes IPL — 0 1 2 IRQB Mode IBL2 0 1 Trigger Level Neg. Edge IBL1 0 0 1 1 IBL0 0 1 0 1 Enabled No Yes Yes Yes IPL — 0 1 2 IRQD Mode IDL2 0 1 Trigger Level Neg.
Programmer’s Reference Date: Application: Programmer: Sheet 4 of 5 CENTRAL PROCESSOR ESAI IPL ESL1 ESL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL — 0 1 2 SHI IPL SHL1 SHL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes Interrupt Priority Register (IPR–P) X:$FFFFFE R/W Reset = $000000 * IPL — 0 1 2 = Reserved, Program as 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 $0 $0 3 2 1 0 SHL1 SHL0 ESL1 ESL0 $0 Figure C-4.
Programmer’s Reference Date: Application: Programmer: Sheet 5 of 5 PLL PSTP PEN 0 1 1 x 0 1 PSTP and PEN Relationship Operation During STOP Recovery Time for STOP PLL Oscillator Disabled Disabled Long Disabled Enabled Short Enabled Enabled Short Power Consumption during STOP Minimal Lower Higher Bits XTLR and XTLD have no effect on DSP56364 operation Clock Output Disable (COD) 0 = 50% Duty Cycle Clock 1 = Pin Held In High State XTAL Disable Bit (XTLD) 0 = Enable Xtal Oscillator 1 = EXTAL Driven F
Programmer’s Reference Date: Application: Programmer: Sheet 1 of 3 SHI HSAR I2C Slave Address Slave address = Bits HA6-HA3, HA1 and external pins HA2, HA0 Slave address after reset = 1011[HA2]0[HA0] SHI Slave Address Register (HSAR) X:$FFFF92 Reset = $Bx0000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 HA6 HA5 HA4 HA3 8 7 6 5 4 3 2 1 0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 HA1 0 0 0 0 SHI Slave Address Register (HSAR) CPOL CPHA Result 0 0 SCK active low, strobe on risi
Programmer’s Reference Date: Application: Programmer: Sheet 2 of 3 SHI SHI Host Transmit Data Register (HTX) X:$FFFF93 Write Only Reset = $xxxxxx Host Transmit Data Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 SHI Host Transmit Data Register (HTX) SHI Host Receive Data Register (HRX) X:$FFFF94 Read Only Reset = $xxxxxx Host Receive Data Register Contents 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 SHI Host Receive Data Register (HRX) (FI
C-16 0 1 0 1 0 0 1 1 HRIE1 HRIE0 *= Reserved, write as 0 Receive FIFO full Receive Overrun Error Reserved 0 HTIE 1 0 HBIE 1 0 HIDL 1 Transmit Interrupt disabled Bus error Interrupt enabled Bus Error Interrupt disabled Stop event Bus busy HRFF=1 & HROE=0 HROE=1 Not applicable *0 HBUSY HBER HROE HRFF *0 HRNE *0 9 HRTQE Pin Operation 7 6 5 Master mode 4 1 0 0 1 3 2 1 0 0 SPI mode SHI enabled HI2C SHI disabled 1 24 bit data 16 bit data 0 HEN 0 0 8 bit data I2C Sl
Freescale Semiconductor FST is output 1 Internal clock source used 1 22 TFSD 23 21 TCKD Frame sync polarity negative 1 THCKP TFSP 19 TCKP 18 TFP3 17 15 TFP2 TFP1 16 TFP0 14 TDC4 13 TDC3 12 TDC2 11 Transmitter Clock Polatiry set to clockout on falling edge of transmit clock, latch in on rising edge of transmit clock 1 20 Transmitter Clock Polarity set to clockout on rising edge of transmitter clock, latch in on falling edge of transmit clock 0 TCKP Frame sync polarity positive
C-18 Transmit Last Slot Interrupt enabled 1 Transmit Interrupt enabled 1 22 TIE 23 21 20 TEDIE TEIE 19 TPR 17 rsvd PADC 18 Zeor Padding enabled 1 TFSR TFSL 15 13 12 11 10 9 8 7 6 1 0 Data shifted out LSB first Data shifted out MSB first 5 TE5 4 TE3 3 TE2 2 TE1 1 Transmitter enabled 1 TE4 Transmitter disabled 0 TE [0:5] TSHFD Data right aligned Data left aligned AC97 Reserved Network mode TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD 14 Word-length f
0 1 Freescale Semiconductor FSR is output FSR is input HCKR is output HCKR is input 23 22 21 Description 1 0 RHCKP 20 18 RFSP RCKP 19 16 15 14 RFP3 RFP2 RFP1 RFP0 17 12 11 10 9 RDC4 RDC3 RDC2 RDC1 RDC0 13 Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock Description Frame sync polarity negative Frame sync polarity positive RCKP RFSD RCKD 0 1 RFSP 8 RPSR De
C-20 0 1 RIE 0 1 RLIE Description 22 21 20 1 0 Description 18 17 16 15 13 12 RSWS4 RSWS3 RSWS2 14 10 9 0 8 6 Rsvd 5 Rsvd 4 RE3 3 Receiver enabled 1 7 Receiver disabled 0 0 RE0 1 RE1 2 RE2 Description Data shifted in MSB first Data shifted in LSB first RE [0:3] 0 1 Description Diata right aligned Data left aligned RSHFD 0 1 Description AC97 1 1 RWA Reserved 0 Network mode Network Mode Normal mode 1 1 0 RMOD1 RMOD0 0 Description ESAI Defines slot and d
Freescale Semiconductor 23 22 20 19 18 17 16 15 14 13 12 11 10 9 Description 7 TEBE 8 OF(2:0) SYN 6 Description 5 4 3 0 OF0 1 OF1 2 OF2 Holds data to send to OFn pin. See 8.3.5.1 to .3 Reserved Description Synchronous mode Asynchronous mode ALC 0 1 Description Controls FSR pin. See 8.3.5.
C-22 0 1 23 22 21 Description Reserved 20 19 18 16 TEDE 17 TODE Transmit odd-data register not empty 0 1 15 TDE 14 TUE 13 TFS 12 11 10 9 RODF REDF Description Description 6 RFS 7 ROE 1 0 RFS 5 4 2 1 0 IF [0:2] Description 3 0 IF0 1 IF1 2 IF2 Holds data sent from SCKR pin. See 8.3.6.1 Holds data sent from FSR pin. See 8.3.6.2 Holds data sent from HCKR pin. See 8.3.6.
Programmer’s Reference Date: Application: Programmer: Sheet 2 of 3 GPIO Port B (GPIO) Port B Control Register (PCRB) X:$FFFFCF ReadWrite Reset = $0 Port B Direction Register (PRRB) X:$FFFFCE ReadWrite Reset = $0 23 11 10 9 8 7 6 5 *0 *0 *0 *0 *0 *0 *0 *0 *0 11 23 10 9 8 7 6 3 4 5 4 *0 *0 *0 *0 *0 *0 *0 *0 *0 2 1 0 PC3 PC2 PC1 PC0 3 2 1 0 PDC3 PDC2PDC1PDC0 PCn = 0 & PDCn = 0 -> Port pin PCn disconnected PCn = 1 & PDCn = 0 -> Port pin PCn configured as input PCn = 0 & PDCn =
Programmer’s Reference Date: Application: Programmer: Sheet 2 of 3 GPIO Port C (ESAI) Port C Control Register (PCRC) X:$FFFFBF ReadWrite Reset = $0 Port C Direction Register (PRRC) X:$FFFFBE ReadWrite Reset = $0 23 11 10 9 8 7 6 5 4 *0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 11 23 *0 10 9 PDC11 PDC10 PDC9 8 7 6 5 PDC8 PDC7 PDC6 PDC5 3 2 1 0 PC3 PC2 PC1 PC0 4 3 2 1 0 PDC4 PDC3 PDC2PDC1PDC0 PCn = 0 & PDCn = 0 -> Port pin PCn disconnected PCn = 1 & PDCn = 0 -> Port pin
Index A adder modulo 1-5 offset 1-5 reverse-carry 1-5 Address Attribute 4-2 address attribute 4-2 Address Generation Unit 1-5 Address Tracing (AT) Mode 4-2 Address Tracing Enable (ATE) 4-2 addressing modes 1-6 AGU 1-5 B barrel shifter 1-4 Block Diagram 1-2 bootstrap 4-4 bootstrap modes 4-3 Bootstrap Program A-1 bootstrap program options invoking 4-4 bootstrap ROM 3-2 bus external address 2-4 external data 2-4 buses internal 1-6 Divide Factor (DF) 1-7 DMA 1-7 DO loop 1-6 DSP56300 core 1-4 DSP56300 Family M
Receive Interrupt Enable Bits 7-14 SHI Control/Status Register 7-10 HDM0-HDM5 (HCKR Divider Modulus Select) 7-9 HEN (HCSR SHI Enable) 7-10 HFIFO (HCSR FIFO Enable Control) 7-12 HFM0-HFM1 (HCKR Filter Mode) 7-9 HI2C (HCSR Serial Host Interface I2C/SPI Selection) 7-11 HIDLE (HCSR Idle) 7-13 HM0-HM1 (HCSR Serial Host Interface Mode) 7-11 HMST (HCSR Master Mode) 7-12 Host Receive Data FIFO (HRX) 7-6 Receive Data FIFO—DSP Side 7-6 Transmit Data Register (HTX) 7-6 Transmit Data Register—DSP Side 7-6 Host Receiv
P PAB 1-7 PAG 1-6 PC register 1-6 PCU 1-6 PDB 1-7 PDC 1-6 Peripheral I/O Expansion Bus 1-6 Peripheral modules 1-3 Peripherals (IPR-P) C-12 Phase Lock Loop Control Register (PCTL) C-13 PIC 1-6 PLL 1-7, 2-4 PLL Pre-Divider Factor (PD0-PD3) 4-8 Port A 2-4 Port B Registers (PCRB, PRRB, PDRB) C-23 Port C 2-10 Port C Registers (PCRC, PRRC, PDRC) C-24 Power 2-2 Priority 4-2 priority mechanism 4-2 Processor Architecture 1-3 Program Address Bus (PAB) 1-7 Program Address Generator (PAG) 1-6 Program Control Unit (PCU)
Sixteen-bit Compatibility 3-1 Size register (SZ) 1-6 SP 1-6 SPI 7-1, 7-16 HCSR Bus Error 7-16 Host Busy 7-16 Host Receive FIFO Full 7-16 Host Receive FIFO Not Empty 7-15 Host Receive Overrun Error 7-16 Host Transmit Data Empty 7-15 Host Transmit Underrun Error 7-15 Receive Interrupt Enable 7-14 Master Mode 7-21 Slave Mode 7-20 SPI Data-To-Clock Timing 7-8 SPI Data-To-Clock Timing Diagram 7-8 SPI Mode 7-1 SR register 1-6 SS 1-6 Stack Counter register (SC) 1-6 Stack Pointer (SP) 1-6 Status Register 1-10 Statu
