PRODUCT SPECIFICATION H132A-S Wi-Fi Single-band 1x1 802.11b/g/n SDIO/UART Module Datasheet Version:v1.
H132A-S Module Datasheet Ordering Information Part NO. FGH132ASXX-00 Description SV32WB01L, b/g/n Wi-Fi, 1T1R, 12X12mm, SDIO/UART, PCB V1.0,1bit mode,with shielding Customer: Customer P/N: Signature: Date: Office: 14th floor, Block B, phoenix zhigu, Xixiang Street, Baoan District, Shenzhen Factory: NO.8, Litong RD., Liuyang Economic & Technical Development Zone, Changsha, CHINA TEL:+86-755-2955-8186 FN-LINK TECHNOLOGY LIMITED Website:www.fn-link.
H132A-S CONTENTS 1. General Description.............................................................................................................. 5 1.1 Introduction......................................................................................................................... 5 1.2 Description.......................................................................................................................... 5 2. Features...................................................................
H132A-S Revision History Version Date Revision Change Draft Checked Approved V1.0 2021/3/10 New version Lxy Lxy Szs V1.1 2021/06/04 增加 34 脚用途描述 Lxy Lxy Szs V1.2 2021/10/14 Update module photo LXY LXY QJP V1.3 2021/10/15 Update tolerance to +/-1.5 LXY LXY QJP V1.4 2022/03/04 Update IO power level LXY LXY QJP V1.5 2022/03/22 Update reference circuit LXY LXY QJP V1.
H132A-S 1. General Description 1.1 Introduction H132A-S is a highly integrated 2.4 GHz Wi-Fi module that support the IEEE 802.11b/g/n standard with 20/40 MHz bandwidth. Module chipset integrates a Andes D10F 32-bit RISC core which runs at up to 480MHz , includes up to 512KB of embedded SRAM, Internal flash up to 2MB, and various peripheral interfaces, including the SPI, UART, I2C, PWM, GPIO, and multi-channel ADC. In addition, it provides SDIO2.0 slave interfaces, with clock frequency up to 50 MHz. 1.
H132A-S 2. Features General Features Operate at ISM frequency bands (2.4GHz) Maximum rate of 150 Mbit/s@HT40 MCS7 Low power dissipation PHY supporting IEEE 802.11b/g/n MAC supporting IEEE802.11 d/e/h/i/k/r/w Module integrated 32K clock WEP/WPA/WPA2/WPA3 /WMM for Wi-Fi Built-in 512 KB SRAM and 128 KB ROM Internal flash 2MB SDIO 1Line mode WLAN Interface SDIO interface for Wi-Fi Support SDIO/UART/PWM/GPIO/I2C/ADC interface 3.
H132A-S 4. General Specification 4.1 WI-FI Specification Feature Description WLAN Standard IEEE 802.11 b/g/n Wi-Fi compliant Frequency Range 2412MHz to 2462MHz Number of Channels 802.11b/g/n(HT20):11 802.11n(HT40):7 Test Items Typical Value EVM 802.11b /11Mbps : 17dBm ± 2 dB EVM -10dB 802.11g /54Mbps : 15dBm ± 2 dB EVM -25dB 802.11n /MCS7 EVM -28dB Output Power : 15dBm ± 2 dB Spectrum Mask Meet with IEEE standard Freq.
H132A-S Maximum Input Level Antenna Reference - MCS=2 PER @ -82 dBm ≤-79 dBm - MCS=3 PER @ -79 dBm ≤-76 dBm - MCS=4 PER @ -76 dBm ≤-73 dBm - MCS=5 PER @ -71 dBm ≤-70 dBm - MCS=6 PER @ -70 dBm ≤-68 dBm - MCS=7 PER @ -68 dBm ≤-66 dBm 802.11b : -10 dBm 802.11g/n : -20 dBm External Antenna 4dBi 5. Pin Definition 5.
H132A-S 5.2 Pin Definition details NO. Name Type Description Voltage 1 GND － Ground connections 2 WL_ANT I/O RF I/O port 3 GND － Ground connections 4 NC － Floating (Don’t connected to ground) 5 NC － Floating (Don’t connected to ground) 6 GPIO33 I/O Muti funtion I/O 7 GPIO17 I/O 8 NC － Floating (Don’t connected to ground) 9 VCC P Main power voltage source input 3.13V-3.
H132A-S Muti funtion I/O 34 GPIO13 I/O H: to download mode;L:to normal mode VCC Don’t pull high, better10K pull low this pin.
H132A-S 6. Electrical Specifications 6.1 Power Supply DC Characteristics MIN TYP MAX -10 25 85 VCC 3.13 3.3 3.46 V VDDIO 1.75 3.3V 3.46 V Operating Temperature Unit deg.C 6.2 Power Consumption VCC = 3.3V(Unit:mA) Power Consumption Power saving 0.17@DTIM3,MCU off TX Test mode (2.4G HT20@17dbm) 212 RX Test mode (2.4G HT20) 47.
H132A-S 6.3 Power-on sequence Below shows the VDD33=3.3V power-on sequence of the SV32WB0xx from power-up to firmware download, including the initial device power-on reset evoked by LDO_EN signal. The LDO_EN input level must be kept above the threshold voltage. After initial power-on, the LDO_EN signal can be held low to turn off the SV32WB0xx or pulsed low to induce a subsequent reset. After LDO_EN is asserted, the host starts the power-on sequence of the SV32WB0xx.
H132A-S 6.4 Interface Circuit time series 6.4.1 SDIO Pin Description The secure digital input/output (SDIO) interface supports three working modes: Default speed mode (DS) The maximum frequency of the interface clock is 25 MHz. The interface clock can work in 1-bit mode . High speed mode (HS) The maximum frequency of the interface clock is 50 MHz. SDR25 mode The maximum frequency of the interface clock is 50 MHz SDIO Pin Description SD 1-Bit Mode DATA0 Data Line 0 CLK Clock CMD Command Line 6.4.
H132A-S Figure 8-6 shows the output data timing in DS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode.
H132A-S Figure 8-7 shows the input data timing in DS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock falling edge, and tODLY(min) is the minimum delay of the output data relative to the clock falling edge. Table 8-12 describes the timing restrictions in DS mode. Note: In DS mode, the output data is referenced to the clock falling edge, and the input data is referenced to the clock rising edge.
H132A-S Figure 8-8 shows the input data timing in HS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode Figure 8-9 shows the input data timing in HS mode.
H132A-S Table 8-15 describes the timing restrictions in HS mode. Table 8-16 Timing restrictions in HS mode (VDDIO = 1.8 V) Note: The data signal timing in HS mode is different from that in DS mode. The output data and input data are referenced to the clock rising edge. SDR25 Mode The SDR25 mode is entered only after the voltage of the SDIO is switched. In this mode, the maximum interface clock frequency is 50 MHz. Table 8-17 describes the clock restrictions.
H132A-S FN-LINK TECHNOLOGY LIMITED 18
H132A-S 7. Size reference 7.1 Module Picture L x W : 12 x 12 (+0.3/-0.1) mm H: 2.3 (±0.2) mm Weight 0.66g 7.2 Marking Description < TOP VIEW > Date code: XXXX 00 表示-00 机型.
H132A-S 7.
H132A-S 7.4 Layout Recommendation 8. The Key Material List Item Part Name 1 PCB 2 Description Manufacturer H132A-S 4L FR4 12X12X0.8mm XY-PCB,KX-PCB,Sunlord,SL-PCB Inductor 0603,4.
H132A-S 9.
H132A-S 10. Recommended Reflow Profile Referred to IPC/JEDEC standard. Peak Temperature : <250°C Number of Times : 2 times 11.
H132A-S 12. Package 12.1 Reel A roll of 1500pcs 12.
H132A-S 12.3 Packaging Detail 13. Moisture sensitivity The Modules is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components.
Single Modular approval Declaration letter We ，FN-LINK TECHNOLOGY LIMITED apply Single modular approval for Product Name: WIFI module Model: H132A-S FCC ID: 2AATL-H132AS According to 996369 D01 Module Equip Auth Guide v01r04 and 15.212 requirement: 1) The radio elements must have the radio frequency circuitry shielded. Physical components and tuning capacitor(s) may be located external to the shield, but must be on the module assembly; Answer ：Yes， Shielded for both side .
Reports and Refer to modular installation manual Please contact me if you have any further questions. Thanks for your attention.
1. FCC Statement FCC Statement FCC standards: FCC CFR Title 47 Part 15 Subpart C Section 15.247 Integral antenna with antenna gain 4dBi This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
