User's Manual
Table Of Contents
- 1. Introduction
- 2. General Specification
- 3. Pin Definition
- 4. Physical Interfaces
- 5. Electrical Characteristic
- 6. Reference Design
- 7. Mechanical Characteristic
- 8. Recommended PCB Layout and Mounting Pattern
- 9. Recommended Reflow Profile
- 10. Ordering Information
FLC-BTM403 Series User Manual
Flaircomm Technologies Confidential
-18-
tsclkl PCM_CLK low time 200 - - ns
tsclkh PCM_CLK high time 200 - - ns
thsclksynch
Hold time from PCM_CLK low to
PCM_SYNC high
30 - - ns
tsusclksynch
Set-up time for PCM_SYNC high to
PCM_CLK low
30 - - ns
tdpout
Delay time from PCM_SYNC or
PCM_CLK whichever is later, to valid
PCM_OUT data (Long Frame Sync only)
- -
20
ns
tdsclkhpout
Delay time from CLK high to PCM_OUT
valid data
- -
20
ns
tdpoutz
Delay time from PCM_SYNC or
PCM_CLK low, whichever is later, to
PCM_OUT data line high impedance
- -
20
ns
tsupinsclkl
Set-up time for PCM_IN valid to CLK
low
30 - - ns
thpinsclkl
Hold time for PCM_CLK low to
PCM_IN invalid
30 - - ns
Table 6: PCM Slave Timing
Figure 11: PCM Slave Timing Long Frame Sync