User's Manual

FLC-CBM202 Datasheet
Flaircomm Microelectronics Confidential
-18-
4.5.1.1.1 SDIO Sleep Signaling
FLC-CBM202 supports a variety of mechanisms to enable both itself and the host to efficiently enter
and leave low-power modes.
4.5.1.1.1.1 Card Sleep and Wake-up
FLC-CBM202 automatically uses its sleep modes to minimize power consumption. Registers in
function 0 are always directly accessible by the host, irrespective of the device’s sleep modes.
Attempts to access function 1 while the device is in deep sleep are likely to results in SDIO timeouts.
To avoid the need for the host to implement complicated retry mechanisms, a simple deep sleep
control scheme is supported via a Vender Unique Register within the CCCR in function 0. The host
uses this register to tell FLC-CBM202 when it is allowed to use deep sleep. When the host
subsequently needs to access function 1 it uses the same register to initiated a wake-up and then
waits for an SDIO interrupt to indicate that the wake-up is compete.
4.5.1.1.1.2 Host Sleep and Wake-up
The normal method for FLC-CBM202 to wake the host up is via the in-band interrupt on
SDIO_DATA [1]. This is the dame mechanism that is used to notify the host of received data or
interesting events, no explicit sleep signaling is required.
An alternative out-of-band mechanism is provided for hosts that cannot utilize the SDIO interrupt as
a wake-up signal, e.g. where a separate power-management IC needs to restore power to the host
processor. This feature is enabled by masking out SDIO interrupts via the Int Enable register within
the CCCR in function 0. When an SDIO interrupt would have been signaled otherwise, a pulse is
instead generated on a configured PIO line.
Note: The out-of-band wake-up signal is not a replacement for the in-band SDIO interrupt. The
standard interrupt signal should be used for data transfer during normal operation.
4.5.1.2 CSPI
CSPI is a proprietary alternative to the standard SDIO bus protocols. It has been designed to be more
efficient for hosts that are capable of supporting SPI but that do not incorporate an SDIO host
controller. Its principal advantages over SD SPI are as follows:
 Burst transfer is continuous rather than being split into blocks with interleaved CRC and status
tokens. This reduces the number of clock cycles required to complete the transfer, and allows
the host to stream data directly to or from memory buffers in a single operation without copying.
 Timings are deterministic (fixed numbers of clock cycles) from the start of commands, so
hardware can be programmed to complete data transfers without requiring interaction on a per-
octet basis.
 Command headers are multiples of 16 bits long, and the endianness of octets within 16-bit
words is configurable. These features enable effective support on 16-bit host platforms.
 16-bit registers are read or written with a single command instead of requiring two separate
 IO_RW_DIRECT (CMD52) operations.
 An interrupt can optionally be generated for failed commands. This can be used if the host does
not support full-duplex transfers, and avoids the need to check status bits or poll status registers
for successful operations.