User's Manual

FLC-BTM805 Datasheet
Flaircomm Microelectronics Confidential
-14-
4.1.4 Low-voltage VDD_AUX Linear Regulator
The on-board low-voltage VDD_AUX Regulator powers BTM805 1.35V VDD_AUX supply.
The regulator is controlled by the firmware.
4.1.5 Power-on Sequencing
BTM805 does not have any strict relative timing requirements for clock and power supply
sequencing during reset or power-on. Follow this sequence of operation to ensure that the initial cold
boot is completed successfully:
1、All external power supplies should be stable.
2、VREG_EN_RST# should be driven high.
It is then possible to establish host communications with the CRS8811 in order to set further
configuration values. When you have set configuration values, perform a warm reset so that they
take effect and normal radio operation can begin.
4.2 Reset
BTM805 the reset function is internally tied to the VREG_EN_RST# pin. The BTM805 may be
reset from several sources:
 VREG_EN_RST# pin
 Power-on reset
 A UART break character
 Via a software-configured watching timer
The VREG_EN_RST# pin is an active low reset. To ensure a full reset the reset signal should be
asserted for a period greater than 5ms.
A warm reset function is also available under software control. After a warm reset the RAM data
remains available.
Pin Name /
Group
I/O Type
No Core Voltage
Reset
Full Chip Reset
VREG_EN_RST#
Digital input
Strong pull-down
N/A
SPI_CLK /
PCM_CLK / PIO[24]
Digital bidirectional tristated
Weak pull-down
Weak pull-down
SPI_CS# /
PCM_SYNC /
PIO[23]
Digital bidirectional tristated
Weak pull-up (SPI)
Weak pull-down (PCM)
Weak pull-up (SPI)
Weak pull-down (PCM /
PIO)
SPI_MISO /
PCM_OUT / PIO[22]
Digital output tristated
Weak pull-down
Weak pull-down
SPI_MOSI /
PCM_IN / PIO[21]
Digital input
Weak pull-down
Weak pull-down
PIO[5:0]
Digital bidirectional tristated
Weak pull-down
Weak pull-down
Table 5: Pin Status on Reset