User's Manual

FLC-BTM805 Datasheet
Flaircomm Microelectronics Confidential
-13-
4. Physical Interfaces
4.1 Power Control and Regulation
Four regulators are integrated in this product.
The high-voltage regulator generates the main 1.8V rail from the VDD_IN. This then supplies 3
lower voltage linear regulators:
 A programmable low-voltage regulator to supply the 0.90V to 1.25V digital supply, VDD_DIG
 A low-voltage regulator to supply the 1.35V VDD_ RADIO rail
 An always-on regulator to supply 1.35V to auxiliary and reference circuitry, VDD_AUX
4.1.1 High-voltage Linear Regulator
A minimum 1.5uF capacitor must be connected to the VREG_OUT_HV pin. Low ESR capacitors
such as multilayer ceramic types should be used.
BTM805 recommends that the supplies are all powered at the same time. The order of powering the
supplies relative to the other I/O supply (VDD_PADS) is not important. If the I/O supply is powered
before the supplies all digital I/Os will have a weak pull-down irrespective of the reset state.
4.1.1.1 Regulator Control
The regulator is enabled by taking the VREG_EN_RST# pin above 1V. The regulator can be
controlled by the software.
The VREG_EN_RST# is also connected internally to the reset function.
VREG_EN_RST# pin is pulled down internally.
4.1.2 Low-voltage VDD_DIG Linear Regulator
The on-chip low-voltage VDD_DIG Regulator powers BTM805 digital circuits.
A minimum 1.5uF capacitor must be connected to the VDD_DIG pin. Low ESR capacitors such as
multilayer ceramic types should be used.
The regulator enable and output voltage is controlled by the firmware.
4.1.3 Low-voltage VDD_ANA Linear Regulator
The on-chip low-voltage VDD_ANA Linear Regulator powers the internal radio circuits of BTM805.
A minimum 1.5uF capacitor must be connected to the VDD_ANA pin. Low ESR capacitors such as
multilayer ceramic types should be used.
The regulator is controlled by the firmware. The regulator is disabled when the device is in deep
sleep mode or reset.