User's Manual

FLC-BTM501 Datasheet
Flaircomm Microelectronics Confidential
-15-
4.3.4 DAC
The DAC contains two second order Sigma Delta converters allowing two separate channels that are
identical in functionality as show in Figure 3.
4.3.5 DAC Sample Rate Selection and Warping
Each DAC supports the following sample rates: 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz,
44.1kHz, 48kHz.
One of the main concerns for the DAC used in stereo wireless music applications is the ability to
keep sample rates for the CODECs at both ends of the wireless link in synchronization. A VM
function adjusts the sample rate using a ‘warping’ function to tune the sample rate to the required
value. The ADC warp function allows the sample rate to be changed by +/-3%, in steps of 1/2
17
, or
7.6ppm. The warp function preserves the signal quality – the distortion introduced when warping the
sample rate is negligible.
4.3.6 DAC Gain
The DAC contains two gain stages for each channel, a digital and an analogue gain stage.
4.3.7 Mono Operation
Mono operation is single channel operation of the stereo CODEC. The left channel represents the
single mono channel for audio in and audio out. In mono operation the right channel is auxiliary
mono channel that may be used in dual mono channel operation.
4.3.8 Audio Input Stage
The audio input stage of the module consists of a low noise input amplifier, which receives its
analogue input signal from pins MIC_LP and MIC_LN to a second–order ∑-Δ ADC that outputs a
4Mbit/sec single-bit stream into the digital circuitry. The input can be configured to be either single
ended or fully differential. It can be programmed for either microphone or line input and has a 3-bit
digital gain setting of the input-amplifier in 3dB steps to optimize it for the use of different
microphones.
4.3.9 Microphone Input
Check the reference design in Figure 10 for the microphone input design.
4.3.10 Audio Output Stage
The output digital circuitry converts the signal from 16-bit per sample, linear PCM of variable
sampling frequency to a 2Mbits/sec multi-bit stream, which is fed into the analogue output circuitry.
The output circuit comprises a digital to analogue converter with gain setting and output amplifier.
Its class-AB output-stage is capable of driving a signal on both channels of up to 2V pk-pk-
differential into a load of 16Ω. The output is available as a differential signal between SPK_LP and
SPK_LN for the left channel; and between SPK_RP and SPK_RN for the right channel. The output
is capable of driving a speaker directly if its impedance is at least 8Ω if only one channel is
connected or an external regulator is used.