User's Manual

FLC-BTM403 Datasheet
Flaircomm Microelectronics Confidential
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Figure 9: 16-Bit Slot Length and Sample Formats
4.3.7 Additional Features
The module has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may
also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power
down.
4.3.8 PCM Timing Information
Symbol
Parameter
Min
Typical
Max
Unit
fmclk
PCL_CLK
Frequency
4MHz DDS generation.
Selection of frequency
is programmable.
-
128
-
kHz
256
512