Datasheet
FTL
X
© Fin
i
I.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Notes
:
1.
C
2. T
F
t
h
o
u
e
x
o
u
3. L
4. I
n
5. L
be
X
1671D3BCL
i
sar Corporati
o
Pin Desc
r
Symbol
V
EET
T
FAULT
T
DIS
SDA
SCL
MOD_AB
RS0
RX_LOS
RS1
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
:
C
ircuit groun
d
i
F
AULT
is an op
e
h
e host board i
f
u
tput indicates
x
ceeding the p
r
u
tput is pulled
aser output di
s
n
ternally pulle
d
OS is open co
l
e
tween 2.0V a
n
Fi
g
ure
SFP+ ER/E
W
o
n - February
2
r
iptions
Transmi
t
Transmi
t
Transmi
t
2-wire S
2-wire S
S Module
A
Rate Sel
e
Loss of
S
Rate Sel
e
Receive
r
Receive
r
Receive
r
Receive
r
Receive
r
Receive
r
Transmi
t
Transmi
t
Transmi
t
Transmi
t
Transmi
t
i
s internally is
o
e
n collector/dr
a
f
intended for
u
a transmitter
f
r
eset alarm thr
to <0.8V.
s
abled on T
DIS
>
d
down per SF
F
l
lector output.
n
d 3.6V. Logi
c
1. Dia
g
ram
o
Towards
Bezel
W
Preliminary
S
2
011
t
ter Groun
d
t
ter Faul
t
t
ter Disable. L
a
erial Interface
erial Interface
A
bsent. Grou
n
e
ct 0.
S
ignal indicati
o
e
ct 1.
r
Groun
d
r
Groun
d
r
Inverted DA
T
r
Non-inverted
r
Ground
r
Power Suppl
y
t
ter Power Su
p
t
ter Ground
t
ter Non-Inver
t
t
ter Inverted
D
t
ter Ground
o
lated from ch
a
a
in output, whi
u
se. Pull up v
o
f
ault caused b
y
esholds. A lo
w
>
2.0V or ope
n
F
-8431 Rev 4.
Should be pu
l
c
0 indicates n
o
o
f Host Board
V
V
T
S
S
M
R
R
1
2
3
4
5
6
7
8
9
10
T
R
S
pecification –
Rev. A0
Name/D
e
a
ser output di
s
Data Line
Clock Line
n
ded within th
e
o
n. Logic 0 i
n
T
A out. AC C
o
DATA out.
A
y
p
ply
t
ed DATA in.
D
ATA in. AC
C
a
ssis ground.
ch should be
p
o
ltage should b
e
y
either the T
X
w
output indic
a
n
, enabled on
T
1.
l
led up with 4.
7
o
rmal operatio
n
Connector B
l
VeeT
VeeT
VeeR
VeeR
TD-
TD+
RD+
RD-
VccT
VccR
V
eeT
V
eeR
T
X_Fault
S
D
A
S
CL
M
OD_ABS
R
S0
R
X_LOS
T
X_Disable
R
S1
February 201
1
e
scription
s
abled on high
e
module
n
dicates norma
l
o
upled.
A
C Coupled.
AC Coupled.
C
oupled.
p
ulled up with
a
e
between 2.0
V
X
bias current o
a
tes normal op
e
T
DIS
<0.8V.
7
k – 10kΩ on
h
n
; logic 1 indi
c
l
ock Pin Num
b
20
19
18
17
16
15
14
13
12
11
Tow
a
A
S
I
1
or open.
l
operation.
a
4.7k – 10k
O
V
to Vcc + 0.3
V
r the TX outp
u
e
ration. In the
l
h
ost board to
a
c
ates loss of si
g
b
ers and Na
m
a
rds
I
C
Page
R
O
hms resistor o
V
. A high
u
t power
l
ow state, the
a
voltage
g
nal.
m
es.
2
R
ef.
1
2
3
2
2
2
4
5
4
1
1
1
1
1
n