User Guide

Hardware Functional Overview
4-8 FIC MD02 Service Manual
Ø . Support for standard definition DVD (i.e. NTSC pixel resolution of 720x480, etc.)
quality encoding at low CPU utilization
Video Overlay
Ø . Single high quality scalable overlay and second Sprite to support second overlay
Ø . Multiple overlay functionality provided via arithmetic stretch BLT(Block Transfer)
Ø . 5-tap horizontal, 3-tap vertical filtered scaling
Ø . Multiple overlay formats
Ø . Direct YUV from overlay to TV-out
Ø . Independent gamma correction
Ø . Independent brightness / contrast/ saturation
Ø . Independent tint/hue support
Ø . Destination colorkeying
Ø . Source chromakeying
Multiple hardware color cursor support (32-bit with alpha and legacy 2-bpp mode)
Accompanying I2C and DDC channels provided through multiplexed interface
Display
Ø . Analog display support
• 350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan
analog monitor with pixel resolution up to 1600x1200 at 85 Hz and up to
2048x1536 at 75 Hz
Ø . Dual independent pipe support
• Concurrent: Different images and native display timings on each display device
• Simultaneous: Same images and native display timings on each display device
Ø . DVO (DVOB and DVOC) support
•
Digital video out ports DVOB and DVOC with 165-MHz dot clock on each 12-bit
interface; two 12-bit channels can be combined to form one dual channel 24-bit
interface with an effective dot clock of 330-MHz
• The combined DVO B/C ports as well as individual DVO B/C ports can drive a
variety of DVO devices (TV-Out Encoders, TMDS and LVDS transmitters, etc.)
with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 72 Hz.
• Compliant with DVI Specification 1.0
Ø . Dedicated LFP (local flat panel) LVDS interface
• Single- or dual-channel LVDS panel support up to UXGA panel resolution with
frequency range from 25 MHz to 112 MHz (single channel/dual channel)
•
Supports data format of 18 bpp
• SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external
SSC clock
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear panel fitting
. Tri-view support through LFP interface, DVO B/C port, and CRT
Internal Graphics Features
Ø . Up to 64 MB of dynamic video memory allocation
Ø . Display image rotation
Ø . Graphics core frequency
Ø . Display core frequency at 133 MHz or 200 MHz
Ø . Render core frequency at 100 MHz,133 MHz, 200 MHz
Ø . 2D graphics engine
n Optimized 128-bit BLT engine
n Ten programmable and predefined monochrome patterns
n Alpha Stretch BLT (via 3D pipeline)
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