User Guide

Hardware Functional Overview
FIC MD02 Service Manual 4-11
PCI Interface
The ICH4 PCI interface provides a 33-MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5-V tolerant, except PME#. The ICH4 integrates a PCI arbiter that supports up
to six external PCI bus masters in addition to the internal ICH4 requests.
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard
disks and ATAPI devices. Each IDE device can have independent timings. The IDE
interface supports PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100
Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates
16x32-bit buffers for optimal transfers.
The ICH4’s IDE system contains two independent IDE signal channels. They can be
electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices). There are integrated series resistors on the data and
control lines (see Section 5.15, “IDE Controller (D31:F1)” on page 5-175 for details).
Low Pin Count (LPC) Interface
The ICH4 implements an LPC Interface as described in the LPC 1.0 specification. The Low
Pin Count (LPC) Bridge function of the ICH4 resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, Interrupt Controllers, Timers, Power Management, System Management,
GPIO, and RTC.
Note that in the current chipset platform, the Super I/O (SIO) component has migrated to
the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost
Super I/O designs.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two
of the seven DMA channels can be programmed to support fast Type-F transfers.
The ICH4 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA
DMA. LPC DMA and PC/PCI DMA use the ICH4’s DMA controller. The PC/PCI protocol
allows PCI-based peripherals to initiate DMA cycles by encoding requests and grants via
two PC/PCI REQ#/GNT# pairs.
LPC DMA is handled through the use of the LDRQ# lines from peripherals and special
encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit
channels. Channel 4 is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.31818-MHz oscillator input
provides the clock source for these three counters.
The ICH4 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
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