User Guide

Hardware Functional Overview
4-10 FIC MD02 Service Manual
Hub Interface to ICH4-M
. 266 -MB/s point-to-point Hub Interface to ICH4-M
. 66-MHz base clock
Power Management
Ø . SMRAM space remapping to A0000h (128-kB)
Ø . Supports extended SMRAM space above 256-MB, additional 1-MB TSEG from top
of memory, cacheable (cacheability controlled by CPU)
Ø . APM Rev 1.2 compliant power management
Ø . Supports Suspend to System Memory (S3), Suspend to Disk (S4) and Soft Off (S5)
Ø . ACPI 1.0b, 2.0 support
Ø . Enhanced Intel SpeedStep technology support
Package
. 732-pin Micro-FCBGA (37.5 x 37.5 mm)
4.5.2 Intel ICH4 Features
The ICH4 provides extensive I/O support. Functions and capabilities include:
•PCI Local Bus Specification, Revision 2.2-compliant with support for 33-MHz PCI
operations.
•PCI slots (supports up to 6 Req/Gnt pairs)
•ACPI Power Management Logic Support
•Enhanced DMA Controller, Interrupt Controller, and Timer Functions
•Integrated IDE controller supports Ultra ATA100/66/33
•USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI
high-speed USB 2.0 Host Controller
•Integrated LAN Controller
•System Management Bus (SMBus) Specification, Version 2.0 with additional support
for I2C devices
•Supports Audio Codec ’97, Revision 2.3 specification (a.k.a., AC ’97 Component
Specification, Revision 2.3). Link for Audio and Telephony codecs (up to 7 channels)
•Low Pin Count (LPC) interface
•Firmware Hub (FWH) interface support
•Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)
Hub Architecture
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With AC ’97, USB 2.0, and Ultra ATA/100, coupled with the existing USB, I/O
requirements could impact PCI bus performance. The chipset’s hub interface architecture
ensures that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC ‘97,
USB, etc.), receive adequate bandwidth. By placing the I/O bridge on the hub interface
(instead of PCI), the hub architecture ensures that both the I/O functions integrated into the
ICH4 and the PCI peripherals obtain the bandwidth necessary for peak performance.
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com