User Guide

Software Functional Overview
3-26 FIC MD02 Service Manual
Register Bit Number
Function
Addr
ess
Name
R/W
7 6 5 4 3 2 1 0
Logic
Defau
lt
Description
A5h
*3
BAT2_C
AP
R(/W
)
BCAP - -
0x7F =
Unknown
0x80 = Not
installed
A6h
*3
Reserve
d
R/W Don’t care - -
A7h
SMB_Ale
rt_
ADDR
R/W ADDRESS[6:0]
R
E
S
- 0x00
SMBAlert output
device address
The alert response
function is available
when this register is
cleared (0x00) only.
When the several
devices assert the
alert signal at the
same time, the least
address is stored to
this register. And
when this register
is cleared , next
alert address is
stored to this
register.
A8h
*5
GPIO-A_
EVT_ST
S
R/W STS_A [7:0] 0x00
A9h
*5
GPIO-B_
EVT_ST
S
R/W 0 STS_B [6:0] 0x00
AAh
*5
GPIO-C_
EVT_ST
S
R/W 0 0 0 0 0
0
STS
_C
[1:0]
Read
0:No event
1:EVT
detection
Write
0:Clear
event
1:Ignore
0x00
To clear the notified
event flag without
unexpected event
loss, clear the
corresponding bit
flag only.
For this operation,
this register has
special writing
manner as follows.
STS_X
ß
(STS_X) AND
(Written data)
ABh
*5
RUN_
EVT_ST
S
R/W
B
T
P
S
M
B
A
L
R
G
P
I
R
E
S
B
A
T
B
A
T
A
D
P
Read
0:No event
1:EVT
detection
0x00
BTP2 =1:
SMB
=1 :
BTP2
event is
detected
SMBus
event is
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