User Guide
FIC MB05W Service Manual
FIC MB05 Service Manual 1-79
Controller Chip Vendor Description
Processor Intel Mobile Banias
North Bridge Intel MontaraGM
South Bridge Intel ICH4
Video Controller Intel Embedded in MontaraGM
PCMCIA Controller RICOH R5C554
Supper I/O Controller SMSC LPC47N267
Audio Controller Intel South Bridge Integrated
Audio Codec Realtek ALC201
Keyboard Controller Misubishi M3885x
Power Management NEC PMU08
ROM BIOS SST 49LF004A
Clock Generator IMI CY28346
Temperature Sensor NS MAX1617
IEEE 1394 RICOH R5C554
LAN Realtek 8100BL
Modem ASKEY MDC AC’97
4.4 System Processor (CPU)
The FIC MB05 runs on Intel Banias based on uFCPGA packaging. It supports CPU with up to
1.3/1.5 GHZ clock speed rating. The processor operates in conjunction with the RAM and
ROM memory and the system control logic to process software instructions (BIOS, Windows,
and Applications).
Intel Pentium M Features
The Intel® Pentium® M processor is a high performance, low power mobile processor with
several micro-architectural enhancements over existing Intel mobile processors.
The following list provides some of the key features on this processor:
• Supports Intel® Architecture with Dynamic Execution
• High performance, low-power core
• On-die, primary 32-kbyte instruction cache and 32-kbyte write-back data cache
• On-die, 1-MByte second level cache with Advanced Transfer Cache Architecture
• Advanced Branch Prediction and Data Prefetch Logic
• Streaming SIMD Extensions 2 (SSE2)
• 400-MHz, Source-Synchronous processor system bus
• Advanced Power Management features including Enhanced Intel® SpeedStep® technology
• Micro-FCPGA and Micro-FCBGA packaging technologies
The Intel Pentium M processor is manufactured on Intel’s advanced 0.13 micron process
technology with copper interconnect. The processor maintains support for MMX™ technology
and Internet Streaming SIMD instructions and full compatibility with IA-32 software. The high
performance core features architectural innovations like Micro-op Fusion and Advanced Stack
Management that reduce the number of micro-ops handled by the processor. This results in
more efficient scheduling and better performance at lower power. The on-die 32-kB Level 1
instruction and data caches and the 1-MB Level 2 cache with Advanced Transfer Cache
Architecture enable significant performance improvement over existing mobile processors.
The processor also features a very advanced branch prediction architecture that significantly
reduces the number of mispredicted branches. The processor’s Data Prefetch Logic
speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in
reduced bus cycle penalties and improved performance.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech
recognition.The new packed double-precision floating-point instructions enhance performance
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