User Guide

Hardware Functional Overview
4-6 FIC MB02 Service Manual
4.3 Chipset Summary
The MB02 notebook consists of following major chipsets:
Controller Chip Vendor Description
Processor
Intel Mobile Banias
North Bridge
Intel MontaraGM
South Bridge
Intel ICH4
Video Controller
Intel Embedded in MontaraGM
PCMCIA Controller
RICOH R5C551
Audio Chip
Intel South Bridge Integrated
Audio Codec
Intel ICH4
Keyboard Controller
Misubishi M3885x
PMU Controller
NEC PMU08
ROM BIOS
SST 49LF004A
Clock Generator
IMI CY28346
Temperature Sensor
NS MAX6690
IEE 1394
RICOH R5C551
LAN
Intel ICH4
Modem
Intel MDC AC97
4.4 System Processor (CPU)
The FIC MB02 runs on Intel Banias based on uFCPGA packaging. It supports CPU with
up to 1.3/1.4/1.5/1.6/1.7 GHZ clock speed rating. The processor operates in conjunction
with the RAM and ROM memory and the system control logic to process software
instructions (BIOS, Windows, and Applications).
Intel Pentium M Features
The Intel® Pentium® M processor is a high performance, low power mobile processor
with several micro-architectural enhancements over existing Intel mobile processors.
The following list provides some of the key features on this processor:
Supports Intel® Architecture with Dynamic Execution
High performance, low-power core
On-die, primary 32-kbyte instruction cache and 32-kbyte write-back data cache
On-die, 1-MByte second level cache with Advanced Transfer Cache Architecture
Advanced Branch Prediction and Data Prefetch Logic
Streaming SIMD Extensions 2 (SSE2)
400-MHz, Source-Synchronous processor system bus
Advanced Power Management features including Enhanced Intel® SpeedStep®
technology
Micro-FCPGA and Micro-FCBGA packaging technologies
The Intel Pentium M processor is manufactured on Intels advanced 0.13 micron process
technology with copper interconnect. The processor maintains support for MMX
technology and Internet Streaming SIMD instructions and full compatibility with IA-32
software. The high performance core features architectural innovations like Micro-op
Fusion and Advanced Stack Management that reduce the number of micro-ops handled by
the processor. This results in more efficient scheduling and better performance at lower
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