User Guide

FIRST INTERNATIONAL COMPUTER,
INC.
- -
58
Regist
er
Bit Number
Func
tion
A
dd
re
ss
Name
R/
W
76 54
3
2 1
0
Logic
Def
aul
t
Description
A
5h
*3
BAT2
_CAP
R(/
W)
BCAP - -
A
6h
*3
Reser
ved
R/
W
Don’t care - -
A
7h
SMB_
Alert_
ADD
R
R/
W
ADDRESS[
6:0]
R
E
S
-
0x0
0
SMBAlert output device
address
The alert response
function is available when
this register is cleared
(0x00) only.
When the several devices
assert the alert signal at
the same time, the least
address is stored to this
register. And when this
register is cleared , next
alert address is stored to
this register.
A
8h
*5
GPIO
-A_
EVT_
STS
R/
W
STS_A [7:0]
0x0
0
A
9h
*5
GPIO
-B_
EVT_
STS
R/
W
0STS_B [6:0]
Read
0:No
event
1:EVT
detectio
n
Write
0:Clear
0x0
0
To clear the notified event
flag without unexpected
event loss, clear the
corresponding bit flag
only.
For this operation, this
register has special
writing manner as follows.
STS_X
ß
(STS_X)
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