User Guide

FIC CONFIDENTIAL AND PROPRIETARY
MB02 Functional Specifications Rev. 0.3 Page 73
FIC H/W
FIC CONFIDENTIAL AND PROPRIETARY 11-November-2002_
Built-in 64x64x2 bit-mapped mono hardware cursor
Built-in 64x64x16 bit-mapped blended color hardware cursor
Maxi mum 64MB frame buffer with linear addressing
Supports Ultra-AGP __ TM
2GB/s data read for all 2D engine functions
Complete TV-OUT/Digital Flat Panel Solution
Built-in secondary CRT controller for independent secondary CRT, LCD or TV digital
output
Cooperates with “SiS301B Video Bridge” to support
NTSC/PAL Video Output
Digital LCD Monitor
Secondary CRT Monitor
Supports Dual 12-bit DDR digital interface to TV encoder and LCD transmitter
MPEG-2/1 Video Decoder
MPEG-2 ISO/IEC 13818-2 MP@HL and MPEG-1 ISO/IEC 11172-2 standards
compliant
Built-in advanced hardware DVD acceleration logic
Support AGP bus master/LFB-mode code fetching
Half pixel resolution in motion compensation
Support VCD, DVD and HDTV (all ATSC modes) decoding
Direct DVD to TV playback
Video Accelerator
Supports single frame buffer architecture
Supports single video windows with overlay function
Supports YUV-to-RGB color space conversion
Supports bi-linear video interpolation with integer increments of 1/2048
Supports graphics and video overlay function
Independent graphics and video formats
16 color-key and/or chroma-key operations
Support YUV or RGB format chroma key
Rectangular video window mode
Video only mode
VCD, DVD and up to HDTV playback mode
Supports reading-back of current refresh scan line
Supports tearing free double buffer flipping
Supports RGB555, RGB565, YUV422, and YUV420 video playback format
Supports filtered horizontal up and down scaling playback
Supports DVD sub-picture playback overlay
Supports DVD playback auto-flipping
Built-in two 120x128 video playback line buffers to support 1920x1080 video playback
Built-in independent Gamma correction RAM
Supports DCI Drivers
Supports Direct Draw Drivers
High Integration
Built-in 64x128 CRT FIFOs to support ultra high resolution graphics modes and reduce
CPU wait-state
Built-in programmable 24-bit true-color RAMDAC up to 333 MHz pixel clock
Built-in reference voltage generator and monitor sense circuit
Supports downloadable 24 bits RAMDAC for gamma correction in high color and true
color modes
Support programmable 4 levels DAC current ratio (700, 750, 800, 850 mv)
Support programmable pedestal level (0, 0.75mv)
Support programmable 4 levels slew rate control
Built-in two clock generators
Integrates PLL loop filter for CRT, 2D, 3D, MPEG and VP Engine
Built-in two 120x128 video line buffers for MPEG II video playback
Built-in TV Encoder Interface
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com