User Guide

FIC CONFIDENTIAL AND PROPRIETARY
MB02 Functional Specifications Rev. 0.3 Page 62
FIC H/W
FIC CONFIDENTIAL AND PROPRIETARY 11-November-2002_
7.6 Clock control
7.6.1 Clock synthesizer/driver
The clock synthesizer/driver Cypress CY28346-2
The outputs CPU clocks, Hub clocks, PCI clocks, LVDS clock, USB clock and Peripheral clock.
This register setting is SMBUS Interface.
The register setting is presented as follows.
Bytes 0: CPU Clock Register
Bits Pin# @Pup Description
7 -- 0 Spread Spectrum Enable. 0 = Spread Off, 1 = Spread
On
This is a Read and Write control bit.
6 -- 0 CPU Clock Power-down Mode Select. 0 = Drive
CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2)
LOW when PD# is asserted LOW. 1 = Tri-state all
CPU outputs. This is only applicable when
PD# is LOW. It is not applicable to CPU_STP#.
5 35 0 3V66_1/VCH Frequency Select, 0 = 66M selected, 1
= 48M selected
This is a Read and Write control bit.)
4 44,45,
48,49,
51,52
Pin53 CPU_STP#. Reflects the current value of the external
CPU_STP# (pin 53) This bit is
Read-only.
3 10,11,
12,13,
16,17,
18
Pin34 Reflects the current value of the internal PCI_STP#
function when read. Internally PCI_STP#
is a logical AND function of the internal SMBus
register bit and the external PCI_STP# pin.
2 40 Pin40 Frequency Select Bit 2. Reflects the value of SEL2
(pin 40). This bit is Read-only.
1 55 Pin55 Frequency Select Bit 1. Reflects the value of SEL1
(pin 55). This bit is Read-only.
0 54 Pin54 Frequency Select Bit 0. Reflects the value of SEL0
(pin 54). This bit is Read-only.
Bytes 1: CPU Clock Register
Bits Pin# @Pup Description
7 43 Pin43 MULT0 (Pin 43) Value. This bit is Read-only.
6 53 0 Output Functionality Control When CPU_STP# is
Asserted. 0 = Drive
CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2)
LOW when CPU_STP# asserted LOW.
1 = three-state all CPU outputs. This bit will override
Byte0,Bit6 such that even if it is 0,
when PD# goes LOW the CPU outputs will be three-
stated.
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