User Guide

FIC CONFIDENTIAL AND PROPRIETARY
MB02 Functional Specifications Rev. 0.3 Page 54
FIC H/W
FIC CONFIDENTIAL AND PROPRIETARY 11-November-2002_
0007h r/w DMA1 CH3 Base and Current Count Register ICH4-M INT
0008h r/w DMA1 Status (r) Command (w) Register ICH4-M INT
0009h r/w DMA1 Request Register ICH4-M INT
000Ah r/w DMA1 Command® Write Single Mask Bit(w) Register ICH4-M INT
000Bh r/w DMA1 Mode DMA Register ICH4-M INT
000Ch w/o DMA1 Clear Byte Pointer ICH4-M INT
000Dh w/o DMA1 Master Clear ICH4-M INT
000Eh w/o DMA1 Clear Mask Register ICH4-M INT
000Fh r/w DMA1 Write All Mask Bits(w) Mask Status(r) Register ICH4-M INT
0020h r/w INT 1 Base Address Register ICH4-M INT
0021h r/w INT 1 Mask Register ICH4-M INT
0040h r/w Interval Timer1—Counter 0 ICH4-M INT
0041h r/w Interval Timer1—Counter 1 ICH4-M INT
0042h r/w Interval Timer1—Counter 2 ICH4-M INT
0043h w/o Interval Timer1—Counter Word Register ICH4-M INT
0061h r/w NMI Status Register ICH4-M INT
0070h W/o CMOS RAM Address and NMI Mask Register ICH4-M INT
0071h r/w Real Time Clock Data ICH4-M INT
0072h r/w Real Time Clock Extended Address ICH4-M INT
0073h r/w Real Time Clock Extended Data ICH4-M INT
0080h r/w Reserved ICH4-M WRT
0081h r/w DMA Channel 2 Low Page Register ICH4-M INT
0082h r/w DMA Channel 3 Low Page Register ICH4-M INT
0083h r/w DMA Channel 1 Low Page Register ICH4-M INT
0084h-0086h r/w Reserved ICH4-M WRT
0087h r/w DMA Channel 0 Low Page Register ICH4-M INT
0088 r/w Reserved ICH4-M WRT
0089h r/w DMA Channel 6 Low Page Register ICH4-M INT
008Ah r/w DMA Channel 7 Low Page Register ICH4-M INT
008Bh r/w DMA Channel 5 Low Page register ICH4-M INT
008Ch-008Fh r/w Reserved ICH4-M WRT
0092h r/w System Control Port ICH4-M INT
00A0h r/w INT 2 Control Register ICH4-M INT
00A1h r/w INT 2 Mask Register ICH4-M INT
00B2h r/w Advanced Power Management Control Port ICH4-M INT
00B3h r/w Advanced Power Management Status Port ICH4-M INT
00C0h r/w DMA2 CH0 Base and Current Address Register ICH4-M INT
00C2h r/w DMA2 CH0 Base and Current Count Register ICH4-M INT
00C4h r/w DMA2 CH1 Base and Current Address Register ICH4-M INT
00C6h r/w DMA2 CH1 Base and Current Count Register ICH4-M INT
00C8h r/w DMA2 CH2 Base and Current Address Register ICH4-M INT
00CAh r/w DMA2 CH2 Base and Current Count Register ICH4-M INT
00CCh r/w DMA2 CH3 Base and Current Address Register ICH4-M INT
00CEh r/w DMA2 CH3 Base and Current Count Register ICH4-M INT
00D0h r/w DMA2 Status (r) Command (w) Register ICH4-M INT
00D2h r/w DMA2 Request Register ICH4-M INT
00D4h r/w DMA2 Command(r) Write Single Mask Bit(w) Register ICH4-M INT
00D6h r/w DMA2 Mode Register ICH4-M INT
00D8h w/o DMA2 Clear Byte Pointer ICH4-M INT
00DAh w/o DMA2 Master Clear ICH4-M INT
00DCh w/o DMA2 Clear Mask register ICH4-M INT
00DEh r/w DMA2 Write All Mask Bits(w) Mask Status Register(r) ICH4-M INT
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