User Guide

FIC CONFIDENTIAL AND PROPRIETARY
MB02 Functional Specifications Rev. 0.3 Page 30
FIC H/W
FIC CONFIDENTIAL AND PROPRIETARY 11-November-2002_
5.3 How to access SPD
Please construct the memory reading Serial Presence Detect data.
Byte number and the function are described to the following tables.
Among byte numbers which have been described to this table, please do not collate following
byte.
Because, the reason is that a value different in each maker is described because configuration
of a peculiar regulated value and memory to the maker is various.
Serial Presence Detect EEPROM Data Format
Byte
Number
Function Required
/Optional
Don’t Care
0 Defines # of bytes written into serial memory at module manufacturer Required
1 Total # of bytes of SPD memory device Required
2 Fundamental memory type (FPM, EDO, SDRAM..) from Appendix A Required
3 # of row address on this assembly (includes Mixed-size Row address) Required Don’t care
4 # Column Address on this assembly (includes Mixed-size Col address) Required Don’t care
5 #Module Rows on this assembly Required Don’t care
6 Data Width of this assembly Required
7 … Data Width continuation Required
8 Voltage interface standard of this assembly Required
9 SDRAM Cycle time, CL=X (highest CAS latency) Required
10 SDRAM Access from Clock (highest CAS latency) Required Don’t care
11 DIMM Configuration type (non-parity, ECC) Required
12 Refresh Rate/Type Required
13 Primary SDRAM Width Required Don’t care
14 Error Checking SDRAM Width Required
15 Minimum Clock Delay Back to Back Random Column Address Required*
16 Burst Lengths Supported Required*
17 # of Banks on Each SDRAM Device Required* Don’t care
18 CAS# Latencies Supported Required*
19 CS# Latency Required*
20 Write Latency Required*
21 SDRAM Module Attributes Required*
22 SDRAM Device Attributes: General Required*
23 Min SDRAM Cycle time at CL X-1 (2
nd
highest CAS latency) Required*
24 Max SDRAM Access from Clock at CL X-1 (2
nd
highest CAS latency) Required* Don’t care
25 Min SDRAM Cycle time at CL X-2 (3
rd
highest CAS latency) Optional* Don’t care
26 Max SDRAM Access from Clock at CL X-2 (3
rd
highest CAS latency) Optional* Don’t care
27 Min Row Precharge Time (Trp) Required*
28 Min Row Active to Row Active (Trrd) Required*
29 Min RAS to CAS Delay (Trcd) Required*
30 Minimum RAS Pulse Width (Tras) Required*
31 Density of each row on module (mixed, non-mixed size) Required
32-61 Superset Information (may be used in future) Required
62 SPD Data Revision Code Required Don’t care
63 Checksum for bytes 0-62 Required Don’t care
64-71 Manufacturer’s JEDEC ID code per JEP-108E Optional Don’t care
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