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Hardware Functional Overview

FIC M785 Service Manual 4-1

Chapter

4.1 Overview

The FIC M785 notebook consists of several important functions and subsystems including:

• System Processor – implemented on the motherboard using the Intel uFCPGA DT

Pentium 4 Northwood at 400/533 MHz Front System Bus speed.

• System North Bridge Core Logic – implemented on the motherboard using the SIS

650 chipset.

- CPU Interface

- AGP BUS Controller

- DDR DRAM Controller

- MuTIOL Media I/O

• System South Bridge Core Logic – implemented on the motherboard using the SIS

962 chipset.

- Integrated MuTIOL Connect to PCI Bridge

- Dual IDE Master/Slave Controller, Integrated DMA

• Clock Frequency Generator – implemented on the motherboard using the ICS 952001

clock generator chip.

• Cache Memory Subsystem – implemented on-die on the Intel CPU.

- L1 cache (Pentium Processor Internal)

- 12KB code and 8KB data, which implemented 8 way set associative and write

back

- L2 cache (Pentium Processor Internal)

- 256KB Advanced Transfer Cache,8 way associativity

- 8-way set associative, 32-byte line size, 1 line per sector

• Video Subsystem – embedded in SIS 650

- High Performance and high quality 3D accelerator

- Integrated VB bridge

- High performance 2D accelerator

- Complete TV-OUT/Digital Flat Panel Solution

• VRAM – embedded in SIS 650

- Share system memory from 8MB up to 64MB

• PCMCIA Subsystem – implemented on the motherboard using the ENE CB1410

PCI-CARDBUS BRIDGE controller chip.

- Support Type II x2 (without door)

• Sound – implemented or integrated in south bridge (SIS 962)

- AC’97 CODEC

- Realtek ALC201

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Summary of content (20 pages)

PAGE 1
Chapter Hardware Functional Overview 4.1 Overview The FIC M785 notebook consists of several important functions and subsystems including: • System Processor – implemented on the motherboard using the Intel uFCPGA DT Pentium 4 Northwood at 400/533 MHz Front System Bus speed. • System North Bridge Core Logic – implemented on the motherboard using the SIS 650 chipset.
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Hardware Functional Overview • AC’97 Revision 2.1 Compliant USB and Bluetooth – implemented or integrated in south bridge (SIS 962) - USB v2.0 and Intel Universal HCI v.1.
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Hardware Functional Overview 4.2 System Hardware Block Diagram Figure 4-1 M785 Diagram FIC M785 Service Manual PDF created with FinePrint pdfFactory Pro trial version http://www.pdffactory.
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Hardware Functional Overview 4.3 Chipset Summary The M785 notebook consists of following major chipsets: Controller Chip Processor Core Logic Video Controller PCMCIA Controller Supper I/O Controller Audio Chip Sound Codec Chip Keyboard Controller PMU Controller Gas Gauge IC ROM BIOS Vendor Intel SIS Embedded in SIS 650 ENE SMSC Embedded in SIS 962 Realtek EME Mitsubishi Description uFCPGA Northwood DT Pentium 4 2.0/2.2/2.26/2.4/2.
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Hardware Functional Overview • Supported by the Intel® 850 and Intel® 845 chipset families • Compatible with existing Intel® Architecture-based software • Streaming SIMD Extensions 2 (SSE2) Instructions • Intel® MMX™ media enhancement technology • Integrated caches include 12-K micro-op trace cache and 8-KB L1 data cache in addition to L2 cache memory • Support for uni-processor designs • Based upon Intel's leading 0.13 micron and 0.18 micron manufacturing process technologies. 0.
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Hardware Functional Overview Level 1 Execution Trace Cache In addition to the 8-KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12-K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored.
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Hardware Functional Overview Streaming SIMD Extensions 2 (SSE2) Instructions With the introduction of SSE2, the Intel NetBurst microarchitecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations.
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Hardware Functional Overview Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS962 An Unified Memory Controller supporting DDR200/266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters.
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Hardware Functional Overview • • • • • Programmable buffer strength optimi zing performance and stability Dynamic Clock Enable(CKE) control placing the SDRAM into Suspend to DRAM state High performance unified memory controller optimi zing the DRAM bus utilization Programmable frame buffer size from 8MB and up to 64MB 128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge • • • • • • • AGP v2.
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Hardware Functional Overview − − − − − − − − − − Supports rectangle structure texture Supports 16/24/32 bpp RGB/ARGB texture format Supports DTX1, DTX2, DTX3 texture compression formats Supports texture transparency, blending, wrapping, mirror, and clamping Supports fogging, alpha blending Supports vertex fogging and fog table Supports specular lighting Supports 2X/4X multi-sampling full scene anti-aliasing Supports back face culling Supports auto-stereo rendering High Performance 2D Accelerator • • • •
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Hardware Functional Overview • • • • CPU wait-state Built-in programmable 24-bit true-color RAMDAC up to 333 MHz pixel clock − Built-in reference voltage generator and monitor sense circuit − Supports downloadable 24 bits RAMDAC for gamma correction in high color and true color modes − Support programmable 4 levels DAC current ratio (700, 750, 800, 850 mv) − Support programmable pedestal level (0, 0.
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Hardware Functional Overview The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4, and Ultra DMA 66/100/133.
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Hardware Functional Overview Dual IDE Master/Slave Controller • • • • • Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming Dual Independent IDE Channels Each with 16 DW FIFO Native and Compatibility Mode PIO Mode 0, 1, 2, 3, 4 and Multiword DMA Mode 0, 1, 2 Ultra DMA 66/100/133 Universal Serial Bus Host Controller • • • • • • Integrated Multithreaded IO Link Mastering Dual Independent OHCI Controllers with Root Hub Supports up to 6 USB 2.0/1.
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Hardware Functional Overview • • • Password Security and Password Power-Up System Sleep and Power-Up by Hot-Key KBC and PS2 Mouse Can Be Individually Disabled Integrated PCI to LPC Bridge • LPC 1.0 Compliance Integrated Real Time Clock (RTC) with 256B CMOS SRAM • • • Supports ACPI Day-of-Month and Month-of-Year Alarm 256 Bytes of CMOS SRAM Provides RTC H/W Year 2000 Solution 4.6 Clock Frequency Generator The notebook utilizes the ICS 952001 chip to supply the system clock needed to run the computer.
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Hardware Functional Overview 4.8.2 Video Memory The video memory of the notebook is embedded inside the VGA controller chip (SIS 650) with 16,32 and 64MB SMA video memory that can support display resolutions of up to 1024 x 768 at 32-bit 16M color (TFT LCD). 4.9 System BIOS The notebook utilizes the Phoenix BIOS 4.0 Release 6.0 (Basic I/O System) that contains both the main system BIOS and the VGA BIOS with Shadow BIOS capability.
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Hardware Functional Overview • • • • • • • • − Support YUV or RGB format chroma key − Rectangular video window mode − Video only mode − VCD, DVD and up to HDTV playback mode − Supports reading-back of current refresh scan line − Supports tearing free double buffer flipping Supports RGB555, RGB565, YUV422, and YUV420 video playback format Supports filtered horizontal up and down scaling playback Supports DVD sub-picture playback overlay Supports DVD playback auto-flipping Built-in two 120x128 video playbac
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Hardware Functional Overview The CB1410 is fully complains with the 33Mhz PCI Bus specification, v2.2. It supports a master device with internal CardBus direct data transfer. The CB1410 implements FIFO data buffer architecture between the PCI bus and CardBus socket interface to enhance data transfers to CardBus Devices. The bi-directional FIFO buffer permits the CB1410 to accept data from a target bus (PCI or CardBus interface) while simultaneously transferring data.
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Hardware Functional Overview additional buffers; 3V card protection during host system suspend with Auto Card VS# resensing; dedicated ZV output port to LCD controller SmartCardBus™ (OZ711E1/OZ711E2) combines a Smart Card reader and CardBus controller in a single IC. In addition to meeting PC Card standards, SmartCardBus is compliant to Microsoft PC/SC, ISO 7816-1, -2, -3 electrical specifications, standard protocols including T = 0, T = 1, and synchronous and asynchronous formats.
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Hardware Functional Overview The Synaptic touch pad communicates with the host via a standard PS/2 mouse or trackball interface. It is fully compatible with the standard Microsoft mouse driver. The module connector includes the PS/2 signal pins, power supply pins and two connections for external button switches. The Synaptic touch pad includes a special “edge-motion” feature that allows the user to extend a drag operation when the finger reaches the edge of the sensor pad.
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Hardware Functional Overview 4.15.3 DC-DC Module of Motherboard The DC-DC module receives approximately 12VDC from the battery pack and uses this input voltage to generate multiple regulated output voltages to provide power for all internal notebook board assemblies. 4.15.4 LCD Inverter Board Assembly The LCD Inverter Board Assembly is located in the LCD Panel Assembly.