User Guide

Hardware Functional Overview
4-6 FIC A985 Service Manual
4.5 System Core Logic
The system core logic function of the notebook is implemented on the CPU module and
motherboard using the SiS650 IGUI HMAC. SiS650 IGUI Host Memory Controller
integrates a high performance host interface for Intel Pentium 4 processor, a high
performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO. SiS650
Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated
on-die termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-
Order-Queue to support maximum outstanding transactions up to 12. It integrated a high
performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware
Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC
systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain
t he bandwidth demand from t he integrated GUI or external AGP master, host processor, as
well as the multi I/O masters. In addition to integrated GUI, SiS650 also can support external
AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and
mat ure SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL
Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-t
hreaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master
devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-t
hreaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidt h
from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-t hreaded I/O Link
Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link
layer to/from SiS961
An Unified Memory Controller supporting DDR200/266 DRAM is incorporated, delivering a
high performance data transfer to/from memory subsystem from/to the Host processor, the
integrated graphic engine or external AGP master, or the I/O bus masters. The memory
controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in
ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the Shared
Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated
from 8MB to 64MB.
4.5.1 SiS650 IGUI HMAC 3D Graphic Chipset Features
The SiS650 chipset is ideal for the high performance, high quality, high energy efficient and
high integration notebook AGP / PCI / ISA computer systems. The Integrated GUI features a
high performance 3D accelerator with 2 Pixel / 4 Text ure, and a 128 bit 2D accelerator with
1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware
acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video
link interfaced to SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to
expand the SiS 650 functionality to support the secondary display, in addition to the default
primary CRT display. The SiS 301B Video Bridge integrates an NTSL/PAL video encoder
with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear
scaling capability for TFT LCD panel support, and an analog RGB port to support a
secondary CRT. The primary CRT display and the extended secondary display (TV, TFT
LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that both can generate
the display in independent resolutions, color depths, and frame rates.
The SiS650 functions and capabilities include:
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com