User Guide

Software Functional Overview
3-32 FIC A985 Service Manual
l Device PM control during STD mode
Device
Power Down
Controlled by
Description
SIS 650 Core Logic Hardware Power off
Super I/O Hardware Power off
VGA Chip Hardware Power off
HDD Hardware Power off
CD-ROM Hardware Power off
PCMCIA Controller Hardware Power off
LAN Hardware Power off
FDD Hardware Power off
Audio Chip Hardware Power off
Audio AMP Hardware Power off
LCD Panel Hardware Power off
Backlight Software Controlled by BIOS set PMU08
Clock Synthesizer Hardware Power off
Keyboard Controller Hardware Power off
MAX3243(RS232 transceiver ) Hardware Power off
L2 Cache Hardware Power off
PMU08 Software Controlled by SUSC#
l The power plane is divided as following:
Power Group
Power
Control Pin
Controlled Devices
CPU Core SUSB# CPU’s Core Part
CPU I/O SUSB#
CPU’s I/O Part, SRAM, SIS 650(CPU I/F), Clock
Generator(CPU Clock)
+3V PWRON
VGA, VideoRAM, PCMCIA, PCMCIA Slot 3V, DRAM,
SIS 650(DRAM I/F), MAX32443
+3VS SUSB#
Flash ROM, Audio, SIS 961(LPC I/F Power), Clock
Generator (IMI9827G SCLK), TAG RAM
+5V PWRON PCMCIA Slot 5V VCC, M38867
+5VS SUSB#
Super I/O, HDD, CD-ROM, USB, LPT Port, Internal K/B,
Glide Pad, External P/S2 Mouse, IR, FDD, Audio AMP
+3V Always Nil uP (PMU08), SIS 961(RTC I/F)
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