Hardware Guide

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FIBOCOM MC116-NA Series Hardware Guide Page 39 of 63
Parameter Min Typ Max Unit
t(clk) PCM_CLK cycle time – 488 – ns
t(clkh) PCM_CLK high time – 244 – ns
t(clkl) PCM_CLK low time – 244 – ns
t(susync)
PCM_SYNC offset time to PCM_CLK
falling
– 122 – ns
t(sudin) PCM_DIN setup time to PCM_CLK falling 60 – – ns
t(hdin) PCM_DIN hold time after PCM_CLK falling 10 – – ns
t(pdout)
Delay from PCM_CLK rising to
PCM_DOUT valid
– – 60 ns
t(zdout)
Delay from PCM_CLK falling to
PCM_DOUT high impedance
– 160 – ns