User's Manual

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L850-GL Hardware User Manual Page
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Figure 3-9 Reference Circuit for PCIe Interface
L850 module supports one PCIe 1.0 interface, including three difference pairs: transmit pair TXP/N,
receiving pair RXP/N and clock pair CLKP/N.
PCIe can achieve the maximum transmission rate of 2.5 GT/s, and must strictly follow the rules below in
PCB Layout:

The differential signal pair lines shall be parallel and equal in length;

The differential signal pair lines shall be short if possible and be controlled within 500mm for AP end;
The impedance of differential signal pair lines is recommended to be 100 ohm, and can be
controlled to 80～120 ohm in accordance with PCIe protocol;

It shall avoid the discontinuous reference ground, such as segment and space;
When the differential signal lines go through different layers, the via hole of grounding signal should
be in close to that of signal, and generally, each pair of signals require 1-3 grounding signal via
holes and the lines shall never cross the segment of plane;
Try to avoid bended lines and avoid introducing common-mode noise in the system, which will
influence the signal integrity and EMI of difference pair. As shown in Figure 3-10, the bending
angle of all lines should be equal or greater than 135 ° , the spacing between difference pair
lines should be larger than 20mil, and the line caused by bending should be greater than 1.5
times line width at least. When a serpentine line is used for length match with another line, the
bended length of each segment shall be at least 3 times the line width ( ≥ 3W). The largest
spacing between the bended part of the serpentine line and another one of the differential lines
must be less than 2 times the spacing of normal differential lines (S1<2S);