User's Manual

Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
L850-GL Hardware User Manual Page
19
of
51
Pin
Pin Name
I/O
Reset Value
Pin Description
Type
44
GNSS_IRQ
I
PD
GNSS Interrupt Request,
Reserved
CMOS 1.8V
45
GND
GND
Power Supply
46
SYSCLK
O
PD
26M clock output
1.8V
47
PERn0
I
PCIe RX Differential signals
Negative
48
TX_BLANKING
O
PD
PA Blanking Timer
CMOS 1.8V
49
PERp0
I
PCIe RX Differential signals Positive
50
PERST#
I
T
PE-Reset is a functional reset to the
Add-In card as defined by the PCIe Mini
Card CEM specification
CMOS 3.3V
51
GND
GND
Power Supply
52
CLKREQ#
O
T
Clock Request is a reference clock
request signal as defined by the PCIe
Mini Card CEM specification; Also used
by L1 PM Substates
CMOS 3.3V
53
REFCLKN
I
PCIe Reference Clock signal
Negative
54
PEWAKE#
O
L
PCIe PME Wake. Open Drain with pull
up on platform,active low
CMOS 3.3V
55
REFCLKP
I
PCIe Reference Clock signal
Positive
56
RFE_RFFE2_
SCLK
O
MIPI Interface Tunable ANT,
RFFE2 clock,Open Drain output
CMOS
3.3/1.8V
57
GND
GND
Power Supply
58
RFE_RFFE2_
SDATA
O
MIPI Interface Tunable ANT,
RFFE2 data,Open Drain output
CMOS
3.3/1.8V
59
ANTCTL0
O
Tunable ANT CTRL0
CMOS 1.8V
60
COEX3
O
PD
Wireless Coexistence between WWAN
and WiFi/BT modules. IDC_UART_TXD,
Reserved
CMOS
3.3/1.8V
61
ANTCTL1
O
Tunable ANT CTRL1
CMOS 1.8V
62
COEX2
I
T
Wireless Coexistence between WWAN
and WiFi/BT modules, IDC_UART_RXD
CMOS 1.8V