User's Manual

H350 LGA Serials Module Hardware User Manual Page of
43
38
5.7.3 PCM Mode Interface
H350 Signal Direction Audio CODEC PCM Port
I2S2_CLK0 (PCM_CLK, PCM clock signal )
PCM_CLK (PCM clock signal)
I2S2_WA0 (PCM_SYNC, PCM frame
synchronization signal )
PCM_SYNC (PCM frame
synchronization signal )
I2S2_RX (PCM_DIN, PCM data input) PCM_DOUT (PCM data output)
I2S2_TX (PCM_DOUT, PCM data output) PCM_DIN (PCM data input)
Note:
 PCM mode can configured to master mode and slave mode

It supports short frame synchronization for 16 bit, 32bit, 48bit and 64bit.

Supports sending data in burst mode and continuous mode
 It supports various audio sample rates (48 KHz, 44.1 KHz, 32 KHz, 24 KHz, 22.5 KHz, 16 KHz, 12
KHz, 11.025 KHz and 8 KHz).
5.8 ADC Interface
H350 supports ADC detection, with accuracy to 10 bit. The input voltage requirement for ADC: 0~1.2V.
The following table shows the ADC signal description:
Pin# Pin Name I/O Description
41 ADC1 I ADC input
5.9 GPS_BLANKING
The defaulted-value is low level (output). When module works with GSM network, pin GPS Blanking and
pin GSM burst will output same pulse signal. Because GSM TX may interfere with GPS RX, AP will close
or stop GPS RX when AP detects GPS Blanking signal.